ST7538Q
FSK power line transceiver
General features
Half duplex frequency shift keying (FSK) transceiver Integrated power line driver with programmable voltage and current control Programmable interface: Synchronous Asynchronous Single supply voltage (from 7.5 up to 12.5V) Very low power consumption (Iq = 5mA) Integrated 5V voltage regulator (up to 50mA) with short circuit protection Integrated 3.3V voltage regulator (up to 50mA) with short circuit protection 3.3V or 5V digital supply 8 programmable transmission frequencies Programmable baud rate up to 4800BPS Receiving sensitivity up to 250Vrms Suitable to application in accordance with EN 50065 CENELEC specifications Carrier or preamble detection Band in use detection Programmable 24 or 48 bit register with security checksum Mains zero crossing detection and synchronization Watchdog timer Output voltage freeze 8 or 16 bit header recognition UART/SPI host interface ST7537 compatible
TQFP44 Slug Down
Description
The ST7538Q is a Half Duplex synchronous/asynchronous FSK Modem designed for power line communication network applications. It operates from a single supply voltage and integrates a line driver and two linear regulators for 5V and 3.3V. The device operation is controlled by means of an internal register, programmable through the synchronous serial interface. Additional functions as watchdog, clock output, output voltage and current control, preamble detection, time-out, band in use are included. Realized in Multipower BCD5 technology that allows to integrate DMOS, Bipolar and CMOS structures in the same chip.
Order codes
Part number ST7538Q ST7538QTR July 2006 Package TQFP44 Slug Down TQFP44 Slug Down Rev 1 Packaging Tube Tape and reel 1/44
www.st.com 44
Contents
ST7538Q
Contents
1 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 2.2 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1 3.2 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4 5
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1 5.2 5.3 5.4 5.5 5.6 5.7 Carrier frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Baud rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Mark and space frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 ST7538Q mains access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Host processor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.5.1 Communication between host and ST7538Q . . . . . . . . . . . . . . . . . . . . 20
Control register access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Receiving mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.7.1 5.7.2 5.7.3 5.7.4 High sensitivity mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Synchronization recovery system (PLL) . . . . . . . . . . . . . . . . . . . . . . . . 23 Carrier/preamble detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Header recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.8 5.9 5.10 5.11
Transmission mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.8.1 Automatic Level Control (ALC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Detection method and Rx Sensitivity in UART mode . . . . . . . . . . . . . . . . 35
2/44
ST7538Q
Contents
6
Auxiliary analog and digital functions . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.12 Band in use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Time out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Reset & watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Zero crossing detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Output clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Output voltage level freeze . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Extended control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Reg OK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Under voltage lock out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5V and 3.3V voltage regulators and power good function . . . . . . . . . . . . 39 Power-up procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7 8
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3/44
Block diagram
ST7538Q
1
Figure 1.
Block diagram
Block diagram
AVdd AVss
TEST1
TEST2
BU
RxFo
CD/PD
CARRIER DETECTION
TEST
BU AGC
RxD CLR/T PLL DIGITAL FILTER FSK DEMOD IF FILTER FILTER AMPL UART/SPI REG/DATA RxTx TxD FSK MODULATOR DAC TX FILTER ALC VOLTAGE CONTROL PLI Vsense ATO ATOP1 ATOP2 + VREG PAVcc Vdc PG RAI SERIAL INTERFACE FILTER CONTROL REGISTER CURRENT CONTROL CL
REGOK
OSC
TIME BASE
ZC
OP-AMP
XOut
XIn
WD
TOUT
RSTO
MCLK ZCout
ZCin C_OUT
CMINUS CPLUS
DVdd DVss
D03IN1407A
4/44
ST7538Q
Pin settings
2
2.1
Pin settings
Pin connection
Figure 2. Pin Connection (Top view)
REG_DATA C_MINUS C_OUT C_PLUS REG_OK
GND
TEST1
35
N.C.
PG
44
43
42
41
40
N.C.
39
38
37
36
CD_PD DVSS RXD RxTx TXD GND TOUT CLR/T BU DVDD MCLK
N.C.
34 33 32 31 30 29 28 27 26 25 24 23
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
VDC RAI RXFO TEST2 VSENSE AVDD XIN XOUT SGND ATO CL
RSTO
UART/SPI
WD
ZCOUT
ZCIN
N.C.
DVSS
ATOP1
PAVSS
ATOP2
PAVCC
D01IN1312
5/44
Pin settings
ST7538Q
2.2
Pin N 1
Pin description
Name CD_PD Type Digital/Output Description Carrier, Preamble or Frame Header Detect Output. "1" No Carrier, Preamble or Frame Header Detected "0" Carrier, Preamble or Frame Header Detected Digital Ground RX Data Output. Rx or Tx mode selection input. "1" - RX Session "0" - TX Session
Table 1. Pin description
2 3 4
DVss RxD RxTx
Supply Digital/Output Digital/Input with internal pull-up
5 6 7
TxD GND TOUT
Digital/Input TX Data Input. with internal pull-down Supply Digital/Output Substrate Ground (same function as PIN 41) TX Time Out Event Detection "1" - Time Out Event Occurred "0" - No Time-out Event Occurred Synchronous Mains Access Clock or Control Register Access Clock Band in use Output. "1" Signal within the Programmed Band "0" No Signal within the Programmed Band Digital Supply Voltage or 3.3V Voltage Regulator Output Master Clock Output Power On or Watchdog Reset Output
8 9
CLR/T BU
Digital/Output Digital/Output
10 11 12 13
DVdd MCLK RSTO UART/SPI
Supply Digital/Output Digital/Output
Digital/Input Interface type: with internal pull-down "0" - Serial Peripheral Interface "1" - UART Interface Digital/Input with internal pull-up Digital/Output Analog/Input Floating Supply Power/Output Supply Power/Output Supply Analog/Input Watchdog input. The Internal Watchdog Counter is cleared on the falling edges. Zero Crossing Detection Output Zero Crossing AC Input. Must be connected to DVss. Digital Ground Power Line Driver Output Power Analog Ground Power Line Driver Output Power Supply Voltage Current Limiting Feedback. A resistor between CL and AVss sets the PLI Current Limiting Value An integrated 80pF filtering input capacitance is present on this pin Small Signal Analog Transmit Output
14 15 16 17 18 19 20 21 22 23
WD ZCOUT ZCIN(1) NC DVss ATOP1 PAVss ATOP2 PAVCC CL(2)
24
ATO
Analog/Output
6/44
ST7538Q Table 1. Pin description (continued)
Pin N 25 26 27 28 29 30 31 32 33 34 35 36 Name SGND XOUT XIN AVdd Vsense(3) TEST2 RxFO RAI VDC NC TEST1 REGOK Supply Analog Output Analog Input Supply Analog/Input Analog/Input Analog/Output Analog/Input Power floating Type Analog Signal Ground Crystal Output Crystal Oscillator Input - External Clock Input Analog Power supply. Description
Pin settings
Output Voltage Sensing input for the voltage control loop Test Input must be connected SGND Receiving Filter Output Receiving Analog Input 5V Voltage Regulator Output Must Be connected to DVss.
Digital/Input Test input. Must Be connected to DVss. with internal pull-down Digital/Output Security checksum logic output "1" - Stored data Corrupted "0" - Stored data OK Op-amp Inverting Input. Op-amp Not Inverting Input. Must Be connected to DVss Op-amp Output Substrate Ground (same function as PIN 6) Power Good logic Output "1" - VDC is above 4.5V and DVdd is above 3.125V "0" - VDC is below 4.25V or DVdd is below 2.875V
37 38 39 40 41 42
C_MINUS(4) Analog/Input C_PLUS(5) NC C_OUT GND PG Analog/Input floating Analog/Output Supply Digital/Output
43
REG_DATA Digital/Input Mains or Control Register Access Selector with internal pull-down "1" - Control Register Access "0" - Mains Access NC floating Must be connected to DVss.
44
1. If not used this pin must be connected to VDC 2. Cannot be left floating 3. Cannot be left floating 4. If not used this pin must be connected to VDC 5. If not used this pin must be tied low (SGND or PAVss or DVss)
7/44
Electrical data
ST7538Q
3
3.1
Electrical data
Maximum ratings
Table 2. Absolute maximum ratings
Symbol PAVCC AVdd DVdd Parameter Power Supply Voltage Analog Supply Voltage Digital Supply Voltage Value -0.3 to +14 -0.3 to +5.5 -0.3 to +5.5 -0.3 to +0.3 DVss - 0.3 to DVdd +0.3 DVss - 0.3 to DVdd +0.3 -2 to +2 Unit V V V V V V mA
AVss/DVss Voltage between AVss and DVss VI VO IO Digital input Voltage Digital output Voltage Digital Output Current
Vsense, XIN, Voltage Range at Vsense, XIN, C_MINUS, C_MINUS C_PLUS, CL Inputs ,C_PLUS, CL RAI, ZCIN ATO, RxFO, C_OUT, XOUT Voltage Range at RAI, ZCIN Inputs
AVss - 0.3 to AVdd+0.3
V
-AVdd - 0.3 to AVdd +0.3
V
Voltage range at ATO, RxFO, C_OUT, XOUT Outputs
AVss - 0.3 to AVdd +0.3
V
ATOP1,2 Voltage range at Powered ATO Output ATOP Tamb Tstg CD_PD Pin Other pins Powered ATO Output Current (1) Operating ambient Temperature Storage Temperature Maximum Withstanding Voltage Range Test Condition: CDF-AEC-Q100-002- "Human Body Model" Acceptance Criteria: "Normal Performance"
AVss - 0.3 to +PAVcc +0.3 400 -40 to +85 -50 to 150 1500 2000
V mArms C C V V
1. This current is intended as not repetitive pulse current
8/44
ST7538Q
Electrical characteristics
3.2
Thermal data
Table 3. Thermal data
Symbol RthJA1 RthJA2 Parameter Maximum Thermal Resistance Junction-Ambient Steady state (1) Maximum Thermal Resistance Junction-Ambient Steady state (2) TQFP44 with slug 35 50 Unit C/W C/W
1. Mounted on Multilayer PCB with a dissipating surface on the bottom side of the PCB 2. It's the same condition of the point above, without any heatsinking surface on the board.
4
Electrical characteristics
Table 4. Electrical characteristics (AVdd = DVdd = +5V, PAVcc =+9 V, PAVss, SGND = DVss = 0V, -40C TA 85C, TJ < 125 C, fc = 86kHz, other control register parameters as default value, unless otherwise specified)
Symbol AVdd, DVdd Parameter Supply voltages DVdd < 4.75V with 5V Digital supply provided externally AVdd < 4.75V Test condition Min 4.75 0.1 Typ 5 Max 5.25 1.2 Unit V V
PAVCC and DVdd Relation PAVdd - DVdd during Power-Up Sequence PAVCC and AVdd Relation PAVCC - AVdd during Power-Up Sequence Power Supply Voltage PAVcc Max allowed slope during Power-Up Input Supply Current
0.1 7.5
1.2 12.5 100
V V V/ms mA mArms A mArms V mV
AIdd + DIdd
Transmission & Receiving mode TX mode (no load)
5 30 500
7 50 1000 370
I PAVCC
Powered Analog Supply Current Input Under Voltage Lock Out Threshold on PAVcc UVLO Hysteresis
RX mode Maximum total current
UVLO UVLOHYS Digital I/O Rdown Rup
3.7
3.9 340
4.1
Pull Down Resistor Pull up Resistor
100 100
k k 9/44
Electrical characteristics
ST7538Q
Table 4. Electrical characteristics (continued) (AVdd = DVdd = +5V, PAVcc =+9 V, PAVss, SGND = DVss = 0V, -40C TA 85C, TJ < 125 C, fc = 86kHz, other control register parameters as default value, unless otherwise specified)
Symbol Parameter Test condition Min Typ Max Unit
Digital I/O 5V digital supply VIH VIL VOH VOL High Logic Level Input Voltage Low Logic Level input Voltage High Logic Level Output Voltage Low Logic Level Output Voltage IOH= -2mA IOL= 2mA DVdd -0.75 DVss + 0.3 2 1.2 V V V V
Digital I/O 3.3V digital supply VIH VIL VOH VOL Oscillator XINSWING XINOFFSET DC Xtal Tclock XtalESR XtalCL Transmitter IATO VATO VATODC Output Transmitting Current on ATO Max Carrier Output AC Voltage Output DC Voltage on ATO RCL = 1.75k Vsense(AC) = 0V 1.75 1.7 2.3 2.1 1 3.5 2.5 mArms VPP V XIN Input Voltage swing XIN Input Voltage offset XTAL Clock Duty Cycle Crystal Oscillator frequency Oscillator Period (1/Xtal) External Oscillator Esr Resistance External Oscillator Stabilization Capacitance External Clock. Figure 19 External Clock. Figure 19 External Clock. Figure 19 Fundamental 40 16 62.5 40 16 5 2.5 60 V V % MHz ns pF High Logic Level Input Voltage Low Logic Level input Voltage High Logic Level Output Voltage Low Logic Level Output Voltage IOH= -2mA IOL= 2mA DVdd -0.75 DVss + 0.4 1.4 0.8 V V V V
10/44
ST7538Q
Electrical characteristics
Table 4. Electrical characteristics (continued) (AVdd = DVdd = +5V, PAVcc =+9 V, PAVss, SGND = DVss = 0V, -40C TA 85C, TJ < 125 C, fc = 86kHz, other control register parameters as default value, unless otherwise specified)
Symbol HD2ATO HD3ATO Parameter Second Harmonic Distortion on ATO Third Harmonic Distortion on ATO Output Transmitting Current in programmable current limiting Max Carrier Output AC Voltage for each ATOP1 and ATOP2 pins Output DC Voltage on ATOP1 and ATOP2 pins VATOP = 4VPP , PAVCC = 10V No Load HD2ATOP Second Harmonic Distortion on each ATOP1 and ATOP2 pins VATOP = 4VPP , PAVCC = 10V RLOAD =50 (Differential) Carrier Frequency: 132.5KHz VATOP = 4VPP , PAVCC = 10V No Load. HD3ATOP Third Harmonic Distortion on each ATOP1 and ATOP2 pins VATOP = 4VPP , PAVCC = 10V RLOAD =50 (Differential) Carrier Frequency: 132.5KHz RCL = 1.75; Vsense(AC) = 0V -1 0.6 1 30 Figure 14 160 180 200 Test condition Min Typ -55 VATO = 2VPP -52 Rcl = 1.85k; RLOAD = 1 (as in Figure 14) RCL = 1.t5k Vsense(AC) = 0V
VATOP(AC) P A V c c ----------------------------------- + 7.5 V 2
Max -42 -49
Unit dBc dBc
IATOP
250
310
370
mArms
VATOP(AC)
3.5
4.6
6
Vpp
VATOP(DC)
3.5
4.2
5
V
-55
-42
dBc
-65
-53
dBc
-56
-49
dBc
-65
-52
dBc
VATOP GST DRNG VsenseTH
Accuracy with Voltage Control Loop Active ALC Gain Step Control loop gain step ALC Dynamic Range Voltage control loop reference threshold on Vsense pin
+1 1.4
GST dB dB mVPK
VsenseHYS VSENSE(DC) VSENSE
Hysteresis on Voltage loop Figure 14 reference threshold Output DC Voltage on VSENSE VSENSE Input Impedance
18 1.865 36
mV V k
11/44
Electrical characteristics
ST7538Q
Table 4. Electrical characteristics (continued) (AVdd = DVdd = +5V, PAVcc =+9 V, PAVss, SGND = DVss = 0V, -40C TA 85C, TJ < 125 C, fc = 86kHz, other control register parameters as default value, unless otherwise specified)
Symbol CCL Parameter Input capacitance on CL pin Current control loop reference threshold on CL pin Figure 14 1.80 Test condition Min Typ 80 Max Unit pF
CCLTH
1.90
2.00
V
CCLHYST
Hysteresis on Current loop Figure 14 reference threshold Figure 17 - 600 Baud Xtal=16MHz Figure 17- 1200 Baud Xtal=16MHz Carrier Activation Time Figure 17- 2400 Baud Xtal=16MHz Figure 17- 4800 Baud Xtal=16MHz
210 0.01 0.01 0.01 0.01
250
290 1.6 800 400 200
mV ms s s s
TRxTx
TALC
Carrier Stabilization Time From STEP 16 to zero or From step 16 to step 31, Tstep
Figure 17 Xtal =16MHz Figure 17 Xtal =16MHz
3.2
ms
TST Receiver
200
s
VIN
Input Sensitivity (Normal Mode) Input Sensitivity (High Sens.) Maximum Input Signal Input Impedance Carrier detection sensitivity (Normal Mode) 80
0.5 250
2
mVrms Vrms
VIN RIN
2 100 0.5 250 VBU 140 2
Vrms k mVrms Vrms dB/ Vrms
VCD
Carrier detection sensitivity (High Sensitivity Mode) Carrier detection sensitivity UART/SPI pin (TxD line forced to "1") forced to "1"
VBU
Band in Use Detection Level
77
85
dB/ Vrms
12/44
ST7538Q
Electrical characteristics
Table 4. Electrical characteristics (continued) (AVdd = DVdd = +5V, PAVcc =+9 V, PAVss, SGND = DVss = 0V, -40C TA 85C, TJ < 125 C, fc = 86kHz, other control register parameters as default value, unless otherwise specified)
Symbol 5V voltage regulator VDC Linear regulator output voltage Power Good Output Voltage Threshold on VDC pin PG on VDC pin Hysteresis 0 < Io < 50mA 7.5V < PAVcc < 12.5V -5% 5.05 +5% V Parameter Test condition Min Typ Max Unit
PGVDC PGVDC(HYS)
4.3
4.5 250
4.7
V mV
3.3V voltage regulator DVdd Linear Regulator Output Voltage Power Good Output Voltage Threshold on DVdd pin PG on DVdd pin Hysteresis 0 < Io < 50mA 7.5V < PAVcc < 12.5V -5% 3.3 +5% V
PGDVdd PGDVdd(HYS)
3.125 250
V mV
Other functions TRSTO TWD TWM TWO TOUT TOFF TOFFD Reset Time Watch-dog Pulse Width Watch-dog Pulse Period Watch-dog Time Out TX TIME OUT Time Out OFF Time See Figure 21; Xtal = 16MHz See Figure 21 See Figure 21 See Figure 21 Control Register Bit 7 and Bit 8 See Figure 20 See Figure 20 125 20 500 1 3 5 300 fclock fclock/2 fclock/4 off 600 1200 2400 4800 500 1 3 50 3.5 TWD + 3.5 1490 1.5 ms ms ms s s ms s s ms ms ms s
RxTx 0->1 vs. TOUT Delay See Figure 20 Carrier Detection Time selectable by register Control Register bit 9 and bit10 Figure 11
TCD
TDCD
CD_PD Propagation Delay Figure 11 Master Clock Output Selectable by register Control Register bit 15 and bit 16 see Table 11 Control Register bit 3 and bit 4 see Table 11
MCLK
MHz
BAUD
Baud rate
Baud
13/44
Electrical characteristics
ST7538Q
Table 4. Electrical characteristics (continued) (AVdd = DVdd = +5V, PAVcc =+9 V, PAVss, SGND = DVss = 0V, -40C TA 85C, TJ < 125 C, fc = 86kHz, other control register parameters as default value, unless otherwise specified)
Symbol Parameter Baud rate Bit Time (=1/BAUD) Test condition Control Register bit 3 and bit 4 see Table 11 Min Typ 1667 833 417 208 Max Unit
TB
s
Zero crossing detection ZCDEL Zero Crossing Detection delay (delay between the ZCIN and ZCOUT signals) Zero Crossing Detection Low Threshold Zero Crossing Detection High Threshold Zero Crossing Offset Figure 22 1 s
ZC(LOW) ZC(HIGH) ZC(OFFSET)
-45 5 -20
-5 +45 +20
mV mV mV
Operational amplifier COUT(Sync) COUT(Source) CIN(Offset) GBWP Max Sync Current Max Source Current Input Terminals OFFSET Gain Bandwidth Product 15 -30 -38 6 7 28 -20 45 -10 +38 9 mA mA mV MHz
Serial interface Ts TH TCR TCC TDS TDH TCRP Setup Time Hold Time CLR/T vs. REG_DATA or RxTx CLR/T vs. CLR/T Setup Time Hold Time see Figure 5, 6, 7, 8 & 9 see Figure 5, 6, 7, 8 & 9 see Figure 5, 6, 7, 8 & 9 see Figure 5, 6, 7, 8 & 9 see Figure 5, 6, 7, 8 & 9 see Figure 5, 6, 7, 8 & 9 TB TB/4 TB/4 TH 5 2 TB/4 2*TB TB/2 TB/2 TB/2 ns ns
14/44
ST7538Q
Functional description
5
5.1
Functional description
Carrier frequencies
ST7538Q is a multi frequency device: eight programmable Carrier Frequencies are available (see Table 5). Only one Carrier could be used a time. The communication channel could be varied during the normal working Mode to realize a multifrequency communication. Selecting the desired frequency in the Control Register the Transmission and Reception filters are accordingly tuned. Table 5. ST7538Q Channels List
FCarrier F0 F1 F2 F3 F4 F5 F6 F7(1) F (KHz) 60 66 72 76 82.05 86 110 132.5
5.2
Baud rates
ST7538Q is a multi Baud rate device: four Baud Rate are available (See Table 6.). Table 6. ST7538Q mark and space tones frequency distance vs baud rate and deviation
Baud Rate [Baud] 600 1200 2400 (4) 4800
1. Frequency deviation. 2. Deviation = F / (Baud Rate) 3. Deviation 0.5 Not Allowed 4. Default value
F (1) (Hz) 600 600 1200 1200 (4) 2400 2400 4800
Deviation (2) 1 (3) 0.5 1 0.5 1 0.5 1
15/44
Functional description
ST7538Q
5.3
Mark and space frequencies
Mark and space communication frequencies are defined by the following formula: F ("0") = FCarrier + [F]/2 F ("1") = FCarrier - [F]/2 F is the Frequency Deviation. With Deviation = "0.5" the difference in terms of frequency between the mark and space tones is half the Baudrate value (F = 0.5*BAudrate). When the Deviation = "1" the difference is the Baudrate itself (F = Baudrate). The minimal Frequency Deviation is 600Hz. Table 7. ST7538Q synthesized frequencies
Exact Carrier Frequency [Hz] Baud Frequency Deviation (Clock=16MHz) Rate (KHz) "1" "0" 60 600 -1 1200 0.5 1 2400 0.5 1 4800 0.5 1 66 600 -1 1200 0.5 1 2400 0.5 1 4800 0.5 1 65755 65755 65430 65430 64779 64779 63639 66243 66243 66569 66569 67220 67220 68359 4800 2400 1200 59733 59733 59408 59408 58757 58757 57617 60221 60221 60547 60547 61198 61198 62337 86 600 4800 2400 1200 Exact Carrier Frequency [Hz] Frequen Baud Deviation (Clock=16MHz) cy Rate (KHz) "1" "0" 82.05 600 -1 0.5 1 0.5 1 0.5 1 -1 0.5 1 0.5 1 0.5 1 85775 85775 85449 85449 84798 84798 83659 86263 86263 86589 86589 87240 87240 88379 81706 81706 81380 81380 80892 80892 79590 82357 82357 82682 82682 83171 83171 84473
16/44
ST7538Q Table 7. ST7538Q synthesized frequencies
Exact Carrier Frequency [Hz] Baud Frequency Deviation (Clock=16MHz) Rate (KHz) "1" "0" 72 600 -1 1200 0.5 1 2400 0.5 1 4800 0.5 1 76 600 -1 1200 0.5 1 2400 0.5 1 4800 0.5 1 75684 75684 75358 75358 74870 74870 73568 76335 76335 76660 76660 77148 77148 78451 4800 2400 1200 71777 71777 71452 71452 70801 70801 69661 72266 72266 72591 72591 73242 73242 74382 132.5 600 4800 2400 1200
Functional description
Exact Carrier Frequency [Hz] Frequen Baud Deviation (Clock=16MHz) cy Rate (KHz) "1" "0" 110 600 -1 0.5 1 0.5 1 0.5 1 -1 0.5 1 0.5 1 0.5 1 132161 132813 132161 132813 131836 133138 131836 133138 131348 133626 131348 133626 130046 134928 109701 110352 109701 110352 109375 110677 109375 110677 108724 111165 108724 111165 107585 112467
5.4
ST7538Q mains access
ST7538Q can access the Mains in two different ways:
Synchronous access Asynchronous access
The choice between the two types of access can be performed by means of Control Register bit 14 (see Table 11) and affects the ST7538Q data flow in Transmission Mode as in Reception Mode (for how to set the communication Mode, see Section 5.5 on page 18).
In Data Transmission Mode: Synchronous Mains access: on clock signal provided by ST7538Q (CLR/T line) rising edge, data transmission line (TxD line) value is read and sent to the FSK Modulator. ST7538Q manages the Transmission timing according to the BaudRate Selected. Asynchronous Mains access: data transmission line (TxD line) value enters directly to the FSK Modulator. The Host Controller manages the Transmission timing (CLR/T line should be neglected).
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Functional description In Data Reception Mode:
ST7538Q
Synchronous Mains access: on clock signal recovered by a PLL from ST7538Q (CLR/T line) rising edge, value on FSK Demodulator is read and put to the data reception line (RxD line). ST7538Q recovers the bit timing according to the BaudRate Selected. Asynchronous Mains access: Value on FSK Demodulator is sent directly to the data reception line (RxD line). The Host Controller recovers the communication timing (CLR/T line should be neglected).
5.5
Host processor interface
ST7538Q exchanges data with the host processor through a serial interface. The data transfer is managed by REG_DATA and RxTx Lines, while data are exchanged using RxD, TxD and CLR/T lines. Four are the ST7538Q working modes:
Data Reception Data Transmission Control Register Read Control Register Write
REG_DATA and RxTx lines are level sensitive inputs. Table 8. Data and control register access bits configuration
REG_DATA Data Transmission Data Reception Control Register Read Control Register Write 0 0 1 1 RxTx 0 1 1 0
ST7538Q features two type of Host Communication Interfaces: S PI UART
The selection can be done through the UART/SPI pin. If UART/SPI pin is forced to "0" SPI interface is selected while if UART/SPI pin is forced to "1" UART interface is selected (a). The type of interface affects the Data Reception by setting the idle state of RxD line. When ST7538Q is in Receiving mode (REG_DATA="0" and RxTx ="1") and no data are available on mains (or RxD is forced to an idle state, i.e. with a conditioned Detection Method), the RxD line is forced to "0" when UART/SPI pin is forced to "0" or to "1" when UART/SPI pin is forced to "1".
a. UART Interface Mode modifies also Control Register Functions and provides one more level of Rx sensitivity (see par. 5.11)
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ST7538Q
Functional description The UART interface allows to connect an UART compatible device instead SPI interface allows to connect an SPI compatible device. The allowed combinations of Host Interface/ST7538Q Mains Access are: Table 9. Host Interface / ST7538Q mains access combinations
Host Device interface type UART UART SPI SPI UART/SPI pin "1" "1" "0" "0" Communication mode Transmission Reception Transmission Reception Mains access Asynchronous X X X(1) X X Synchronous
1. Received Data more stable than in Asynchronous Mains Access
Figure 3.
Synchronous and asynchronous ST7538Q/Host controller interfaces
UART/Asynchronous Data Interface RxD TxD RxTx CLR/T REG_DATA SPI/Synchronous Data Interface RxD TxD RxTx CLR/T REG_DATA
Host Controller
ST7538Q
Host Controller
D03IN1415
ST7538Q
ST7538Q allows to interface the Host Controller using a five line interface (RxD,TxD,RxTx, CLR/T, & REG_DATA) in case of Synchronous mains access or using a 3 line interface (RxD,TxD & RxTx) in Asynchronous mains access. Since Control Register is not accessible in Asynchronous mode, in this case REG_DATA pin can be tied to GND.
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Functional description
ST7538Q
5.5.1
Communication between host and ST7538Q
The Host can achieve the Mains access by selecting REG_DATA = "0" and the choice between Data Transmission or Data Reception is performed by selecting RxTx line (if RxTx ="1" ST7538Q receives data from mains, if RxTx = "0" ST7538Q transmits data over the mains). Communication between Host and ST7538Q is different in Asynchronous and Synchronous mode:
Asynchronous mode In Asynchronous Mode, data are exchanged without any data Clock reference. The host controller has to recover the clock reference in receiving Mode and control the Bit time in transmission mode. If RxTx line is set to "1" & REG_DATA = "0" (Data Reception), ST7538Q enters in an Idle State. After Tcc time the modem starts providing received data on RxD line. If RxTx line is set to "0" & REG_DATA="0" (Data Transmission), ST7538Q enters in an Idle State and transmission circuitry is switched on. After Tcc time the modem starts transmitting data present on TxD line.
Synchronous mode In Synchronous Mode ST7538Q is always the master of the communication and provides the clock reference on CLR/T line. When ST7538Q is in receiving mode an internal PLL recovers the clock reference. Data on RxD line are stable on CLR/T rising Edge. When ST7538Q is in transmitting mode the clock reference is internally generated and TxD line is sampled on CLR/T rising Edge. If RxTx line is set to "1" & REG_DATA="0" (Data Reception), ST7538Q enters in an Idle State and CLR/T line is forced Low. After Tcc time the modem starts providing received data on RxD line. If RxTx line is set to "0" & REG_DATA="0" (Data Transmission), ST7538Q enters in an Idle State and transmission circuitry is switched on. After Tcc time the modem starts transmitting data present on TxD line (Figure 5) .
Figure 4.
Receiving and transmitting data/recovered clock timing
Receiving Bit Synchronization Transmitting Bit Synchronization
CLR/T
CLR/T
RxD
TxD
D03IN1416
TSTH
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ST7538Q Figure 5.
CLR_T TB RxD REG_DATA TCR RxTx TSTH BIT23 BIT22 TCR
Functional description Data reception -> data transmission -> data reception
TCC TCC TDS TDH
TxD
D03IN1402
5.6
Control register access
The communication with ST7538Q Control Register is always synchronous. The access is achieved using the same lines of the Mains interface (RxD, TxD, RxTx and CLR/T) plus REG_DATA Line. With REG_DATA = 1 and RxTx = 0, the data present on TxD are loaded into the Control Register MSB first. The ST7538Q samples the TxD line on CLR/T rising edges. The control Register content is updated at the end of the register access section (REG_DATA falling edge). In Normal Control Register mode (Control Register bit 21="0", see Table 11) if more than 24 bits are transferred to ST7538Q only latest 24 bits are stored inside the Control Register. If less than 24 bits are transferred to ST7538Q the Control Register writing is aborted (in this case if at least 16 bits are provided REGOK line will be activated). In order to avoid undesired Control Register writings caused by REG_DATA line fluctuations (for example because of surge or burst on mains), in Extended Control Register mode (Control Register bit 21="1" see Table 11) exactly 24 or 48 bits must be transferred to ST7538Q in order to properly write the Control Register, otherwise writing is aborted and if at least 16 bits are provided REGOK line will be activated. If 24 bits are transferred, only the first 24 Control Register bits (from 23 to 0) are written. With REG_DATA = 1 and RxTx = 1, the content of the Control Register is sent on RxD port. The Data on RxD are stable on CLR/T rising edges MSB First. In Normal Control Register mode 24 bits are transferred from ST7538Q to the Host. In Extended Control Register mode 24 or 48 bits are transferred from ST7538Q to the Host depending on content of Control Register bit 18 (with bit 18 = "0" the first 24 bits are transferred, otherwise all 48 bits are transferred, see Table 11).
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Functional description Figure 6.
ST7538Q Data reception -> control register read -> data reception timing diagram
TCC TCC TDS TDH BIT22 TCR TB
CLR_T TDS RXD TCR TDH
BIT23
REG_DATA
RxTx
D03IN1404
Figure 7.
CLR_T TD S RxD
Data reception -> control register write -> data reception timing diagram
TC C TD H TC C TB
TC R REG_DATA TC R RxTx TSTH TxD BIT23 BIT22 TC R
TC R
D03IN1403
Figure 8.
CLR_T
Data transmission -> control reg. read data -> reception timing diagram
TC C TB TD S BIT23 TD H TCC TD S TDH
RxD
BIT22
REG_DATA
TC R
TCR
TC R RxTx TSTH TxD
D03IN1405
Figure 9.
CLR_T
Data transmission -> control reg. write -> data reception timing diagram
TCC TB TSTH BIT23 BIT22 TCR TSTH TCC
TxD
REG_DATA TCR TCR RxTx TDS RxD
D03IN1401
TDH
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ST7538Q
Functional description
5.7
Receiving mode
The receive section is active when RxTx Pin = "1" and REG_DATA = 0. The input signal is read on RAI Pin using SGND as ground reference and then pre-filtered by a Band pass Filter (62kHz max bandwidth at -3dB). The Pre-Filter can be inserted setting one bit in the Control Register. The Input Stage features a wide dynamic range to receive Signal with a Very Low Signal to Noise Ratio. The Amplitude of the applied waveform is automatically adapted by an Automatic Gain Control block (AGC) and then filtered by a Narrow Band Band-Pass Filter centered around the Selected Channel Frequency (14kHz max at -3dB). The resulting signal is down-converted by a mixer using a sinewave generated by the FSK Modulator. Finally an Intermediate Frequency Band Pass-Filter (IF Filter) improves the Signal to Noise ration before sending the signal to the FSK demodulator. The FSK demodulator then send the signal to the RX Logic for final digital filtering. Digital filtering Removes Noise spikes far from the BAUD rate frequency and Reduces the Signal Jitter. RxD Line is forced at logic level "0" or "1" (according the UART/SPI pin level) when neither mark or space frequencies are detected on RAI Pin. Mark and Space Frequency in Receiving Mode must be distant at least BaudRate/2 to have a correct demodulation. While ST7538Q is in Receiving Mode (RxTx pin = "1"), the transmit circuitry, Power Line Interface included, is turned off. This allows the device to achieve a very low current consumption (5mA typ). In Receiving mode ATOP2 pin is internally connected to PAVSS.
5.7.1
High sensitivity mode
It is possible to increase the ST7538Q Receiving Sensitivity setting to `1' the High Sensitivity Bit of Control Register (b). This function allows to increase the communication reliability when the ST7538Q sensitivity is the limiting factor.
5.7.2
Synchronization recovery system (PLL)
ST7538Q embeds a Clock Recovery System to feature a Synchronous data exchange with the Host Controller. The clock recovery system is realized by means of a second order PLL. Data on the data line (RxD) are stable on CLR/T line rising edge (CLR/T Falling edge synchronized to RxD line transitions LOCK-IN Range). The PLL Lock-in and Lock-out Range is /2. When the PLL is in the unlock condition, CLR/T and RxD lines are forced to a low logic level. When PLL is in unlock condition it is sensitive to RxD Rising and Falling Edges. The maximum number of transition required to reach the lock-in condition is 5. When in lock-in condition the PLL is sensitive only to RxD rising Edges to reduce the CLR/T Jitter. ST7538Q PLL is forced in the un-lock condition, when more than 32 equal symbols are received. Due to the fact that the PLL, in lock-in condition, is sensitive only to RxD rising edge, sequences equal or longer than 15 equal symbols can put the PLL into the un-lock condition.
b. A third level of Rx sensitivity can be selected in UART Interface Mode (see par. 5.11)
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Functional description Figure 10. ST7538Q PLL lock-in range
CLR/T
ST7538Q
RxD
D03IN1417
LOCK-IN RANGE
5.7.3
Carrier/preamble detection
The Carrier/Preamble Block is a digital Frequency detector Circuit. It can be used to manage the MAINS access and to detect an incoming signal. Two are the possible setting:
Carrier detection: The Carrier/Preamble detection Block notifies to the host controller the presence of a Carrier when it detects on the RAI Input a signal with an harmonic component close to the programmed Carrier Frequency. The CD_PD signal sensitivity is identical to the data reception sensitivity (0.5mVrms Typ. in Normal Sensitivity Mode). The CD_PD line is forced to a logic level low when a Carrier is detected. Preamble detection: The Carrier/Preamble detection Block notifies to the host controller the presence of a Carrier modulated at the Programmed Baud Rate for at least 4 Consecutive Symbols ("1010" or "0101" are the symbols sequences detected). CD_PD line is forced low till a Carrier signal is detected and PLL is in the lock-in range. To reinforce the effectiveness of the information given by CD_PD Block, a digital filtering is applied on Carrier or Preamble notification signal (See Control Register Paragraph). The Detection Time Bits in the Control Register define the filter performance. Increasing the Detection Time reduces the false notifications caused by noise on main line. The Digital filter adds a delay to CD_PD notification equal to the programmed Detection Time. When the carrier frequency disappears, CD_PD line is held low for a period equal to the detection time and then forced high. During this time the some spurious data caused by noise can be demodulated.
5.7.4
Header recognition
In Extended Control Register Mode (Control Register bit 21 = "1", see Table 11) the CD_PD line can be used to recognize if an header has been sent during the transmission. With Header Recognition function enable (Control Register bit 18 = "1", see Table 11), CD_PD line is forced low when a Frame Header is detected. If Frame Length Count function is enabled, CD_PD is held low and a number of 16 bit word equal to the Frame Length selected is sent to the host controller. In this case, CLR/T is forced to "0" and RxD is forced to "0" or "1" (according the UART/SPI pin level) when Header has not been detected or after the Frame Length has been reached. If Frame Length Count function is disabled, an header recognition is signaled by forcing CD_PD low for one period of CLR/T line. In this case, CLR/T and RxD signal are always present, even if no header has been recognized.
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ST7538Q Figure 11. CD_PD timing during RX
TD C D TC D
Functional description
TD C D
TC D
CD_PD
RAI
demodulation active on RxD pin RxD (UART/SPI="1") noise demodulated
RxD (UART/SPI="0")
noise demodulated
D03IN1418
Figure 12. Receiving path block diagram
RXFO 31 Bits 3-4 3 RxD Bits 3-4 &14 8 CLR/T PLL Bits 18-21 & 24-47 1 CD_PD 9 BU HEADER RECOGN. Low Pass Low Pass DIGITAL FILTER FSK DEMODULATOR Band Pass IF FILTER LOCAL OSC Bits 0 -2 Carrier Detection Band Pass CHANNEL FILTER GAIN CONTROL Bits 3-4 & 22 MIXER AGC Band Pass PRE-FILTER Bits 0-2 Bit 23 32 RAI
Bits 9-10
Bits 12-13 & 22 CARRIER/ PREAMBLE DETECTION
BAND IN USE
D03IN1419
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Functional description
ST7538Q
5.8
Transmission mode
The transmit mode is set when RxTx Pin = "0" and REG_DATA Pin = "0". In transmitting mode the FSK Modulator and the Power Line Interface are turned ON. The transmit Data (TXD) enter synchronously or asynchronously to the FSK modulator.
Host Controller Synchronous Communication Mode: on CLR/T rising edge, TXD Line Value is read and sent to the FSK Modulator. ST7538Q Manages the Transmission timing according to the BaudRate Selected Host Controller Asynchronous Communication Mode: TXD data enter directly to the FSK Modulator.The Host Controller Manages the Transmission timing
In both conditions no Protocol Bits are added by ST7538Q. The FSK frequencies are synthesized in the FSK modulator from a 16MHz crystal oscillator by direct digital synthesis technique. The frequencies Table in different Configuration is reported in Table 7. The frequencies precision is same as external crystal one's. In the analog domain, the signal is filtered in order to reduce the output signal spectrum and to reduce the harmonic distortion. The transition between a symbol and the following is done at the end of the on-going half FSK sinewave cycle. Figure 13. Transmitting path block diagram
Bit 7 & 8 TIMER 7 TOUT THERMAL SENSOR Bit 14 5 TxD DAC Band Pass D-TYPE FLIP FLOP 8 CLR/T ZERO CROSSING FSK MODULATOR TRANSMISSION FILTER PLI 21 ATOP2 ALC PLI Bit 0-5 Bit 0-2 19 ATOP1 CURRENT LOOP 23 CL Bits 17 & 21 VOLTAGE LOOP 29 Vsense
24
ATO
15 ZCOUT
CLR/T GENERATOR 16 ZCIN
D03IN1420
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ST7538Q
Functional description
5.8.1
Automatic Level Control (ALC)
The Automatic Level Control Block (ALC) is a variable gain amplifier (with 32 non linear discrete steps) controlled by two analog feed backs acting at the same time. The ALC gain range is 0dB to 30 dB and the gain change is clocked at 5KHz. Each step increases or reduces the voltage of 1dB (Typ). Two are the control loops acting to define the ALC gain:
The Voltage control loop acts to keep the Peak-to-Peak Voltage constant on Vsense. The gain adjustment is related to the result of a peak detection between the Voltage waveform on Vsense and two internal Voltage references. It is possible to protect the Voltage Control Loop against noise by freezing the output level (see Section 6.6: Output voltage level freeze on page 38).
If Vsense < VCLTH - VCLHYST The next gain level is increased by 1 step If VCLTH - VCLHYST < Vsense < VCLTH + VCLHYST No Gain Change If Vsense > VCLTH + VLCHYST The next gain level is decreased by 1 step
The Current control loop acts to limit the maximum Peak Output current inside ATOP1 and ATOP2. The current control loop acts through the voltage control loop decreasing the Output Peak-to-Peak Amplitude to reduce the Current inside the Power Line Interface. The current sensing is done by mirroring the current in the High side MOS of the Power Amplifier (not dissipating current Sensing). The Output Current Limit (up to 400mApeak), is set by means of an external resistor (RCL) connected between CL and PAVss. The resistor converts the current sensed into a voltage signal. The Peak current sensing block works as the Output Voltage sensing Block:
Voltage Control Loop Acting If V(CL) < CCLTH - CCLHYST If CCLTH - CCLHYST < V(CL) < CCLTH + CCLHYST No Gain Change If V(CL) > CCLTH + CLCHYST The next gain level is decreased by 1 step Figure 14 shows the typical connection of Current an Voltage control loops. Figure 14. Voltage and current feedback external interconnection example
ALC
ATOP/ATO
Vout
VRPK
R1 VOLTAGE LOOP Vsense 5.6nF R2 VCLHYST VCLTH CURRENT LOOP 80 pF CL RCL AVss CCLHYST CCLTH 1.865V (Typ)
D03IN1421
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Functional description Voltage control loop formula
R1 + R2 V R P K ------------------- ( V C L T H V C L H Y S T ) R2
ST7538Q
Table 10. Vout vs R1 & R2 resistors value
Vout (Vrms) 0.150 0.250 0.350 0.500 0.625 0.750 0.875 1.000 1.250 1.500 Vout (dBV) 103.5 108.0 110.9 114.0 115.9 117.5 118.8 120.0 121.9 123.5 (R1+R2)/R2 1.1 1.9 2.7 3.7 4.7 5.8 6.6 7.6 9.5 10.8 R2 (K) 7.5 5.1 3.6 3.3 3.3 2.7 2.0 1.6 1.6 1.6 R1 (K) 1.0 3.9 5.6 8.2 11.0 12.0 11.0 10.0 13.0 15.0
Note:
The rate of R2 takes in account the input resistance on the SENSE pin (36 K). 5.6nF capacitor effect has been neglected. Figure 15. Typical output current vs rcl
Irms (mA)
325 300 275 250 225 200 175 150 125 100 2 2.5 3 3.5 4 4.5 5 Rcl(K)
D01IN1311
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ST7538Q
Functional description
Integrated Power Line Interface (PLI) The Power Line Interface (PLI) is a double CMOS AB Class Power Amplifier with the two outputs (ATOP1 and ATOP2) in opposition of phase. Two are the possible configuration: - Single Ended Output (ATOP1). - Bridge Connection The Bridge connection guarantee a Differential Output Voltage to the load with twice the swing of each individual Output. This topology virtually eliminates the even harmonics generation. The PLI requires, to ensure a proper operation, a regulated and well filtered Supply Voltage. PAVcc Voltage must fulfil the following formula to work without clipping phenomena:
P A V c c V------T----------------------- + 7.5 V --- A ---O P ( A C ) 2
To allow the driving of an external Power Line Interface, the output of the ALC is available even on ATO pin. ATO output has a current capability much lower than ATOP1 and ATOP2. Figure 16. PLI bridge topology
VRPK
INVERTER
ATOP2
2*VRPK
LOAD ATOP1 Vout
ALC
R1 VOLTAGE LOOP Vsense 5.6nF R2
VRPK
CURRENT LOOP 80 pF
CL RCL PAVss
D03IN1422
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Functional description Figure 17. PLI startup timing diagram
RX/TX TALC TRXTX 4V TST
ST7538Q
ATOP2
0V STEP NUMBER 16 17 18 31
D03IN1408
5.9
Crystal oscillator
ST7538Q integrates a inverter driver circuit to realize a 16MHz crystal oscillator. This circuit is able to drive a maximum load capacitance of 16pF with typical quartz ESR of 40 . If the internal driver circuit is used, only one external crystal quartz and two external load capacitors (C1 and C2) are needed to realize the oscillator function (Figure 18). Figure 18. Typical crystal configuration if internal crystal driver circuit is used
XOUT
XIN
C1
C2
D03IN1425A
If an external oscillator is used, XOUT must be disconnected, while XIN must satisfies the specifications given in Table 4 (see Figure 19).
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ST7538Q Figure 19. XIN waveform if an external oscillator is used
Functional description
5.10
Control register
The ST7538Q is a multi-channel and multifunction transceiver. An internal 24 or 48 Bits (in Extended mode) Control Register allows to manage all the programmable parameters (Table 11). The programmable functions are:
Channel Frequency Baud Rate Deviation Watchdog Transmission Timeout Frequency Detection Time Detection Method Mains Interfacing Mode Output Clock Sensitivity Mode Input Pre-Filter
In addition to these functions the Extended mode provides 24 additional bits and others functions:
Output Level Freeze Frame Header Recognizer (one 16 bits header of or two 8 bits headers) with support to Frame Length Bit count
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Functional description
ST7538Q
Table 11. Control register functions
Bits Function Value Selection Bit2 60 KHz 66 KHz 72 KHz 76 KHz 82.05 KHz 86 KHz 110 KHz 132.5 KHz 0 0 0 0 1 1 1 1 Bit 4 3 to 4 Baud Rate 600 1,200 2,400 4,800 0 0 1 1 Bit 5 5 Deviation 0.5 1 0 1 Bit 6 6 Watchdog Disabled Enabled (1.5 s) Bit 8 7 to 8 Transmission Time Out Disabled 1s 3s Not Used 0 0 1 1 Bit 10 9 to 10 Frequency detection time 500 s 1 ms 3 ms 5 ms 0 0 1 1 Bit 11 Disabled Enabled 0 1 Disabled 0 1 Bit 7 0 1 0 1 Bit 9 0 1 0 1 Enabled 0.5 Bit1 Bit0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Bit 3 0 1 0 1 Note Default
0 to 2
Frequencies
132.5 kHz
2400
1 sec
1 ms
11
Zero Crossing Synchronizati on
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ST7538Q Table 11. Control register functions (continued)
Function Value Selection Bit 13 Carrier detection without conditioning Bit 12
Functional description
Note
Default
0
0
Carrier Detection Notification on CD_PD Line CLR/T and RxD signal always Present CLR/T and RxD lines are forced to "0" when Carrier is not detected Preamble Detection Notification on CD_PD Line CLR/T and RxD signal always Present Preamble Detection Notification on CD_PD Line CLR/T and RxD lines are forced to "0" when Preamble has not been detected or PLL is in Unlock condition Preamble detection without conditioning
Carrier detection with conditioning Preamble detection without conditioning
0
1
12 to 13
Detection Method(1)
1
0
Preamble detection with conditioning
1
1
Bit 14 14 Mains Interfacing Mode Synchronous Asynchronous Bit 16 15 to 16 16 MHz 8 MHz 4 MHz Clock OFF 0 0 1 1 Bit 17 17 Output Voltage Level Freeze Enabled Disabled 0 1 Bit 18 18 Header Recognition Disabled Enabled 0 1 Bit 19 Frame Length Count Disabled Enabled 0 1 Active only if Extended Control Register is enable (Bit 21="1") Active only if Header Recognition Function (Bit 18="1") and Extended Control Register (Bit 21="1") are enable Disabled Active only if Extended Control Register is enable (Bit 21="1") Disabled 0 1 Bit 15 0 1 0 1 Asynchronou s
Output Clock
4 MHz
19
Disabled
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Functional description Table 11. Control register functions (continued)
Function Value Selection Bit 20 20 Header Length 8 bits 16 bits 0 1 Bit 21 21 Extended Register Disable (24 bits) Enabled (48 bits) 0 1 Bit 22 22 Sensitivity Mode Normal Sensitivity High Sensitivity 0 1 Bit 23 23 Input Filter Disabled Enabled from 0000h to FFFFh 0 1 One 16 bits Header or two 8 bits Headers (MSB first) depending on Bit 17 Number of 16 bits words expected Extended Register enables Functions on Bit 17, 18,19 and 20 Active only if Extended Control Register is enable (Bit 21="1") Note
ST7538Q
Default
16 bits
Disabled (24 bits)
Normal
Disabled
24 to 39 40 to 47
Frame Header Frame Length
9B58h
from 01h to FFh
08h
1. The Detection method bit meaning differs depending on UART/SPI pin value. In this table is listed the SPI mode (UART/SPI="0"). For Detection method bit meaning in UART mode (UART/SPI="1") please see Table 12.
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ST7538Q
Functional description
5.11
Detection method and Rx Sensitivity in UART mode
When ST7538Q is running in UART mode (by forcing UART/SPI pin to "1") the Control Register Function "Detection method" differs from SPI mode as indicated in the Table 12: Table 12. Control register functions in UART mode
Function Value Selection Bit 13 Bit 12 This configuration should be avoided because it could cause an unpredictable behavior of the device This configuration should be avoided because it could cause an unpredictable behavior of the device Carrier Detection Notification on CD_PD Line CLR/T and RxD signal always Present Carrier Detection Notification on CD_PD Line CLR/T Line is forced to "0" and RxD Line is forced to "0" or "1" (according the UART/SPI pin level) when Carrier is not detected Carrier detection without conditioning Note Default
Not Allowed
0
0
Not Allowed
0
1
12 to 13
Detection Method
Carrier detection without conditioning
1
0
Carrier detection with conditioning
1
1
UART mode provides also a third level of Receiving sensitivity in addition to two levels select able by Control Register (see Table 11). By setting to "1" the TxD pin during a receiving session the sensitivity is forced to BU threshold (this condition suppresses the Control Register setting).
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Auxiliary analog and digital functions
S T7 53 8 Q
6
6.1
Auxiliary analog and digital functions
Band in use
The Band in Use Block has a Carrier Detection like function but with a different Input Sensibility (77dBV Typ.) and with a different BandPass filter Selectivity (40dB/Dec). BU line is forced High when a signal in band is detected. To prevent BU line false transition, BU signal is conditioned to Carrier Detection Internal Signal.
6.2
Time out
Time Out Function is a protection against a too long data transmission. When Time Out function is enabled after 1 or 3 second of continuos transmission the transceiver is forced in receiving mode. This function allows ST7538Q to automatically manage the CENELEC Medium Access specification. When a time-out event occur, TOUT is forced high, and is held high for at least 125 ms. To Unlock the Time Out condition RxTx should be forced High. During the time out period only register access or reception mode are enabled. During Reset sequence if RxTx line ="0" & REG_DATA line ="0", TIMEOUT protection is suddendly enabled and ST7538Q must be configured in data reception after the reset event before starting a new data transmission. Time Out time is programmable using Control Register bits 7 and 8 (Table 11). Figure 20. Time-out timing and unlock sequence
RxTx TOUT TOFF TOFFD
Time Out function
D03IN1409
6.3
Reset & watchdog
RSTO Output is a reset generator for the application circuitry. During the ST7538Q startup sequence is forced low. RSTO becomes high after a TRSTO delay from the end of oscillator startup sequence. Inside ST7538Q is also embedded a watchdog function. The watchdog function is used to detect the occurrence of a software fault of the Host Controller. The watchdog circuitry generates an internal and external reset (RSTO low for TRSTO time) on expiry of the internal watchdog timer. The watchdog timer reset can be achieved applying a negative pulse on WD pin (Figure 21).
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ST7538Q Figure 21. Reset and watchdog timing
TRSTO
Auxiliary analog and digital functions
TWO
TRSTO
RSTO TWD WD
TWM
D03IN1410
6.4
Zero crossing detection
The Mains Voltage Zero Crossing can be detected, through a proper connection of ZCIN to the Mains. ZCIN comparator has a threshold fixed at SGND. ZCOUT is a TTL Output forced High after a positive zero-crossing transition, and low after a negative one. Setting the Bit 11 inside the Control Register to "1" the transmission is automatically synchronized to the mains positive zero-crossing transition. This function is achieved turning on the PLI when RX/TX is low and delaying the CLR/T first transition until the first zerocrossing event. The automatic synchronization procedure can work only if the synchronous interface is programmed. If asynchronous interface is in use the Zero Crossing synchronization can be achieved managing the ZCOUT line. Figure 22. Synchronous zero-crossing transmission
ZCIN
t
RxTx
CLR/T
TxD
ZCDEL ZCOUT
D03IN1423
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Auxiliary analog and digital functions
S T7 53 8 Q
6.5
Output clock
MCLK is the master clock output. The clock frequency sourced can be programed through the control register to be a ratio of the crystal oscillator frequency (Fosc, Fosc/2 Fosc/4) or can be disabled (off). The transition between one frequency and another is done only at the end of the ongoing cycle.
6.6
Output voltage level freeze
The Output Level Freeze function, when enabled, turns off the Voltage Control Loop once the ALC stays in a stable condition for about 3 periods of control loop, and maintains a constant gain until the end of transmission. Output Level Freeze can be enabled using Control Register bit 17 (Table 11). This function is available only using the Extended Control Register (Control Register bit 21 = "1").
6.7
Extended control register
When Extended Control Register function is enabled, all the 48 bits of Control Register are programmable. Otherwise, only the first 24 bits of Control Register are programmable. The functions Header Recognition, Frame Bit Count and Output Voltage Freeze are available only if Extended Control Register function is enabled. Extended Control Register can be enabled setting the Control Register bit 21(Table 11).
6.8
Reg OK
REGOK allows to detect an incomplete writing of the Control Register content (see Section 5.6: Control register access on page 21) or an accidental corruption of the Control Register content. In these cases REGOK goes to "1" until a new Control Register writing session is performed.
6.9
Under voltage lock out
The UVLO function turns off the device if the PAVcc voltage falls under 4V. Hysteresis is 340mV typically.
6.10
Thermal shutdown
The ST7538Q is provided of a thermal protection which turn off the PLI when the junction temperature exceeds 170C 10% . Hysteresis is around 30C. When shutdown threshold is overcome, PLI interface is switched OFF. Thermal Shutdown event is notified to the HOST controller using TIMEOUT line. When TIMEOUT line is High, ST7538Q junction temperature exceed the shutdown threshold (Not Leached).
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ST7538Q
Auxiliary analog and digital functions
6.11
5V and 3.3V voltage regulators and power good function
ST7538Q has an embedded 5V linear regulator externally available to supply the application circuitry. The linear regulator has a very low quiescent current (50A) and a current capability of 50mA. The regulator is protected against short circuitry events. The DVdd pin can act either as 3.3V Voltage Output or as Input Digital Supply. When the DVdd pin is externally forced to 5V all the Digital I/Os operate at 5V, otherwise all the Digital I/Os are internally supplied at 3.3V. The DVdd pin can also source 3.3V voltage to supply external components. The 3.3V linear regulator has a very low quiescent current (50A) and a current capability of 50mA. The regulator is protected against short circuitry events. If AVdd and DVdd pins are connected to VDC pin, the 5V regulator maximum current capability rises to 100mA When the regulator Voltages are above of the power good thresholds VPG (see Table 4), Power Good line is forced high, while is forced low at startup and when VDC or DVdd falls below VPG - VPGHYS Voltage. Figure 23. Power good function
VDC/DVDD
4.5V/3.125V 250mV
Time
PG PG OK
D03IN1411
Time
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Auxiliary analog and digital functions
S T7 53 8 Q
6.12
Power-up procedure
To ensure ST7538Q proper power-Up sequence, PAVcc, AVdd and DVdd Supply has to fulfil the following rules: PAVcc rising slope must not exceed 100V/ms. When DVdd is below 5V/3.3V and AVdd is below 5V: 100mV < PAVcc-AVdd , PAVcc-DVdd < 1.2V. When AVdd and DVdd supplies are connected to VDC the above mentioned relation is guarantied if VDC load < 100mA and if the filtering capacitor on VDC < 100uF. If DVdd is not forced to 5V, the Digital I/Os are internally supplied at 3.3 V and if DVdd load < 50mA and the filtering capacitor on DVdd < 100uF the second relation can be ignored . Figure 24. Power-UP sequence
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ST7538Q
N.C. VDC 33 44 39 22 40 38 37 21 24 32 LOAD ATOP1 R1 RAI AC LINE ATO ATOP2 No External Components for POWER LINE DRIVER C_MINUS C_PLUS C_OUT 28 34 PAVCC 17 SINGLE SUPPY 25 AC/DC Conver ter SGND
N.C.
N.C.
N.C.
5V Supply for Host Controller AVdd DVdd 10 13 30 35 14 42 36 7 9 15 1 3 5 4 8 43 31 16 27 11 12 20 PAVSS DVSS 18 DVSS 2 GND 6 GND D03IN1412A 41 26 RxFO ZCIN XIN Zero Crossing Transmission Synchronization XOUT 23 CL RCL 29 Vsense R2 19
UART/SPI TEST2 TEST1 WD PG REGOK TOUT BU ZCOUT CD/PD RxD TxD RX/TX CLR/T
ST7538Q
C1
HOST CONTROLLER
Voltage Regulation & Current Protection
Mains Coupling reference circuit
REG/DATA
Figure 25. Application schematic example with coupling tranformer.
5 Lines Serial Interface MCLK RSTO
Clock & Reset for Host Controller
Auxiliary analog and digital functions
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Package mechanical data
ST7538Q
7
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com Best thermal performance is achieved when slug is soldered to PCB. It is recommended to have five solder dots (See Figure 27) without resist to connect the Copper slug to the ground layer on the soldering side. Moreover it is recommitted to connect the ground layer on the soldering side to another ground layer on the opposite side with 15 to 20 vias. It is suggested to not use the PCB surface below the slug area to interconnect any pin except ground pins. Figure 26. ST7538Q slug drawing
0.10mm 0.05 Copper Slug Solder plated Lead frame
D03IN1414
Figure 27. Soldering information
Cu plate Solder dots
Package Sizes
B A L L1
10x10x1.4mm 2.00 mm 1.00 mm 6.00 mm 10.00 mm
A B L L1 (Copper plate)
L
L1
D03IN1413
If PCB with ground layer, connect copper plate with 15 to 20 vias
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ST7538Q
Revision history
8
Revision history
Table 13. Revision history
Date 12-Jul-2006 Revision 1 Initial release. Changes
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ST7538Q
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