PM6681A
Dual synchronous step-down controller with adjustable LDO
Features
6 V to 36 V input voltage range Adjustable output voltages 0.9 - 3.3 V LDO adjustable delivers 100 mA peak current 5 V LDO delivers 100 mA peak current 1.237 V 1 % reference voltage available No RSENSE current sensing using low side MOSFETs' RDS(on) Negative current limit Soft-start internally fixed at 2 ms Soft output discharge Latched UVP Not-latched OVP Selectable pulse skipping at light loads Selectable minimum frequency (33 kHz) in pulse skip mode 5 mW maximum quiescent power Independent Power Good signals Output voltage ripple compensation
VFQFPN-32 (5 mm x 5 mm)
Description
PM6681A is a dual step-down controller specifically designed to provide extremely high efficiency conversion, with lossless current sensing technique. The constant on-time architecture assures fast load transient response and the embedded voltage feed-forward provides nearly constant switching frequency operation. An embedded integrator control loop compensates the DC voltage error due to the output ripple. Pulse skipping technique increases efficiency at very light load. Moreover a minimum switching frequency of 33 kHz is selectable to avoid audio noise issues. The PM6681A provides a selectable switching frequency, allowing three different values of switching frequencies for the two switching sections. The output voltages OUT1 and OUT2 can be adjusted from 0.9 V to 5 V and from 0.9 V to 3.3 V respectively. The device provides also 2 LDOs, 5 V fixed and 0.9 V - 3.3 V adjustable.
Applications
Embedded computer system FPGA system power Industrial applications on 24 V High performance and high density DC-DC modules Notebook computer Order codes
Order codes PM6681A PM6681ATR
Table 1.
Package VFQFPN-32 (5 mm x 5 mm) exposed pad
Packaging Tray Tape and reel
June 2008
Rev 3
1/47
www.st.com 47
Contents
PM6681A
Contents
1 2 Simplified application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 2.2 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 F unctions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 4 5 6 7
Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 Constant on time PWM control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Constant on time architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Output ripple compensation and loop stability . . . . . . . . . . . . . . . . . . . . . 20 Pulse skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 No-audible skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 soft-star t and soft-end . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Gate drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Internal linear regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Power up sequencing and operative modes . . . . . . . . . . . . . . . . . . . . . . . 28
8
Monitoring and protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.1 8.2 8.3 8.4 Power good signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Undervoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
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PM6681A
Contents
9
Design guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 Switching frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Input capacitors selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Power MOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Closing the integrator loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Other parts design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Design example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
9.8.1 9.8.2 9.8.3 9.8.4 9.8.5 9.8.6 9.8.7 9.8.8 Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Power MOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Input capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Synchronous rectifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Integrator loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Output feedback divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
10 11 12
Layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3/47
Simplified application schematic
PM6681A
1
Simplified application schematic
Figure 1. Application schematic
4/47
PM6681A
Pin settings
2
2.1
Pin settings
Connections
Figure 2. Pin connection (top view)
PGOOD2 PGOOD COMP1 VREF 32 OUT VCC 31 EN1 FB1
30
29
28
27
26
25
1 SGND COMP2 FSEL 2
24
SKIP
23 BOOT1
3
22 HGATE1
EN2
4
21
PM6681A
5 20 6 19
PHASE1
SHDN
CSENSE1
FB2
VIN 7 18 LDO5 8 17 V5SW 9 10 11 12 13 14 15 16
LDO OUT2
LDO FB
HGATE2
PHASE2
CSENSE2
LGATE2
PGND
LGATE1
BOOT2
2.2
Functions
Table 2.
N
Pin functions
Pin Function Signal ground. Reference for internal logic circuitry. It must be connected to the signal ground plan of the power supply. The signal ground plan and the power ground plan must be connected together in one point near the PGND pin. DC voltage error compensation pin for the switching section 2 Frequency selection pin. It provides a selectable switching frequency, allowing three different values of switching frequencies for the switching sections.
1
SGND
2 3
COMP2 FSEL
5/47
Pin settings Table 2.
N
PM6681A Pin functions (continued)
Pin Function Enable input for the switching section 2. The section 2 is enabled applying a voltage greater than 2.4 V to this pin. The section 2 is disabled applying a voltage lower than 0.8 V. When the section is disabled the high side gate driver goes low and Low Side gate driver goes high. If both EN1 and EN2 pins are low and SHDN pin is high the device enters in standby mode. Shutdown control input. The device switch off if the SHDN voltage is lower than the device off threshold (shutdown mode) The device switch on if the SHDN voltage is greater than the device on threshold. The SHDN pin can be connected to the battery through a voltage divider to program an undervoltage lockout. In shutdown mode, the gate drivers of the two switching sections are in high impedance (high-Z). Feedback input for the switching section 2 This pin is connected to a resistive voltage-divider from OUT2 to PGND to adjust the output voltage from 0.9 V to 3.3 V. Adjustable internal regulator output. It can be set from 0.9 V to 3.3 V. LDO pin can provide a 100 mA peak current. Output voltage sense for the switching section 2. This pin must be directly connected to the output voltage of the switching section. Bootstrap capacitor connection for the switching section 2. It supplies the high-side gate driver. High-side gate driver output for section 2. This is the floating gate driver output. Switch node connection and return path for the high side driver for the section 2. It is also used as negative current sense input. Positive current sense input for the switching section 2. This pin must be connected through a resistor to the drain of the synchronous rectifier (RDS(on) sensing) to obtain a positive current limit threshold for the power supply controller. Low-side gate driver output for the section 2. Power ground. This pin must be connected to the power ground plan of the power supply. Low-side gate driver output for the section 1. Feedback input for the adjustable internal linear regulator. This pin is connected to a resistive voltage-divider from LDO to SGND to adjust the output voltage from 0.9 V to 3.3 V. Internal 5 V regulator bypass connection. If V5SW is connected to OUT5 (or to an external 5 V supply) and V5SW is greater than 4.9 V, the LDO5 regulator shuts down and the LDO5 pin is directly connected to OUT5 through a 3 W (max) switch. If V5SW is connected to GND, the LDO5 linear regulator is always on if the device is not in shutdown mode.
4
EN2
5
SHDN
6
FB2
7 8 9 10 11
LDO OUT2 BOOT2 HGATE2 PHASE2
12
CSENSE2
13 14 15 16
LGATE2 PGND LGATE1 LDO FB
17
V5SW
6/47
PM6681A Table 2.
N 18 19
Pin settings Pin functions (continued)
Pin LDO5 VIN Function 5 V internal regulator output. It can provide up to 100 mA peak current. LDO5 pin supplies embedded low side gate drivers and an external load. Device supply voltage input and battery voltage sense. A bypass filter (4 W and 4.7 F) between the battery and this pin is recommended. Positive current sense input for the switching section 1. This pin must be connected through a resistor to the drain of the synchronous rectifier (RDS(on) sensing) to obtain a positive current limit threshold for the power supply controller. Switch node connection and return path for the high side driver for the section 1. It is also used as negative current sense input. High-side gate driver output for section 1. This is the floating gate driver output. Bootstrap capacitor connection for the switching section 1. It supplies the high-side gate driver. Pulse skipping mode control input. If the pin is connected to LDO5 the PWM mode is enabled. If the pin is connected to GND, the pulse skip mode is enabled. If the pin is connected to VREF the pulse skip mode is enabled but the switching frequency is kept higher than 33 kHz (No-audible pulse skip mode). Enable input for the switching section 1. The section 1 is enabled applying a voltage greater than 2.4 V to this pin. The section 1 is disabled applying a voltage lower than 0.8 V. when the section is disabled the high side gate driver goes low and low side gate driver goes high. Power Good output signal for the section 1. This pin is an open drain output and when the output of the switching section 1 is out of +/- 10 % of its nominal value.It is pulled down. Power Good output signal for the section 2. This pin is an open drain output and when the output of the switching section 2 is out of +/- 10 % of its nominal value.It is pulled down. Feedback input for the switching section 1. This pin is connected to a resistive voltage-divider from OUT1 to PGND to adjust the output voltage from 0.9 V to 5.5 V. Output voltage sense for the switching section 1.This pin must be directly connected to the output voltage of the switching section. DC voltage error compensation pin for the switching section 1. Device supply voltage pin. It supplies all the internal analog circuitry except the gate drivers (see LDO5). Connect this pin to LDO5. Internal 1.237 V high accuracy voltage reference. It can deliver 50 A. Bypass to SGND with a 100 nF capacitor to reduce noise.
20
CSENSE1
21 22 23
PHASE1 HGATE1 BOOT1
24
SKIP
25
EN1
26
PGOOD1
27
PGOOD2
28
FB1
29 30 31 32
OUT1 COMP1 VCC VREF
7/47
Functional block diagram
PM6681A
3
Functional block diagram
Figure 3. Functional block diagram
8/47
PM6681A
Maximum ratings
4
Maximum ratings
Table 3. Absolute maximum ratings
Parameter V5SW, LDO5 to PGND VIN to PGND HGATEx and BOOTx, to PHASEx PHASEx to PGND CSENSEx, to PGND CSENSEx to BOOTx LGATEx to PGND FBx, COMPx, SKIP, FSEL,VREF to SGND, LDO FB PGND to SGND SHDN, PGOODx, OUTx, VCC, ENx to SGND Power dissipation at TA = 25 C Maximum withstanding voltage range test condition: CDF-AEC-Q100-002- "human body model" acceptance criteria: "normal performance"
1. PHASE to PGND up to -2.5 V for t < 10 ns 2. LGATEx to PGND up to -1 V for t < 40 ns
Value -0.3 to 6 -0.3 to 36 -0.3 to 6 -0.6 (1) to36 -0.6 to 42 -6 to 0.3 -0.3
(2)
Unit V V V V V V V V V V W V
to LDO5 +0.3
-0.3 to Vcc+0.3 -0.3 to 0.3 -0.3 to 6 2.8 VIN Other pins 1000 2000
Table 4.
Symbol TSTG RthJA TJ TA
Thermal data
Parameter Storage temperature range Thermal resistance junction to ambient Junction operating temperature range Operating ambient temperature range Value -50 to 150 35 -40 to 125 -40 to 85 Unit C C/W C C
Table 5.
Symbol VIN VCC VV5SW
Recommended operating conditions
Value Parameter Input voltage range IC supply voltage VV5SW maximum operating range Test condition Min LDO5 in regulation 5.5 4.5 Typ Max 36 5.5 5.5 V V V Unit
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Electrical characteristics
PM6681A
5
Table 6.
Symbol
Electrical characteristics
Electrical characteristics (VIN = 24 V; TJ = 25 C, unless otherwise specified)
Parameter Test condition Min Typ Max Unit
Supply section Turn-on voltage threshold VV5SW Turn-off voltage threshold Hysteresis RDS(on) LDO5 internal bootstrap switch resistance OUTx, OUTx discharge-mode On-resistance OUTx, OUTx discharge-mode Synchronous rectifier turn-on level Pin Ish Isb Operating power consumption Operating current sunk by VIN Operating current sunk by VIN FBx > VREF, Vref in regulation, V5WS to 5 V SHDN connected to GND ENx to GND, V5SW to GND 20 250 V5SW > 4.9 V 4.6 20 4.8 4.75 50 1.8 3 4.9 V V mV
18
25
0.2
0.35
0.6
V
4 30 380
mW A A
Shutdown section Device on threshold VSHDN Device off threshold 1.2 0.8 1.5 0.85 1.7 0.9 V V
soft-start section soft-star t ramp time Current limit and zero crossing comparator ICSENSE Input bias current limit (1) Comparator offset Zero crossing comparator offset Fixed negative current limit threshold VCSENSE - VPGND VPGND - VPHASE VPGND - VPHASE 90 -6 -1 -120 100 110 6 11 A mV mV mV 2 3.5 ms
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PM6681A Table 6.
Symbol On time pulse width FSEL to GND OUT1 = 3.3 V OUT2 = 1.8 V Ton On time duration_ @VIN = 24 V FSEL to VREF OUT1 = 3.3 V OUT2 = 1.8 V FSEL to LDO5 OUT1 = 3.3 V OUT2 =1.8 V OFF time TOFFMIN Minimum off time @VIN = 24 V
Electrical characteristics Electrical characteristics (VIN = 24 V; TJ = 25 C, unless otherwise specified) (continued)
Parameter Test condition Min Typ Max Unit
575 195 390 145 285 110
680 230 460 175 340 135
785 265 530 ns 205 395 160
350
500
ns
Voltage reference VREF Voltage accuracy Load regulation Undervoltage lockout fault threshold Integrator FB FB COMP COMP Voltage accuracy Input bias current Over voltage clamp Under voltage clamp
(1)
4 V < VLDO5 < 5.5 V -100 A< IREF < 100 A Falling edge of REF
1.224 -4
1.236
1.249 4 0.95
V mV mV
+891 0.1 250
+909
mV A mV
Normal mode
-150
Line regulation Both SMPS, 6 V < Vin < 36 V (1) LDO5 linear regulator VLDO5 LDO5 linear output voltage LDO5 line regulation ILDO5 ULVO LDO5 current limit Under voltage lockout of LDO5 6 V < VIN < 36 V, 0 < ILDO5 < 50 mA 6 V < VIN < 36 V, ILDO5 = 20 mA , VLDO5 > UVLO 270 3.94 330 4 4.9 5.0 5.1 0.004 400 4.13 V %/V mA V 1 %
LDO linear regulator 4.5 V< V5SW < 5.5 V 0.5 mA < ILDO < 50 mA LDO FB connected to LDO
VLDO
LDO linear output voltage
0.887
0.905
0.923
V
11/47
Electrical characteristics Table 6.
Symbol ILDO ILDO FB
PM6681A
Electrical characteristics (VIN = 24 V; TJ = 25 C, unless otherwise specified) (continued)
Parameter LDO current limit Input bias current
(1)
Test condition
Min 170
Typ 220 0.1
Max 270
Unit mA A
High and low gate drivers HGATEx high state (pull-up) HGATE driver on-resistance HGATEx low state (pull-down) LGATEx high state (pull-up) LGATE driver on-resistance LGATEx low state (pull-down) PGOOD pins UVP/OVP protections OVP UVP Over voltage threshold Under voltage threshold Upper threshold (VFB-VREF) PGOOD1,2 Lower threshold (VFB-VREF) IPGOOD1,2 VPGOOD1,2 PGOOD leakage current output low voltage VPGOOD1,2 forced to 5.5 V ISink = 4 mA 150 88 91 94 1 250 % uA mV Both SMPS sections with respect to VREF, OUT1 = 5 V, OUT2 = 3.3 V 112 65 107 116 68 110 120 71 113 % % % 0.8 1.2 1.6 1.4 2.7 2.1 2.0 3
Power management pins SMPS disabled level EN1,2 SMPS enabled level Frequency selection range FSEL
(1) (1)
0.8 V 2.4 0.5 1.0 VLDO5 0.8 0.5 1.0 VLDO5 0.8 1 1 1 1 A VLDO5 1.5 V VLDO5 1.5 V
Low level (1) Middle level (1) High level (1)
Pulse skip mode SKIP Ultrasonic mode PWM mode
(1) (1)
(1)
VEN1,2 = 0 to 5 V Input leakage current VSKIP = 0 to 5 V VSHDN = 0 to 5 V VFSEL = 0 to 5 V
1. by design
12/47
PM6681A
Typical operating characteristics
6
Typical operating characteristics
(FSEL = GND (200/300 kHz), SKIP = GND (skip mode), V5SW = EXT5 V (external 5 V power supply connected), input voltage VIN = 24 V, SHDN, EN1 and EN2 high, OUT1 = 3.3 V, OUT2 = 1.8 V, no load, LDO = 3.3 V, (LDO_FB divider = 5.6 k and 15 k) unless specified) Figure 4. Efficiency vs current load Figure 5.
\
Efficiency vs current load
Figure 6.
PWM no load battery current Figure 7. vs input voltage
\
No-audible skip no load battery current vs input voltage
Figure 8.
Skip no load battery current vs input voltage
Figure 9.
\
Shutdown mode input battery current vs input voltage
13/47
Typical operating characteristics
PM6681A
Figure 10. Standby mode input battery current vs input voltage
Figure 11. Voltage reference vs load current
\
Figure 12. OUT1 = 3.3 V switching frequency
Figure 13. OUT2 = 1.8 V switching frequency
\
Figure 14. OUT1 = 3.3 V load regulation Figure 15. OUT2 = 1.8 V load regulation
\
14/47
PM6681A
Typical operating characteristics
Figure 16. LDO5 vs output current
Figure 17. LDO vs output current
\
Figure 18. SHDN, OUT1, LDO and LDO5 Figure 19. OUT1, OUT2, LDO and LDO5 power-up power-up
\
Figure 20. OUT1 = 3.3 V load transient 0 to 2 A
Figure 21. OUT2 = 1.8 V load transient 0 to 2 A
\
15/47
Typical operating characteristics Figure 22. 3.3 V soft-start (1 load)
PM6681A Figure 23. 1.8 V soft-start (0.6 load)
\
Figure 24. OUT1 = 3.3 V soft-end (no load)
Figure 25. OUT2 = 1.8 V soft-end (no load)
\
Figure 26. OUT1 = 3.3 V soft-end (0.8 load)
Figure 27. OUT2 = 1.8 V soft-end (0.6 load)
\
16/47
PM6681A
Typical operating characteristics
Figure 28. 3.3 V no-audible skip mode
Figure 29. 1.8 V no-audible skip mode
\
17/47
Device description
PM6681A
7
Device description
The PM6681A is a dual step-down controller dedicated to provide logic voltages for industrial automation application and notebook computer. It is based on a constant on time control architecture. This type of control offers a very fast load transient response with a minimum external component count. A typical application circuit is shown in Figure 1. The PM6681A regulates two adjustable output voltages: OUT1 and OUT2. The switching frequency of the two sections can be adjusted to three different values. In order to maximize the efficiency at light load condition, a pulse skipping mode can be selected. The PM6681A includes also a 5 V linear regulator (LDO5) that can power the switching drivers. If the output OUT1 regulates 5 V, in order to maximize the efficiency in higher consumption status, the linear regulator can be turned off and their outputs can be supplied directly from the switching outputs. Moreover, the PM6681A includes also a linear regulator with an output voltage adjustable from 0.9 V to 3.3 V. It can provide 100 mA of peak current. The PM6681A provides protection versus overvoltage, undervoltage and overtemperature as well as Power Good signals for monitoring purposes. An external 1.237 V reference is available.
7.1
Constant on time PWM control
If the SKIP pin is tied to 5 V, the device works in PWM mode. Each power section has an independent on time control.The PM6681A employees a pseudo-fixed switching frequency, constant on time (COT) controller as core of the switched mode section. Each power section has an independent COT control. The COT controller is based on a relatively simple algorithm and uses the ripple voltage due to the output capacitor's ESR to trigger the fixed on-time one-shot generator. In this way, the output capacitor's ESR acts as a current sense resistor providing the appropriate ramp signal to the PWM comparator. On-time one-shot duration is directly proportional to the output voltage, sensed at the OUT1/OUT2 pins, and inversely proportional to the input voltage, sensed at the VIN pin, as follows: Equation 1
Ton = K ×
Vout Vin
This leads to a nearly constant switching frequency, regardless of input and output voltages. When the output voltage goes lower than the regulated voltage Vreg, the on-time one shot generator directly drives the high side MOSFET for a fixed on time allowing the inductor current to increase; after the on time, an off time phase, in which the low side MOSFET is turned on, follows. Figure 30 shows the inductor current and the output voltage waveforms in PWM mode.
18/47
PM6681A Figure 30. Constant on time PWM control
V
Device description
The duty cycle of the buck converter in steady state is:
Equation 2
D=
Vout in
The PWM control works at a nearly fixed frequency fSW:
Equation 3
fsw
D = = Ton
Vout Vin =1 K on Vout K on × Vin
As mentioned the steady state switching frequency is theoretically independent from battery voltage and from output voltage. Actually the frequency depends on parasitic voltage drops that are present during the charging path (high side switch resistance, inductor resistance (DCR) and discharging path (low side switch resistance, DCR). As a result the switching frequency increases as a function of the load current. Standard switching frequency values can be selected for both sections by connecting pin FSEL to SGND, VREF or LDO5 pin. The following table shows the typical switching frequencies that can be obtained as a function of the programmed output voltage. The measures are referred to switching sections with 2 A load, 12 V input voltage and working in continuous conduction mode.
Table 7. FSEL pin selection: typical switching frequency
Fsw @ OUT1 = 1.5 V (kHz) FSEL = GND FSEL = VREF FSEL = LDO5 200 290 390 Fsw @ OUT2 = 1.05 V (kHz) 325 425 590
19/47
Device description
PM6681A
7.2
Constant on time architecture
Figure 31 shows the simplified block diagram of a constant on time controller. A minimum off-time constrain (350 ns typ.) is introduced to allow inductor valley current sensing on synchronous switch. A minimum on-time (130 ns) is also introduced to assure the start-up switching sequence.
PM6681A has a one-shot generator for each power section that turns on the high side MOSFET when the following conditions are satisfied simultaneously: the PWM comparator is high, the synchronous rectifier current is below the current limit threshold, and the minimum off-time has timed out. Once the on-time has timed out, the high side switch is turned off, while the synchronous switch is turned on according to the anti-cross conduction circuitry management. When the negative input voltage at the PWM comparator (Figure 31), which is a scaleddown replica of the output voltage (see the external R1/R2 divider in Figure 32), reaches the valley limit (determined by internal reference Vr = 0.9 V), the low-side MOSFET is turned off according to the anti-cross conduction logic once again, and a new cycle begins.
Figure 31. Constant on-time block diagram
7.3
Output ripple compensation and loop stability
In a classic constant on time control, the system regulates the valley value of the output voltage and not the average value, as shown in Figure 30. In this condition, the output voltage ripple is source of a DC static error. To compensate this error, an integrator network can be introduced in the control loop, by connecting the output voltage to the COMP1/COMP2 (for the OUT1 and OUT2 sections respectively) pin through a capacitor CINT as in Figure 32.
20/47
PM6681A Figure 32. Circuitry for output ripple compensation
Device description
The integrator amplifier generates a current, proportional to the DC errors between the FB voltage and Vr, which decreases the output voltage in order to compensate the total static error, including the voltage drop on PCB traces. In addition, CINT provides an AC path for the output ripple. In steady state, the voltage on COMP1/COMP2 pin is the sum of the reference voltage Vr and the output ripple (see Figure 32). In fact when the voltage on the COMP pin reaches Vr, a fixed Ton begins and the output increases. For example, we consider Vout = 5 V with an output ripple of V = 50 mV. Considering CINT >> CFILT, the CINT DC voltage drop VCINT is about 5 V - Vr + 25 mV = 4.125 V. CINT assures an AC path for the output voltage ripple. Then the COMP pin ripple is a replica of the output ripple, with a DC value of Vr + 25 mV = 925 mV. For more details about the output ripple compensation network, see the paragraph "Closing the integrator loop" in the design guidelines. In steady state the FB pin voltage is about Vr and the regulated output voltage depends on the external divider:
Equation 4
R OUT = Vr × 1 + 2 R1
7.4
Pulse skip mode
If the SKIP pin is tied to ground, the device works in skip mode. At light loads a zero-crossing comparator truncates the low-side switch on-time when the inductor current becomes negative. In this condition the section works in discontinuous conduction mode. The threshold between continuous and discontinuous conduction mode is:
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Device description Equation 5
PM6681A
ILOAD(SKIP) =
VIN - VOUT × TON 2×L
For higher loads the inductor current doesn't cross the zero and the device works in the same way as in PWM mode and the frequency is fixed to the nominal value.
Figure 33. PWM and pulse skip mode inductor current
T
Figure 33 shows inductor current waveforms in PWM and SKIP mode. In order to keep average inductor current equal to load current, in SKIP mode some switching cycles are skipped. When the output ripple reaches the regulated voltage Vreg, a new cycle begins. The off cycle duration and the switching frequency depend on the load condition.
As a result of the control technique, losses are reduced at light loads, improving the system efficiency.
7.5
No-audible skip mode
If SKIP pin is tied to VREF, a no-audible skip mode with a minimum switching frequency of 33 kHz is enabled. At light load condition, If there is not a new switching cycle within a 30 s (typ.) period, a no-audible skip mode cycle begins.
Figure 34. No audible skip mode
Inductor current No audible skip m ode 30us ime
0 Low side
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PM6681A
Device description
The low side switch is turned on until the output voltage crosses about Vreg+1 %. Then the high side MOSFET is turned on for a fixed on time period. Afterwards the low side switch is enabled until the inductor current reaches the zero-crossing threshold. This keeps the switching frequency higher than 33 kHz. As a consequence of the control, the regulated voltage can be slightly higher than Vreg (up to 1 %). If, due to the load, the frequency is higher than 33 kHz, the device works like in skip mode. No-audible skip mode reduces audio frequency noise that may occur in pulse skip mode at very light loads, keeping the efficiency higher than in PWM mode.
7.6
Current limit
The current-limit circuit employs a "valley" current-sensing algorithm. During the conduction time of the low side MOSFET the current flowing through it is sensed. The current-sensing element is the low side MOSFET on-resistance (Figure 35).
Figure 35. RDS(on) sensing technique
2
An internal 100 A current source is connected to CSENSE pin and determines a voltage drop on RCSENSE. If the voltage across the sensing element is greater than this voltage drop, the controller doesn't initiate a new cycle. A new cycle starts only when the sensed current goes below the current limit. Since the current limit circuit is a valley current limit, the actual peak current limit is greater than the current limit threshold by an amount equal to the inductor ripple current. Moreover the maximum output current is equal to the valley current limit plus half of the inductor ripple current:
Equation 6
ILOAD (max) = ILvalley +
IL
The output current limit depends on the current ripple, as shown in Figure 36:
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Device description Figure 36. Current waveforms in current limit conditions
Current DC current limit = maximum load
PM6681A
Maximum load current is influenced by the inductor current ripple
Inductor current
Val ley current threshold Time
Being fixed the valley threshold, the greater the current ripple is, greater the DC output current is: The valley current limit can be set with resistor RCSENSE:
Equation 7 (RDS(on) sensing technique)
RCSENSE =
RDSon × ILvalley ICSENSE
Where ICSENSE = 100 A, RDS(on) is the drain-source on resistance of the low side switch. Consider the temperature effect and the worst case value in RDS(on) calculation. The accuracy of the valley current threshold detection depends on the offset of the internal comparator (VOFF) and on the accuracy of the current generator(ICSENSE):
Equation 8
ILvalley ILvalley
=
RCSENSE RSNS ICSENSE VOFF + × 100 + + ICSENSE RSNS RCSENSE × ICSENSE RCSENSE
Where RSNS is the sensing element (RDS(on)). PM6681A provides also a fixed negative peak current limit to prevent an excessive reverse inductor current when the switching section sinks current from the load in PWM mode. This negative current limit threshold is measured between PHASE and SGND pins, comparing the magnitude drop on the PHASE node during the conduction time of the low side MOSFET with an internal fixed voltage of 120 mV. The negative valley-current limit INEG (if the device works in PWM mode) is given by:
Equation 9
INEG =
120mV RDSon
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PM6681A
Device description
7.7
soft-start and soft-end
Each switching section is enabled separately by asserting high EN1/EN2 pins respectively. In order to realize the soft-start, at the startup the overcurrent threshold is set 25 % of the nominal value and the undervoltage protection (see related sections) is disabled. The controller starts charging the output capacitor working in current limit. The overcurrent threshold is increased from 25 % to 100 % of the nominal value with steps of 25 % every 700 s (typ.). After 2.8 ms (typ.) the undervoltage protection is enabled. The s oft start time is not programmable. A minimum capacitor CINT is required to ensure a soft-start without any overshoot on the output:
Equation 10
CINT
6uA × C out ILvalley IL + 4 2
Figure 37. Soft-start waveforms
Sw itching
Curre nt limit threshold
Time
EN1 /EN2
When a switching section is turned off (EN1/EN2 pins low), the controller enters in soft-end mode. The output capacitor is discharged through an internal 18 P-MOSFET switch; when the output voltage reaches 0.3 V, the low-side MOSFET turns on, keeping the output to ground. The soft-end time also depends on load condition.
7.8
Gate drivers
The integrated high-current drivers allow to use different power MOSFETs. The high side driver MOSFET uses a bootstrap circuit which is indirectly supplied by LDO5 output. The BOOT and PHASE pins work respectively as supply and return rails for the HS driver. The low side driver uses the internal LDO5 output for the supply rail and PGND pin as return rail. An important feature of the gate drivers is the adaptive anti-cross conduction protection, which prevents high side and low side MOSFETs from being on at the same time. When the
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Device description
PM6681A
high side MOSFET is turned off the voltage at the phase node begins to fall. The low side MOSFET is turned on when the voltage at the phase node reaches an internal threshold. When the low side MOSFET is turned off, the high side remains off until the LGATE pin voltage goes approximately under 1 V. The power dissipation of the drivers is a function of the total gate charge of the external power MOSFETs and the switching frequency, as shown in the following equation:
Equation 11
Pdriver = Vdriver × Q g × fsw
Where Vdriver is the 5 V driver supply. Reference voltage and bandgap The 1.237 V (typ.) internal bandgap voltage is accurate to 1 % over the temperature range. It is externally available (VREF pin) and can supply up to 100 A and can be used as a voltage threshold for the multifunction pins FSEL and SKIP to select the appropriate working mode. Bypass VREF to ground with a 100 nF minimum capacitor. If VREF goes below 0.87 V (typ.), the system detects a fault condition and all the circuitry is turned off. A toggle on the input voltage (power on reset) or a toggle on SHDN pin is necessary to restart the device. An internal divider of the bandgap provides a voltage reference Vr of 0.9 V. This voltage is used as reference for the linear and the switching regulators outputs. The overvoltage protection, the undervoltage protection and the Power Good signals are referred to Vr.
7.9
Internal linear regulators
The PM6681A has two linear regulators providing respectively 5 V (LDO5) and an adjustable voltage (LDO) at 2 % accuracy. High side drivers, low side drivers and MOSFETs of internal circuitry are supplied by LDO5 output through VCC pin (an external RC filter may be applied between LDO5 and VCC). The linear regulator can provide an average output current of 50 mA and a peak output current of 100mA. Bypass LDO5 output with a minimum 1 F ceramic capacitor and a 4,7 F tantalum capacitor (ESR 2 ). If the 5 V output goes below 4 V, the system detects a fault condition and all the circuitry is turned off. A power on reset or a toggle on SHDN pin is necessary to restart the device. V5SW pin allows to keep the 5 V linear regulator always active or to enable the internal bootstrap-switch over function: if the 5 V switching output is connected to V5SW, when the voltage on V5SW pin is above 4.8 V, an internal 3.0 max P-channel MOSFET switch connects V5SW pin to LDO5 pin and simultaneously LDO5 shuts down. This configuration allows to achieve higher efficiency. V5SW can be connected also to an external 5 V supply. LDO5 regulator turns off and LDO5 is supplied externally. If V5SW is connected to ground, the internal 5 V regulator is always on and supplies LDO5 output.
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PM6681A
Device description
Table 8.
V5SW GND
V5SW multifunction pin
Description The 5 V linear regulator is always turned on and supplies LDO5 output.
Switching 5 V The 5 V linear regulator is turned off when the voltage on V5SW is above 4.8 V and output LDO5 output is supplied by the switching 5 V output. External 5 V supply The 5 V linear regulator is turned off when the voltage on V5SW is above 4.8 V and LDO5 output is supplied by the external 5 V.
The adjustable linear regulator is supplied by LDO5 output. It turns on after LDO5 power up sequence. It can provide up to 100 mA peak current. Set up the feedback resistor divider according to the following formula, to regulate a voltage from 0.9 V to 3.3 V.
Equation 12
Rup LDO = Vr × 1 + R down
where LDO is the desired output voltage, Vr = 0.9 V is the internal reference voltage and Rup and Rdown are the resistors of the feedback divider, as shown in Figure 38:
Figure 38. LDO linear regulator
Bypass LDO5 and LDO output with 1-10 F ceramic capacitor and a 4,7 F tantalum capacitor (ESR 2 ).
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Device description
PM6681A
7.10
Power up sequencing and operative modes
Let's consider SHDN, EN1 and EN2 low at the beginning. The battery voltage is applied as input voltage. The device is in shutdown mode. When the SHDN pin voltage is above the shutdown device on threshold (1.5 V typ.), the controller begins the power-up sequence. All the latched faults are cleared. LDO5 undervoltage control is blanked for 4 ms and the internal regulator LDO5 turns on. If the LDO5 output is above the UVLO threshold after this time, the device enters in standby mode and the adjustable internal linear regulator LDO is turned on. The switching outputs are kept to ground by turning on the low side MOSFETs. When EN1 and EN2 pins are forced high the switching sections begin their soft-start sequence.
Table 9.
Mode Run
Operative modes
Conditions SHDN is high, EN1/EN2 pins are high Description Switching regulators are enabled; internal linear regulators outputs are enabled.
Standby Shutdown
Internal linear regulators active (LDO5 is always on). In Both EN1/EN2 pins are low Standby mode LGATE1/LGATE2 pins are forced high and SHDN pin is high while HGATE1/HGATE2 pins are forced low. SHDN is low All circuits off.
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PM6681A
Monitoring and protections
8
8.1
Monitoring and protections
Power Good signals
The PM6681A provides three independent Power Good signals: one for each switching section (PGOOD1/PGOOD2). PGOOD1/PGOOD2 signals are low if the output voltage is out of 10 % of the designed set point or during the soft-start, standby and shutdown mode.
8.2
Thermal protection
The PM6681A has a thermal protection to preserve the device from overheating. The thermal shutdown occurs when the die temperature goes above +150 C. In this case all internal circuitry is turned off and the power sections are turned off after the discharge mode. A power on reset or a toggle on the SHDN pin is necessary to restart the device.
8.3
Overvoltage protection
When the switching output voltage goes over the OVP threshold (about 116 % of its nominal value), the low side MOSFET turns on. The LS MOSFET is kept on until the output voltage returns under the OVP threshold.
8.4
Undervoltage protection
When the switching output voltage is below 70 % of its nominal value, a latched undervoltage protection occurs. In this case the switching section is immediately disabled and both switches are open. The controller enters in soft-end mode and the output is eventually kept to ground, turning low side MOSFET on. The undervoltage circuit protection is enabled only at the end of the soft-start. Once an overvoltage protection has been detected, a toggle on SHDN, EN1/EN2 pin or a power on reset is necessary to clear the undervoltage fault and starts with a new soft-start phase.
Table 10.
Mode Overvoltage protection Undervoltage protection Thermal shutdown
Protections and operatives modes
Conditions OUT1/OUT2 > 115 % of the nominal value Description LGATE1/LGATE2 pin is forced high until the output voltage is over the OVP threshold, LDO5 remains active.
LGATE1/LGATE2 is forced high after the soft-end OUT1/OUT2 < 70 % of the mode, LDO5 remains active. Exit by a power on reset nominal value or toggling SHDN or EN1/EN2 TJ > +150 C All circuitry off. Exit by a POR on VIN or toggling SHDN.
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Design guidelines
PM6681A
9
Design guidelines
The design of a switching section starts from two parameters:
Input voltage range: in notebook applications it varies from the minimum battery voltage, VINmin to the AC adapter voltage, VINmax. Maximum load current: it is the maximum required output current, ILOAD(max).
9.1
Switching frequency
It's possible to set 3 different working frequency ranges for the two sections with FSEL pin (table 1). Switching frequency mainly influences two parameters:
Inductor size: for a given saturation current and RMS current, greater frequency allows to use lower inductor values, which means smaller size. Efficiency: switching losses are proportional to frequency. High frequency generally involves low efficiency.
9.2
Inductor selection
Once that switching frequency is defined, inductor selection depends on the desired inductor ripple current and load transient performance. Low inductance means great ripple current and could generate great output noise. On the other hand, low inductor values involve fast load transient response. A good compromise between the transient response time, the efficiency, the cost and the size is to choose the inductor value in order to maintain the inductor ripple current IL between 20 % and 50 % of the maximum output current ILOAD(max). The maximum IL occurs at the maximum input voltage. With this considerations, the inductor value can be calculated with the following relationship:
Equation 13
L=
VIN - VOUT VOUT × fsw × IL VIN
where fsw is the switching frequency, VIN is the input voltage, VOUT is the output voltage and IL is the selected inductor ripple current. In order to prevent overtemperature working conditions, inductor must be able to provide an RMS current greater than the maximum RMS inductor current ILRMS:
Equation 14
ILRMS = (ILOAD (max))2 +
Where IL(max) is the maximum ripple current:
(IL (max))2 12
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PM6681A Equation 15
Design guidelines
IL (max) =
VIN max - VOUT V × OUT ` fsw × L VIN max
If hard saturation inductors are used, the inductor saturation current should be much greater than the maximum inductor peak current Ipeak:
Equation 16
Ipeak = ILOAD (max) +
IL (max) 2
Using soft saturation inductors it's possible to choose inductors with saturation current limit nearly to Ipeak. Below there is a list of some inductor manufacturers.
Table 11. Inductor manufacturer
Series SER1360 MLC RLF12560 Inductor value (uH) 1 to 8 0.7 to 4.5 1 to 10 RMS current (A) 6 to 9.5 13.6 to 17.3 7.5 to 14.4 Saturation current (A) 7 to 31 11.5 to 26 7.5 to 18.5
Manufacturer Coilcraft Coilcraft TDK
9.3
Output capacitor
The selection of the output capacitor is based on the ESR value Rout and the voltage rating rather than on the capacitor value Cout. The output capacitor has to satisfy the output voltage ripple requirements. Lower inductor value can reduce the size of the choke but increases the inductor current ripple IL. Since the voltage ripple VRIPPLEout is given by:
Equation 17
VRIPPLEout = R out × IL A low ESR capacitor is required to reduce the output voltage ripple. Switching sections can work correctly even with 20 mV output ripple. However, to reduce jitter noise between the two switching sections it's preferable to work with an output voltage ripple greater than 30 mV. If lower output ripple is required, a further compensation network is needed (see Closing the integrator loop paragraph). Finally the output capacitor choice deeply impacts on the load transient response (see Load transient response paragraph). Below there is a list of some capacitor manufacturers.
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Design guidelines
PM6681A
Table 12.
Output capacitor manufacturer
Series POSCAP TPB,TPD, TPE SPCAP UD, UE Capacitor value (uF) 100 to 470 100 to 470 Rated voltage (V) 2.5 to 6.3 2 to 6.3 ESR max (m) 12 to 65 7 to 18
Manufacturer SANYO Panasonic
9.4
Input capacitors selection
In a buck topology converter the current that flows into the input capacitor is a pulsed current with zero average value. The input RMS current of the two switching sections can be roughly estimated as follows:
Equation 18
2 ICinRMS = D1 × I1 × (1 - D1) + D 2 × I2 × (1 - D 2 ) 2
Where D1, D2 are the duty cycles and I1, I2 are the maximum load currents of the two sections. Input capacitor should be chosen with an RMS rated current higher than the maximum RMS current given by both sections. Tantalum capacitors are good in term of low ESR and small size, but they occasionally can burn out if subjected to very high current during the charge. Ceramic capacitors have usually a higher RMS current rating with smaller size and they remain the best choice. Below there is a list of some ceramic capacitor manufacturers.
Table 13. Input capacitor manufacturer
Series UMK432 X5506MM-T C3225X5R1E106M Capacitor value (uF) 10 10 Rated voltage (V) 50 25
Manufacturer Tayio yuden TDK
9.5
Power MOSFETs
Logic-level MOSFETs are recommended, since low side and high side gate drivers are powered by LDO5. Their breakdown voltage VBRDSS must be higher than VINmax. In notebook applications, power management efficiency is a high level requirement. The power dissipation on the power switches becomes an important factor in switching selections. Losses of high-side and low-side MOSFETs depend on their working conditions. The power dissipation of the high-side MOSFET is given by:
Equation 19
PDHighSide = Pconduction + Pswitching
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PM6681A
Design guidelines
Maximum conduction losses are approximately:
Equation 20
Pconduction = RDSon ×
VOUT × ILOAD (max)2 VIN min
where RDS(on) is the drain-source on resistance of the high side MOSFET. Switching losses are approximately:
Equation 21
Pswitching =
VIN × (ILOAD (max) -
IL I ) × t on × fsw VIN × (ILOAD (max) + L ) × t off × fsw 2 2 + 2 2
where ton and toff are the switching times of the turn off and turn off phases of the MOSFET. As general rule, high side MOSFETs with low gate charge are recommended, in order to minimize driver losses. Below there is a list of possible choices for the high side MOSFET.
Table 14. High side MOSFET manufacturer
Type STS12NH3LL STS17NH3LL Gate charge (nC) 10 18 Rated reverse voltage (V) 30 30
Manufacturer ST ST
The power dissipation of the low side MOSFET is given by:
Equation 22
PDLowSide = Pconduction
Maximum conduction losses occur at the maximum input voltage:
Equation 23
V Pconduction = RDSon × 1 - OUT V IN max
× ILOAD (max)2
Choose a synchronous rectifier with low RDS(on). When high side MOSFET turns on, the fast variation of the phase node voltage can bring up even the low side gate through its gate drain capacitance CRSS, causing cross-conduction problems. Choose a low side MOSFET that minimizes the ratio CRSS/CGS (CGS = CISS - CRSS). Below there is a list of some possible low side MOSFETs.
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Design guidelines
PM6681A
Table 15.
Low side MOSFET manufacturer
Type STS17NF3LL STS25NH3LL RDS(on) (m) 5.5 3.5
CRSS CGS
Manufacturer ST ST
Rated reverse voltage (V) 30 30
0.047 0.011
Dual N-channel MOSFETs can be used in applications with a maximum output current of about 3 A. Below there is a list of some MOSFET manufacturers.
Table 16. Dual MOSFET manufacturer
Type STS8DNH3LL STS4DNF60L RDS(on) (m) 25 65 Gate charge (nC) Rated reverse voltage (V) 10 32 30 60
Manufacturer ST ST
A rectifier across the low side MOSFET is recommended. The rectifier works as a voltage clamp across the synchronous rectifier and reduces the negative inductor swing during the dead time between turning the high-side MOSFET off and the synchronous rectifier on. It can increase the efficiency of the switching section, since it reduces the low side switch losses. A Schottky diode is suitable for its low forward voltage drop (0.3 V). The diode reverse voltage must be greater than the maximum input voltage VINmax. A minimum recovery reverse charge is preferable. Below there is a list of some Schottky diode manufacturers.
Table 17. Schottky diode manufacturer
Series STPS1L30M STPS1L20M Forward voltage (V) 0.34 0.37 Rated reverse voltage (V) 30 20 Reverse current (uA) 0.00039 0.000075
Manufacturer ST ST
9.6
Closing the integrator loop
The design of external feedback network depends on the output voltage ripple. If the ripple is higher than approximately 30 mV, the feedback network (Figure 39) is usually enough to keep the loop stable.
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PM6681A Figure 39. Circuitry for output ripple compensation
Design guidelines
o
The stability of the system depends firstly on the output capacitor zero frequency. The following condition should be satisfied:
Equation 24
fsw > k × fZout =
k 2 × C out × R
ut
where k is a design parameter greater than 3 and Rout is the ESR of the output capacitor. It determinates the minimum integrator capacitor value CINT:
Equation 25
CINT >
gm f 2 × sw - fZout k
×
Vr VOUT
where gm = 50 s is the integrator trans conductance. In order to ensure stability it must be also verified that:
Equation 26
CINT >
gm Vr × 2 × fZout VOUT
In order to reduce ground noise due to load transient on the other section, it is recommended to add a resistor RINT and a capacitor Cfilt that, together with CINT, realize a low pass filter (see Figure 39). The cutoff frequency fCUT must be much greater (10 or more times) than the switching frequency of the section:
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Design guidelines Equation 27
PM6681A
RINT =
1 C × C filt 2 × fCUT × INT CINT + C filt
Due to the capacitive divider (CINT, Cfilt), the ripple voltage at the COMP pin is given by:
Equation 28
VRIPPLEINT = VRIPPLEout ×
CINT = VRIPPLEout × q CINT + C filt
Where VRIPPLEout is the output ripple and q is the attenuation factor of the output ripple. If the ripple is very small (lower than approximately 30 mV), a further compensation network, named virtual ESR network, is needed. This additional part generates a triangular ripple that is added to the ESR output voltage ripple at the input of the integrator network. The complete control schematic is represented in Figure 40.
Figure 40. Virtual ESR network
o
The T node voltage is the sum of the output voltage and the triangular waveform generated by the virtual ESR network. In fact the virtual ESR network behaves like a further equivalent ESR RESR. A good trade-off is to design the network in order to achieve an RESR given by:
Equation 29
RESR =
VRIPPLE -R IL
ut
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PM6681A
Design guidelines
where IL is the inductor current ripple and VRIPPLE is the overall ripple of the T node voltage. It should be chosen higher than approximately 30 mV. The new closed loop gain depends on CINT. In order to ensure stability it must be verified that:
Equation 30
CINT > Where:
Equation 31
gm Vr × 2 × fZ VOUT
fZ =
1 2 × C out × R TOT
where RTOT is the sum of the ESR of the output capacitor Rout and the equivalent ESR given by the virtual ESR network RESR. Moreover CINT must meet the following condition:
Equation 32
fsw > k × fZ =
k 2 × C out × R TOT
Where k is a free design parameter greater than 3 and determines the minimum integrator capacitor value CINT:
Equation 33
CINT >
gm Vr × f VOUT 2 × sw - fZ k
C must be selected as shown:
Equation 34
C > 5 × CINT R must be chosen in order to have enough ripple voltage on integrator input:
Equation 35
R= R1 can be selected as follows:
L RESR × C
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Design guidelines Equation 36
PM6681A
1 R× C× × f Z R1 = 1 R- C × × fZ Example: OUT1 = 1.5 V, fSW = 290 kHz, L = 2.5 H, Cout = 330 F with Rout 12 m. We design RESR = 12 m. We choose CINT = 1 nF by equations 31, 34 and Cfilt = 47 pF, RINT = 1 k by eq.28, 29. C = 5.6 nF by Eq.35. Then R = 36 k (eq.36) and R1 = 3 k (eq.37).
9.7
Other parts design
VIN filter. A VIN pin low pass filter is suggested to reduce switching noise. The low pass filter is shown in the next figure:
Figure 41. VIN pin filter
Typical components values are: R = 3.9 and C = 4.7 F. VCC filter. A VCC low pass filter helps to reject switching commutations noise:
Figure 42. Inductor current waveforms
LD O5 R VC C C
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PM6681A
Design guidelines
Typical components values are: R = 47 and C = 1 F. VREF capacitor. A 10 nF to 100 nF ceramic capacitor on VREF pin must be added to ensure noise rejection. LDO5 output capacitors. Bypass the output of each linear regulator with 1 F ceramic capacitor closer to the LDO pin and a 4.7 F tantalum capacitor (ESR = 2 ). In most applicative conditions a 4.7 F ceramic output capacitor can be enough to ensure stability. Bootstrap circuit. The external bootstrap circuit is represented in the next figure:
Figure 43. Bootstrap circuit
D D R BOOT RO LDO5 O5 BOOT BOOT CBOOT L PH ASE PH
The bootstrap circuit capacitor value CBOOT must provide the total gate charge to the high side MOSFET during turn on phase. A typical value is 100 nF. The bootstrap diode D must charge the capacitor during the off time phases. The maximum rated voltage must be higher than VINmax. A resistor RBOOT on the BOOT pin could be added in order to reduce noise when the phase node rises up, working like a gate resistor for the turn on phase of the high side MOSFET.
9.8
Design example
The following design example considers an input voltage from 7 V to 16 V. The two switching outputs are OUT1 = 1.5 V and OUT2 = 1.05 V and must deliver a maximum current of 5 A. The selected switching frequencies are about 290 kHz for OUT1 section and about 425 kHz for OUT2 section (see Table 1).
9.8.1
Inductor selection
OUT1: ILOAD = 2.5 A, 45 % ripple current.
L=
3.3V (20V - 3.3V) 8.2H 290KHz 24V 0.45 2.5
We choose standard value L = 8.2 H. IL(max) = 1.16 A @ VIN = 24 V. ILRMS = 2.53 A
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Design guidelines
PM6681A
Ipeak = 2.5 A + 0.58 A = 3.08 A OUT2 : ILOAD = 2.5 A, 35 % ripple current. 1.8V (24V - 1.8V) 4.76H 425KHz 24V 0.35 2.5
L=
We choose standard value L = 4.7 H. IL(max) = 0.89 A @ VIN = 24 V. ILRMS = 2.513 A Ipeak = 2.5 A + 0.443 A = 2.943 A
9.8.2
Output capacitor selection
We would like to have an output ripple smaller than 25 mV. OUT1: POSCAP 4TPE150MI OUT2: POSCAP 6TPE220M
9.8.3
Power MOSFETs
OUT1:High side: STS5NF60L Low side: STS7NF60L OUT2:High side: STS5NF60L Low side: STS7NF60L
9.8.4
Current limit
OUT1:
ILvalley (min) = ILOAD(max) -
IL (min) = 4.12A 2
RCSENSE
4.12A 16.25m 670 100A
(Let's assume the maximum temperature Tmax = 75 C in RDS(on) calculation) OUT2:
ILvalley (min) = ILOAD (max) -
IL (min) = 4 .2 A 2
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PM6681A
Design guidelines
RCSENSE
4 . 2A 16.25m 680 100A
(Let's assume Tmax = 75 C in RDS(on) calculation)
9.8.5
Input capacitor
Maximum input capacitor RMS current is about 1.1 A. Then ICinRMS > 1.1 A We can put two 10 F ceramic capacitors with Irms = 1.5 A.
9.8.6
Synchronous rectifier
OUT1: Schottky diode STPS1L40M OUT2: Schottky diode STPS1L40M
9.8.7
Integrator loop
(Refer to Figure 40) OUT1: The ripple is smaller than 40mV, then the virtual ESR network is required. CINT = 1 nF; Cfilt = 47 pF; RINT = 1 k C = 5.6 nF; R = 36 k; R1 = 3 k OUT2: The ripple is smaller than 40mV, then the virtual ESR network is required. CINT = 1 nF; Cfilt = 110 pF; RINT = 1 k C = 5.6 nF; R = 22 k; R1 = 3.3 k
9.8.8
Output feedback divider
(Refer to Figure 32) OUT1: R1 = 10 k; R2 = 6.8 k OUT2: R1 = 11 k; R2 = 1.8 k
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Layout guidelines
PM6681A
10
Layout guidelines
The layout is very important in terms of efficiency, stability and noise of the system. It is possible to refer to the PM6681A demonstration board for a complete layout example. For good PC board layout follows these guidelines: Place on the top side all the power components (inductors, input and output capacitors, MOSFETs and diodes). Refer them to a power ground plan, PGND. If possible, reserve a layer to PGND plan. The PGND plan is the same for both the switching sections. AC current paths layout is very critical (see Figure 44). The first priority is to minimize their length. Trace the LS MOSFET connection to PGND plan (with or without current sense resistor RSENSE) as short as possible. Place the synchronous diode D near the LS MOSFET. Connect the LS MOSFET drain to the switching node with a short trace. Place input capacitors near HS MOSFET drain. It is recommended to use the same input voltage plan for both the switching sections, in order to put together all input capacitors. Place all the sensitive analog signals (feedbacks, voltage reference and current sense paths) on the bottom side of the board or in an inner layer. Isolate them from the power top side with a signal ground layer, SGND. Connect the SGND and PGND plans only in one point (a multiple via connection is preferable to a 0 ohm resistor connection) near the PGND device pin. Place the device on the top or on the bottom size and connect the exposed pad and the SGND pins to the SGND plan (see Figure 44).
Figure 44. Current paths, ground connection and driver traces layout
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PM6681A
Layout guidelines
As general rule, make the high side and low side drivers traces wide and short. The high side driver is powered by the bootstrap circuit. It's very important to place capacitor CBOOT and diode DBOOT as near as possible to the HGATE pin (for example on the layer opposite to the device). Route HGATE and PHASE traces as near as possible in order to minimize the area between them. The Low side gate driver is powered by the 5 V linear regulator output. Placing PGND and LGATE pins near the low side MOSFETs reduces the length of the traces and the crosstalk noise between the two sections. The linear regulator output LDO5 is referred to SGND as long as the reference voltage Vref. Place their output filtering capacitors as near as possible to the device. Place input filtering capacitors near VCC and VIN pins. It would be better if the feedback networks connected to COMP, FB and OUT pins are "referred" to SGND in the same point as reference voltage Vref. To avoid capacitive coupling place these traces as far as possible from the gate drivers and phase (switching) paths. Place the current sense traces on the bottom side. If low side MOSFET RDS(on) sensing is enabled, use a dedicated connection between the switching node and the current limit resistor RCSENSE.
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Package mechanical data
PM6681A
11
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
Table 18. VFQFPN32 5 x 5 x 1.0 mm pitch 0.50
Databook (mm) Dim. Min A A1 A3 b D D2 E E2 e L ddd 0.3 4.85 0.18 4.85 0.8 0 Typ 0.9 0.02 0.2 0.25 5 See exposed pad variations 5 See exposed pad variations 0.5 0.4 0.5 0.05
(2) (2)
Max 1 0.05
0.3 5.15
5.15
Table 19.
Exposed pad variations
(1)(2)D2
E2 Max 3.20 Min 2.90 Typ 3.10 Max 3.20
Min 2.90
Typ 3.10
1. VFQFPN stands for thermally enhanced very thin fine pitch quad flat package no lead. Very thin: A = 1.00 mm Max. 2. Dimensions D2 and E2 are not in accordance with JEDEC.
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PM6681A Figure 45. Package dimensions
Package mechanical data
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Revision history
PM6681A
12
Revision history
Table 20.
Date 02-Nov-2006 03-Jun-2008 26-Jun-2008
Document revision history
Revision 1 2 3 Initial release Document status promoted from Target specification to Datasheet Updated: Figure 1 on page 4, Figure 27 on page 16, Figure 16 and Figure 17 on page 15 Changes
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PM6681A
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