PD84001
RF power transistor the LdmoST plastic family
Features
Excellent thermal stability Common source configuration Broadband performances POUT = 1 W with 15 dB gain @ 870 MHz Plastic package ESD protection Supplied in tape and reel In compliance with the 2002/95/EC european directive Figure 1. Pin connection
SOT-89
Description
The PD84001 is a common source N-channel, enhancement-mode lateral field-effect RF power transistor. It is designed for high gain, broad band commercial and industrial applications. It operates at 7 V in common source mode at frequencies of up to 1 GHz. PD84001's superior gain and efficiency makes it an ideal solution for portable radio and UHF RFID reader.
Source
Source Gate Drain
Table 1.
Device summary
Marking 8401 Package SOT-89 Packaging Tape and reel
Order code PD84001
August 2008
Rev 4
1/18
www.st.com 18
Contents
PD84001
Contents
1 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 1.2 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 2.2 2.3 2.4 Static . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 D ynamic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ESD protection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Moisture sensitivity level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 4 5 6
Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Typical performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6.1 6.2 Thermal pad and via design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Soldering profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
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PD84001
Electrical data
1
1.1
Electrical data
Maximum ratings
Table 2.
Symbol V(BR)DSS VGS ID PDISS TJ TSTG
Absolute maximum ratings (TCASE = +25 C)
Parameter Drain-source voltage Gate-source voltage Drain current Power dissipation Max. operating junction temperature Storage temperature Value 18 -0.5 to +15 1.5 6 150 -65 to +150 Unit V V A W C C
1.2
Thermal data
Table 3.
Symbol RthJC
Thermal data
Parameter Junction - case thermal resistance Value 21 Unit C/W
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Electrical characteristics
PD84001
2
2.1
Electrical characteristics
Static
Table 4.
Symbol I DSS IGSS VGS(Q) VDS(ON) CISS COSS CRSS VGS = 0 V VGS = 5 V VDS = 10 V VGS = 10 V VGS = 0 V VGS = 0 V VGS = 0 V
Static (TCASE = +25 oC)
Test conditions VDS = 28 V V DS = 0 V ID = 250 A ID = 0.4 A VDS = 7 V VDS = 7 V VDS = 7 V f = 1 MHz f = 1 MHz f = 1 MHz 2.0 3.0 0.6 14.7 13.3 1.3 Min. Typ. Max. 1 1 5.0 Unit A A V V pF pF pF
2.2
Dynamic
Table 5.
Symbol POUT GPS hD
Dynamic
Test conditions VDD = 7.5 V, IDQ = 50 mA, PIN = 17 dBm, f = 870 MHz VDD = 7.5 V, IDQ = 50 mA, POUT = 30 dBm, f = 870 MHz VDD = 7.5 V, IDQ = 50 mA PIN = 17 dBm, f = 870 MHz Min. 30 13 55 20:1 Typ. 31 15 60 Max. Unit dBm dB % VSWR
Load VDD = 7.5 V, IDQ = 50 mA, POUT = 1 W, f = 870 MHz mismatch All phase angles
2.3
ESD protection characteristics
Table 6. ESD protection characteristics
Test conditions Human body model Machine model Class 2 M3
2.4
Moisture sensitivity level
Table 7. Moisture sensitivity level
Test methodology J-STD-020B Rating MSL 3
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PD84001
Impedance
3
Impedance
Figure 2. Current conventions
Table 8.
Impedance data
Freq. (MHz) 920 900 880 860 840 820 800 ZGS () 4.0 + j4.3 3.6 + j4.3 3.3 + j4.1 3.1 + j3.7 2.9 + j3.4 2.8 + j3.0 2.7 + j2.5 ZDL() 3.7 + j6.2 3.9 + j5.5 4.1 + j4.7 4.3 + j4.0 4.5 + j3.2 4.8 + j2.4 5.0 + j1.6
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Typical performance
PD84001
4
Figure 3.
Typical performance
VGS vs ID Figure 4. DC output characteristics
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PD84001
Typical performance
Figure 5.
3.2 3.0 2.8 2.6 2.4 2.2 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0 1
CRSS vs VDS
Figure 6.
20 18 16 14 Cis s (pF) 12 10 8 6 4 2 0
CISS vs VDS
2.0
Crss (pF)
2
3
4
5 CRSS
6
7
8
9
10 11 12 13 14 15
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CISS V ds (V)
Vds (V)
Figure 7.
28 26 24 22 20 18 16 14 12 10 8 6 4 2 0 0 1
COSS VS VDS
Coss vs Vds
Coss (pF)
2
34
5
6
7
8
9 10 11 12 13 14 15
COSS
Vds (V)
7/18
Typical performance
PD84001
Figure 8.
20 18 16 14 12 10 8 6 18 20
Gain vs output power and frequency
Figure 9.
34 32 30
Output power vs input power and frequency
Pout (dBm)
28 26 24 22 20 18 V dd = 7.5V Idq = 50m A
Gai n (dB)
22
24
26
28
30
32
34
0
2
4
6
8
10
12
14
16
18
20
Pout (dBm)
840 MHz 870 MHz 900 MHz
Pin (dBm)
840 MHz 870 MHz 900 MHz
Figure 10. Efficiency vs output power and frequency
70
Figure 11. Gain and efficiency vs frequency
18 80
60
16
70
50
14
60
40
Gai n (dB)
Nd (%)
12
50
30 V dd = 7.5V Idq = 50m A 20
10 Pin = 17dBm V dd = 7.5V Idq = 50m A
40
8
30
10 18 20 22 24 26 28 30 32 34
6 810
820
830
840
850
860
870
880
890
900
910
20 920
Pout (dBm)
840 MHz 870 MHz 900 MHz
Fre q (MHz)
Gain Nd
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PD84001
Typical performance
Figure 12. Input return loss vs frequency
0
Figure 13. Output power vs input power and VDD
34 32 30 28 26 24 22 Fr e q = 870 MHz Idq = 50m A
-2
Input Return Loss (dB)
Pin = 17dBm V dd = 7.5V Idq = 50m A
-6
-8 20 -10 810 820 830 840 850 860 870 880 890 900 910 920 18 0 2 4 6 8 10 12
Pout (dBm)
-4
14
16
18
20
Fre q (MHz)
9V
Pin (dBm)
7.5V 6V
Figure 14. Efficiency vs output power and VDD Figure 15. Output power and drain current vs drain supply voltage
70
34 Fr e q = 870 MHz Pin = 17dBm Idq = 50m A
0.6
60
32
0.5
50
30
0.4
40
Pout (dBm)
Nd (%)
28
0.3
30
26
0.2
20
24
0.1
10 18 20 22 24 26 28 30 32 34
22 2 3 4 5 6 7 8 9 10
0
Pout (dBm)
9V 7.5V 6V
Vdd (V)
Pout ID
9/18
Typical performance
PD84001
Figure 16. Gain and efficiency vs pin
26 24 22 20
y
90 80 70
18 16 14 12 10 8 -5 0 5 10 15
Fre q = 520 MHz Vdd = 7.5V
50 40 30 20 10 0
20
25
30
Pin (dBm)
Gain- 70mA Ef f - 70mA Gain- 200mA Ef f - 200mA Gain- 50mA Ef f - 50mA Gain- 100mA Ef f - 100mA
10/18
Effi ci ency (%)
60
Gain (dB)
PD84001
Test circuit
5
Test circuit
Figure 17. Test circuit schematic / 840-900 MHz
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Package mechanical data
PD84001
6
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com
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PD84001 Table 9.
Dim. Min A B B1 C C1 D D1 E e e1 H L 1.4 0.44 0.36 0.35 0.35 4.4 1.62 2.29 1.42 2.92 3.94 0.89
Package mechanical data SOT-89 mechanical data
mm. Typ Max 1.6 0.56 0.48 0.44 0.44 4.6 1.83 2.6 1.57 3.07 4.25 1.2 Min 55.1 17.3 14.2 13.8 13.8 173.2 63.8 90.2 55.9 115.0 155.1 35.0 Inch Typ Max 63.0 22.0 18.9 17.3 17.3 181.1 72.0 102.4 61.8 120.9 167.3 47.2
Figure 18. Package dimensions
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Package mechanical data
PD84001
6.1
Thermal pad and via design
Thernal vias are required in the PCB layout to effectively conduct heat away from the package. The via pattern has been designed to address thermal, power dissipation and electrical requirements of the device. The via pattern is based on thru-hole vias with 0.203 mm to 0.330 mm finished hole size on a 0.5 mm to 1.2 mm grid pattern with 0.025 plating on via walls. If micro vias are used in a design, it is suggested that the quantity of vias be increased by a 4:1 ratio to achieve similar results. Figure 19. Pad layout details
SOT-89
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PD84001
Package mechanical data
6.2
Soldering profile
Figure 20 shows the recommeded solder for devices that have Pb-free terminal plating and where a Pb-free solder is used. Figure 20. Recommended solder profile
Figure 21 shows the recommeded solder for devices with Pb-free terminal plating used with leaded solder, or for devices with leaded terminal plating used with a leaded solder. Figure 21. Recommended solder profile for leaded devices
15/18
Package mechanical data Figure 22. Reel information
PD84001
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PD84001
Revision history
7
Revision history
Table 10.
Date 06-Dec-2006 16-May-2007 05-Jun-2007 25-Aug-2008
Document revision history
Revision 1 2 3 4 Initial release Marking updated Par t number update Updated Table 4 on page 4 Changes
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PD84001
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