L5983
1.5 A step-down switching regulator
Features
1.5 A DC output current 2.9 V to 18 V input voltage Output voltage adjustable from 0.6 V 250 kHz switching frequency, programmable up to 1 MHz Internal soft-start Inhibit Low dropout operation: 100 % duty cycle Voltage feed-forward Zero load current operation Over current and thermal protection VFQFPN8 3 x 3 mm package VFQFPN8 3 x 3 mm
Description
The L5983 is a step down switching regulator with 2.0 A (min.)current limited embedded power MOSFET, so it is able to deliver an output current in excess of 1.5 A DC to the load. The input voltage can range from 2.9 V to 18 V, while the output voltage can be set starting from 0.6 V to VIN. Having a minimum input voltage of 2.9 V, the device is suitable for also for the 3.3 V bus. Requiring a minimum set of external components, the device includes an internal 250 kHz switching frequency oscillator that can be externally adjusted up to 1 MHz. The VFQFPN package with exposed pad allows reducing the RthJA down to approximately 60 C/W.
Applications
Consumer: STB, DVD, DVD recorder, car audio, LCD TV and monitors Industrial: Chargers, PLD, PLA, FPGA Networking: XDSL, modems, DC-DC modules Computer: Optical storage, hard disk drive, printers, audio/graphic cards LED driving Application circuit
Figure 1.
September 2008
Rev 4
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Contents
L5983
Contents
1 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 1.2 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 2.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 4
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.1 4.2 4.3 4.4 4.5 4.6 Oscillator and synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Soft-star t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Error amplifier and compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Over-current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Inhibit function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Hysteretic thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1 5.2 5.3 5.4 Input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.4.1 5.4.2 Type III compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Type II compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.5 5.6 5.7
Thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6 7 8
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Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Pin settings
L5983
1
1.1
Pin settings
Pin connection
Figure 2. Pin connection (top view)
OUT SYNCH INH COMP
VCC GND FSW FB
1.2
Pin description
Table 1.
N. 1
Pin description
Type OUT Regulator output Master/slave synchronization. When it is left floating, a signal with a phase shift of half a period respect to the power turn on is present at the pin. When connected to an external signal at a frequency higher than the internal one, then the device is synchronized by the external signal, with zero phase shift. Connecting together the SYNCH pin of two devices, the one with higher frequency works as master and the other one as slave; so the two powers turn on have a phase shift of half a period. A logical signal (active high) disable the device. With INH higher than 1.9 V the device is OFF and with INH lower than 0.6 V the device is ON. Error amplifier output to be used for loop frequency compensation Feedback input. Connecting the output voltage directly to this pin the output voltage is regulated at 0.6 V. To have higher regulated voltages an external resistor divider is required from Vout to FB pin. The switching frequency can be increased connecting an external resistor from FSW pin and ground. If this pin is left floating the deice works at its free-running frequency of 250 kHz. Ground Unregulated DC input voltage Description
2
SYNCH
3 4 5
INH COMP FB
6 7 8
FSW GND VCC
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Maximum ratings
L5983
2
2.1
Maximum ratings
Absolute maximum ratings
Table 2. Absolute maximum ratings
Parameter Input voltage Output DC voltage Analog pin Inhibit pin Feedback voltage Power dissipation at TA < 60 C Junction temperature range Storage temperature range Value 20 -0.3 to VCC -0.3 to 4 -0.3 to VCC -0.3 to 1.5 1.5 -40 to 150 -55 to 150 W C C V Unit
Symbol Vcc OUT FSW, COMP, SYNCH INH FB PTOT TJ Tstg
2.2
Thermal data
Table 3. Thermal data
Parameter Maximum thermal resistance VFQFPN junction-ambient (1) Value 60 Unit C/W
Symbol RthJA
1. Package mounted on demonstration board.
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Electrical characteristics
L5983
3
Electrical characteristics
Table 4. Electrical characteristics ( TJ = 25 C, VCC = 12 V, unless otherwise specified.)
Values Symbol Parameter Operating input voltage range Turn on VCC threshold Turn off VCC threshold Mosfet on resistance Maximum limiting current Test condition Min VCC VCCON VCCOFF RDS(on) ILIM Oscillator 225 FSW VFSW D FADJ Switching frequency FSW pin voltage Duty cycle Adjustable switching frequency RFSW = 33 k 0 1000
(1) (1) (1) (1)
Unit Typ Max 18 2.9 2.4 140 170 220 2.6 A m V
2.9
(1)
140 2.0 2.3
250
275 kHz 275
220 1.254
V 100 % kHz
Dynamic characteristics VFB Feedback voltage 2.9 V < VCC < 18 V (1) 0.593 0.6 0.607 V
DC characteristics IQ IQST-BY Inhibit Device ON level INH threshold voltage Device OFF level INH current Soft-start FSW pin floating TSS Soft-star t duration FSW = 1 MHz, RFSW = 33 k 7.4 8.2 2 9.1 ms INH = 0 1.9 7.5 10 A 0.6 V Quiescent current Total stand-by quiescent current Duty cycle = 0, VFB = 0.8 V 20 2.4 30 mA A
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Electrical characteristics Table 4. Electrical characteristics ( TJ = 25 C, VCC = 12 V, unless otherwise specified.)
Values Symbol Parameter Test condition Min Error amplifier VCH VCL IF B High level output voltage Low level output voltage Bias source current VFB < 0.6 V VFB > 0.6 V VFB = 0 V to 0.8V VFB = 0.5 V, VCOMP=1 V VFB = 0.7 V, VCOMP=1 V
(2)
L5983
Unit Typ Max
3 V 0.1 1 17 25 100 A mA mA dB
IO SOURCE Source COMP pin IO SINK GV Sink COMP pin Open loop voltage gain
Synchronization function High input voltage Low input voltage Slave sink current Master output amplitude Output pulse width Input pulse width Protection IFBDISC TSHDN(1) FB disconnection source current Thermal shutdown Hystereris 1 150 C 30 A VSYNCH = 2.9 V ISOURCE = 200 A SYNCH floating 70 0.7 3.0 110 ns 2 3.3 V 1 0.9 mA V
1. Specification refered to TJ from -40 to +125 C. Specification in the -40 to +125 C temperature range are assured by design, characterization and statistical correlation. 2. Guaranteed by design.
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Functional description
L5983
4
Functional description
The L5983 is based on a "voltage mode", constant frequency control. The output voltage VOUT is sensed by the feedback pin (FB), compared to an internal reference (0.6 V) providing an error signal that, compared to a fixed frequency sawtooth, controls the on and off time of the power switch. The main internal blocks are shown in the block diagram in Figure 3. They are:
A fully integrated oscillator that provides sawtooth to modulate the duty cycle and the synchronization signal. Its switching frequency can be adjusted by an external resistor. The voltage and frequency feed forward are implemented. The soft-start circuitry to limit inrush current during the start up phase. The voltage mode error amplifier The pulse width modulator and the relative logic circuitry necessary to drive the internal power switch. The high-side driver for embedded p-channel power MOSFET switch. The peak current limit sensing block, to handle over load and short circuit conditions. A voltage regulator and internal reference. It supplies internal circuitry and provides a fixed internal reference. A voltage monitor circuitry (UVLO) that checks the input and internal voltages. A thermal shutdown block, to prevent thermal run away.
Figure 3.
Block diagram
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Functional description
L5983
4.1
Oscillator and synchronization
Figure 4 shows the block diagram of the oscillator circuit. The internal oscillator provides a constant frequency clock. Its frequency depends on the resistor externally connect to FSW pin. In case the FSW pin is left floating the frequency is 250 kHz; it can be increased as shown in Figure 6 by external resistor connected to ground. To improve the line transient performance keeping the PWM gain constant versus the input voltage, the voltage feed forward is implemented by changing the slope of the sawtooth according to the input voltage change (see Figure 5.a). The slope of the sawtooth also changes if the oscillator frequency is increased by the external resistor. In this way a frequency feed forward is implemented (Figure 5.b) in order to keep the PWM gain constant versus the switching frequency (see Section 5.4 for PWM gain expression). On the SYNCH pin the synchronization signal is generated. This signal has a phase shift of 180 with respect to the clock. This delay is useful when two devices are synchronized connecting the SYNCH pin together. When SYNCH pins are connected, the device with higher oscillator frequency works as Master, so the Slave device switches at the frequency of the Master but with a delay of half a period. This minimizes the RMS current flowing through the input capacitor [see L5988D Data sheet]. Figure 4. Oscillator circuit block diagram
Clock
FSW
Clock Generator
Synchronization
SYNCH
Ramp Generator
Sawtooth
The device can be synchronized to work at higher frequency feeding an external clock signal. The synchronization changes the sawtooth amplitude, changing the PWM gain (Figure 5.c). This changing has to be taken into account when the loop stability is studied. To minimize the change of the PWM gain, the free running frequency should be set (with a resistor on FSW pin) only slightly lower than the external clock frequency. This pre-adjusting of the frequency will change the sawtooth slope in order to get negligible the truncation of sawtooth, due to the external synchronization.
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Functional description Figure 5.
L5983 Sawtooth: voltage and frequency feed forward; external synchronization
Figure 6.
Oscillator frequency versus FSW pin resistor
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Functional description
L5983
4.2
Soft-start
The soft-start is essential to assure correct and safe start up of the step-down converter. It avoids inrush current surge and makes the output voltage increases monothonically. The soft-start is performed by a staircase ramp on the non-inverting input (VREF) of the error amplifier. So the output voltage slew rate is: Equation 1
S R O U T = S R V R E F 1 + R--- ----1 R 2
where SRVREF is the slew rate of the non-inverting input while R1 and R2 the resistor divider to regulate the output voltage (see Figure 7). The soft-start stair case consists of 64 steps of 9.5 mV each one, from 0 V to 0.6 V. The time base of one step is of 32 clock cycles. So the soft-start time and then the output voltage slew rate depend on the switching frequency. Figure 7. Soft-start scheme
Soft-star t time results: Equation 2
32 64 S S T I M E = ----------------Fsw
For example with a switching frequency of 250 kHz the SSTIME is 8 ms.
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Functional description
L5983
4.3
Error amplifier and compensation
The error amplifier (E/A) provides the error signal to be compared with the sawtooth to perform the pulse width modulation. Its non-inverting input is internally connected to a 0.6 V voltage reference, while its inverting input (FB) and output (COMP) are externally available for feedback and frequency compensation. In this device the error amplifier is a voltage mode operational amplifier so with high DC gain and low output impedance. The uncompensated error amplifier characteristics are the following: Table 5. Uncompensated error amplifier characteristics
Error amplifier Low frequency gain GBWP Slew rate Output voltage swing Maximum source/sink current Value 100 dB 4.5 MHz 7 V/s 0 to 3.3 V 25 mA/40 mA
In continuos conduction mode (CCM), the transfer function of the power section has two poles due to the LC filter and one zero due to the ESR of the output capacitor. Different kinds of compensation networks can be used depending on the ESR value of the output capacitor. In case the zero introduced by the output capacitor helps to compensate the double pole of the LC filter a type II compensation network can be used. Otherwise, a type III compensation network has to be used (see Chapter 5.4 for details about the compensation network selection). Anyway the methodology to compensate the loop is to introduce zeros to obtain a safe phase margin.
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Functional description
L5983
4.4
Over-current protection
The L5983 implements the over current protection sensing current flowing through the power MOSFET. Due to the noise created by the switching activity of the power MOSFET, the current sensing is disabled during the initial phase of the conduction time. This avoids an erroneous detection of a fault condition. This interval is generally known as "masking time" or "blanking time". The masking time is about 200 ns. When the over current is detected, two different behaviors are possible depending on the operating condition. 1. Output voltage in regulation. When the over current is sensed, the power MOSFET is switched off and the internal reference (VREF), that biases the non-inverting input of the error amplifier, is set to zero and kept in this condition for a soft-start time (TSS, 2048 clock cycles). After this time, a new soft-start phase takes place and the internal reference begins ramping (see Figure 8.a). Soft-start phase. If the over current limit is reached the power MOSFET is turned off implementing the pulse by pulse over current protection. During the soft-start phase, under over current condition, the device can skip pulses in order to keep the output current constant and equal to the current limit. If at the end of the "masking time" the current is higher than the over current threshold, the power MOSFET is turned off and it will skip one pulse. If, at the next switching on at the end of the "masking time" the current is still higher than the threshold, the device will skip two pulses. This mechanism is repeated and the device can skip up to seven pulses. While, if at the end of the "masking time" the current is lower than the over current threshold, the number of skipped cycles is decreased of one unit. At the end of soft-start phase the output voltage is in regulation and if the over current persists the behavior explained above takes place. (see Figure 8.b)
2.
So the over current protection can be summarized as an "hiccup" intervention when the output is in regulation and a constant current during the soft-start phase. If the output is shorted to ground when the output voltage is on regulation, the over current is triggered and the device starts cycling with a period of 2048 clock cycles between "hiccup" (power MOSFET off and no current to the load) and "constant current" with very short ontime and with reduced switching frequency (up to one eighth of normal switching frequency). See figure 32 for short circuit behavior.
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Functional description Figure 8. Over current protection strategy
L5983
4.5
Inhibit function
The inhibit feature allows to put in stand-by mode the device. With INH pin higher than 1.9 V the device is disabled and the power consumption is reduced to less than 30 A. With INH pin lower than 0.6 V, the device is enabled. If the INH pin is left floating, an internal pull up ensures that the voltage at the pin reaches the inhibit threshold and the device is disabled. The pin is also VCC compatible.
4.6
Hysteretic thermal shutdown
The thermal shutdown block generates a signal that turns off the power stage if the junction temperature goes above 150 oC. Once the junction temperature goes back to about 130 oC, the device restarts in normal operation. The sensing element is very close to the PDMOS area, so ensuring an accurate and fast temperature detection.
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Application information
L5983
5
5.1
Application information
Input capacitor selection
The capacitor connected to the input has to be capable to support the maximum input operating voltage and the maximum RMS input current required by the device. The input capacitor is subject to a pulsed current, the RMS value of which is dissipated over its ESR, affecting the overall system efficiency. So the input capacitor must have a RMS current rating higher than the maximum RMS input current and an ESR value compliant with the expected efficiency. The maximum RMS input current flowing through the capacitor can be calculated as: Equation 3
D --- --I R M S = I O D 2-----D--- + -----2
2 2
Where Io is the maximum DC output current, D is the duty cycle, is the efficiency. Considering = 1, this function has a maximum at D = 0.5 and it is equal to Io/2. In a specific application the range of possible duty cycles has to be considered in order to find out the maximum RMS input current. The maximum and minimum duty cycles can be calculated as: Equation 4
VO U T + VF D M A X = -----------------------------------VI N M I N VS W
and Equation 5
VO U T + VF D M I N = ------------------------------------VI N M A X VS W
Where VF is the forward voltage on the freewheeling diode and VSW is voltage drop across the internal PDMOS. In Table 6 some multi layer ceramic capacitors suitable for this device are reported Table 6. Input capacitors
Series GRM31 MURATA GRM55 TDK C3225 10 10 25 25 Cap value (F) 10 Rated voltage (V) 25
Manufacture
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Application information
L5983
5.2
Inductor selection
The inductance value fixes the current ripple flowing through the output capacitor. So the minimum inductance value in order to have the expected current ripple has to be selected. The rule to fix the current ripple value is to have a ripple at 20 %-40 % of the output current. The inductance value can be calculated by the following equation: Equation 6
VI N VO U T VO U T I L = ----------------------------- T O N = -------------- T O F F L L
Where TON is the conduction time of the internal high side switch and TOFF is the conduction time of the external diode (in CCM, FSW = 1 / (TON + TOFF)) the maximum current ripple, at fixed Vout, is obtained at maximum TOFF that is at minimum duty cycle (see previous section to calculate minimum duty). So fixing IL = 20 % to 40 % of the maximum output current, the minimum inductance value can be calculated: Equation 7
VO U T + VF 1 DM I N L M I N = --------------------------- --------------------- IM A X FS W
where FSW is the switching frequency, 1/(TON + TOFF). For example for VOUT = 3.3 V, VIN = 12 V, IO = 1.5 A and FSW = 250 kHz the minimum inductance value to have IL = 30 % of IO is about 21 H. The peak current through the inductor is given by: Equation 8
I I L, P K = I O + ------L 2
So if the inductor value decreases, the peak current (that has to be lower than the current limit of the device) increases. The higher is the inductor value, the higher is the average output current that can be delivered, without reaching the current limit. In the table below some inductor part numbers are listed. Table 7. Inductors
Series PD MSS1038 Coilcraft MSS7341 CD1 Coiltronics UP2.8B BI SUMIDA CDRH8D28/HP 15 to 22 2.5 to 2.8 HM76-3 CDRH8D28 4.7 to 10 15 to 33 4.7 to 10 2.7 to 3.9 2.5 to 3.7 2.5 to 3.4 3.3 to 6.2 15 to 22 2.5 to 3.5 2.9 to 3.6 Inductor value (H) 3.3 to 6.8 15 to 18 Saturation current (A) 2.75 to 4.2 3.2 to 3.6
Manufacturer Wur th
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Application information
L5983
5.3
Output capacitor selection
The current in the capacitor has a triangular waveform which generates a voltage ripple across it. This ripple is due to the capacitive component (charge and discharge of the output capacitor) and the resistive component (due to the voltage drop across its ESR). So the output capacitor has to be selected in order to have a voltage ripple compliant with the application requirements. The amount of the voltage ripple can be calculated starting from the current ripple obtained by the inductor selection. Equation 9
IM A - V O U T = E S R I M A X + ------------------------X---------8 CO U T fS W
Usually the resistive component of the ripple is much higher than the capacitive one, if the output capacitor adopted is not a multi layer ceramic capacitor (MLCC) with very low ESR value. The output capacitor is important also for loop stability: it fixes the double LC filter pole and the zero due to its ESR. In Chapter 5.4, it will be illustrated how to consider its effect in the system stability. For example with VOUT = 3.3 V, VIN = 12 V, IL = 0.5 A (resulting by the inductor value), in order to have a VOUT = 0.01·VOUT, if the multi layer capacitor are adopted, 10 F are needed and the ESR effect on the output voltage ripple can be neglected. In case of not negligible ESR (electrolytic or tantalum capacitors), the capacitor is chosen taking into account its ESR value. So in case of 100 F with ESR = 40 m, the resistive component of the drop dominates and the voltage ripple is 20 mV. The output capacitor is also important to sustain the output voltage when a load transient with high slew rate is required by the load. When the load transient slew rate exceeds the system bandwidth the output capacitor provides the current to the load. So if the high slew rate load transient is required by the application the output capacitor and system bandwidth have to be chosen in order to sustain the load transient. In the table below some capacitor series are listed. Table 8. Output capacitors
Series GRM32 MURATA GRM31 ECJ PANASONIC EEFCD SANYO TDK TPA/B/C C3225 10 to 68 100 to 470 22 to 100 6.3 4 to 16 6.3 15 to 55 40 to 80 <5 10 to 47 10 to 22 6.3 to 25 6.3 <5 <5 Cap value (F) 22 to 100 Rated voltage (V) 6.3 to 25 ESR (m) <5
Manufacturer
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Application information
L5983
5.4
Compensation network
The compensation network has to assure stability and good dynamic performance. The loop of the L5983 is based on the voltage mode control. The error amplifier is a voltage operational amplifier with high bandwidth. So selecting the compensation network the E/A will be considered as ideal, that is, its bandwidth is much larger than the system one. The transfer functions of PWM modulator and the output LC filter are studied (Figure 9 on page 18). The transfer function of the PWM modulator, from the Error Amplifier output (COMP pin) to the OUT pin, results: Equation 10
VI G P W 0 = ------N -Vs
where VS is the sawtooth amplitude. As seen in Chapter 4.1, the voltage feed forward generates a sawtooth amplitude directly proportional to the input voltage, that is: Equation 11
VS = K VI N
In this way the PWM modulator gain results constant and equals to: Equation 12
VI 1 -G P W 0 = ------N = --- = 9 Vs K
The synchronization of the device with an external clock provided trough SYNCH pin can modifies the PWM modulator gain (see Chapter 4.1 to understand how this gain changes and how to keep it constant in spite of the external synchronization) The transfer function on the LC filter is given by: Equation 13
s 1 + ------------------------2 fz E S R G L C ( s ) = -----------------------------------------------------------------------2 s 1 + -------------s------------- + ------------------ - 2 f L C 2 Q f
LC
where: Equation 14
1 f L C = ----------------------------------------------------------------------- , ESR 2 L C O U T 1 + -------------RO U T 1 f z E S R = ------------------------------------------2 E S R CO U T
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Application information Equation 15
RO U T L CO U T ( RO U T + E S R ) Q = ----------------------------------------------------------------------------------------- , L + CO U T RO U T E S R VO U R O U T = ------------T -IO U T
L5983
As seen in Chapter 4.3 two different kind of network can compensate the loop. In the two following paragraph the guidelines to select the Type II and Type III compensation network are illustrated. Figure 9. Error amplifier, PWM modulator and LC output filter
VCC VS VREF FB E/ A COMP PWM OUT L ESR GPW0 GLC COUT
5.4.1
Type III compensation network
The methodology to stabilize the loop consists of placing two zeros to compensate the effect of the LC double pole, so increasing phase margin; then to place one pole in the origin to minimize the dc error on regulated output voltage; finally to place other poles far away the zero dB frequency. If the equivalent series resistance (ESR) of the output capacitor introduces a zero with a frequency higher than the desired bandwidth (that is: 2 * ESR * COUT < 1 /BW), the type III compensation network is needed. Multi Layer Ceramic capacitors (MLCC) have very low ESR (<1 m), with very high frequency zero, so type III network is adopted to compensate the loop. In Figure 10 the type III compensation network is shown. This network introduces two zeros (fZ1, fZ2) and three poles (fP0, fP1, fP2). They expression are: Equation 16
1 f Z 1 = ----------------------------------------------- , 2 C3 ( R1 + R3 ) 1 f Z 2 = ----------------------------2 R4 C4
Equation 17
f P 0 = 0, 1 f P 1 = ----------------------------- , 2 R3 C3 1 f P 2 = ------------------------------------------C4 C5 2 R 4 ------------------C4 + C5
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Application information Figure 10. Type III compensation network
L5983
In Figure 11 the Bode diagram of the PWM and LC filter transfer function (GPW0 · GLC(f)) and the open loop gain (GLOOP(f)=GPW0 · GLC(f) · GTYPEIII(f)) are drawn. Figure 11. Open loop gain: module bode diagram
The guidelines for positioning the poles and the zeroes and for calculating the component values can be summarized as follow: 1. 2. Choose a value for R1, usually between 1 k and 5 k. Choose a gain (R4/R1) in order to have the required bandwidth (BW), that means:
Equation 18
BW 1 R 4 = --------- --- R 1 fL C K
where K is the feed forward constant and 1/K is equals to 9. 3. Calculate C4 by placing the zero at 50 % of the output filter double pole frequency (fLC):
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Application information Equation 19
1 C 4 = ------------------------- R4 fL C
L5983
4.
Calculate C5 by placing the second pole at four times the system bandwidth (BW):
Equation 20
C C 5 = --------------------------------4---------------------------2 R4 C4 4 B W 1
5.
Set also the first pole at four times the system bandwidth and also the second zero at the output filter double pole:
Equation 21
R1 R 3 = -------------------------- , 4----B------ 1 --- - --- W fL C 1 C 3 = ---------------------------------------2 R3 4 B W
The suggested maximum system bandwidth is equals to the switching frequency divided by 3.5 (FSW/3.5), anyway lower than 100 kHz if the FSW is set higher than 500 kHz. For example with VOUT = 3.3 V, VIN = 12 V, IO = 1.5 A, L = 22 H, COUT = 22 F, ESR < 1 m, the type III compensation network is:
R 1 = 4.99 k ,
R 2 = 1.1 k , R 3 = 120 , R 4 = 4.99 k ,
C 3 = 4.7 n F,
C 4 = 10 n F,
C 5 = 68 p F
In Figure 12 is shown the module and phase of the open loop gain. The bandwidth is about 77 kHz and the phase margin is 47.
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Application information Figure 12. Open loop gain bode diagram with ceramic output capacitor
L5983
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Application information
L5983
5.4.2
Type II compensation network
If the equivalent series resistance (ESR) of the output capacitor introduces a zero with a frequency lower than the desired bandwidth (that is: 2 * ESR * COUT > 1/BW), this zero helps stabilize the loop. Electrolytic capacitors show not negligible ESR (>30 m), so with this kind of output capacitor the type II network combined with the zero of the ESR allows stabilizing the loop. In Figure 13 the type II network is shown. Figure 13. Type II compensation network
The singularities of the network are:
1 f Z 1 = ----------------------------- , 2 R4 C4
f P 0 = 0,
1 f P 1 = ------------------------------------------C4 C5 2 R 4 ------------------C4 + C5
In Figure 14 the Bode diagram of the PWM and LC filter transfer function (GPW0 · GLC(f)) and the open loop gain (GLOOP(f)=GPW0 · GLC(f) · GTYPEII(f)) are drawn.
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Application information Figure 14. Open loop gain: module bode diagram
L5983
The guidelines for positioning the poles and the zeroes and for calculating the component values can be summarized as follow: 1. 2. Choose a value for R1, usually between 1 k and 5 k, in order to have values of C4 and C5 not comparable with parasitic capacitance of the board. Choose a gain (R4/R1) in order to have the required bandwidth (BW), that means:
Equation 22
fE S R 2 B W VS R 4 = ----------- ----------- -------- R 1 fL C fE S R VI N
Where fESR is the ESR zero: Equation 23
1 f E S R = ------------------------------------------2 E S R CO U T
and Vs is the saw-tooth amplitude. The voltage feed forward keeps the ratio Vs/Vin constant. 3. Calculate C4 by placing the zero one decade below the output filter double pole:
Equation 24
10 C 4 = -----------------------------2 R4 fL C
4.
Then calculate C3 in order to place the second pole at four times the system bandwidth (BW):
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Application information Equation 25
C -C 5 = --------------------------------4--------------------------2 R4 C4 4 B W 1
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For example with VOUT = 3.3 V, VIN = 12 V, IO = 1.5 A, L = 22 H, COUT = 330 F, ESR = 50 m, the type II compensation network is:
R 1 = 1.1 k ,
R 2 = 249 ,
R 4 = 10 k ,
C 4 = 6.8 n F,
C 5 = 68 p F
In Figure 15 is shown the module and phase of the open loop gain. The bandwidth is about 30 kHz and the phase margin is 45.
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Application information
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Figure 15. Open loop gain bode diagram with electrolytic/tantalum output capacitor
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Application information
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5.5
Thermal considerations
The thermal design is important to prevent the thermal shutdown of device if junction temperature goes above 150 C. The three different sources of losses within the device are: a) conduction losses due to the not negligible RDS(on) of the power switch; these are equal to:
Equation 26
PO N = RD S ( o n ) ( IO U T ) D
2
Where D is the duty cycle of the application and the maximum RDS(on) is 220 m. Note that the duty cycle is theoretically given by the ratio between VOUT an VIN, but actually it is quite higher to compensate the losses of the regulator. So the conduction losses increases compared with the ideal case. b) switching losses due to power MOSFET turn ON and OFF; these can be calculated as:
Equation 27
( TR I S E + TF A L L ) P S W = V I N I O U T ------------------------------------------ F s w = V I N I O U T T S W F S W 2
Where TRISE and TFALL are the overlap times of the voltage across the power switch (VDS) and the current flowing into it during turn ON and turn OFF phases, as shown in Figure 16. TSW is the equivalent switching time. For this device the typical value for the equivalent switching time is 50ns. c) Quiescent current losses, calculated as:
Equation 28
PQ = VI N IQ
where IQ is the quiescent current. (IQ = 2.4 mA) The junction temperature TJ can be calculated as: Equation 29
TJ = TA + R t hJ A PT O T
Where TA is the ambient temperature and PTOT is the sum of the power losses just seen. RthJA is the equivalent thermal resistance junction to ambient of the device; it can be calculated as the parallel of many paths of heat conduction from the junction to the ambient.
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Application information
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For this device the path through the exposed pad is the one conducting the largest amount of heat. The RthJA measured on the demonstration board described in the following paragraph is about 60 /W. Figure 16. Switching losses
5.6
Layout considerations
The PC board layout of switching DC/DC regulator is very important to minimize the noise injected in high impedance nodes and interferences generated by the high switching current loops. In a step down converter the input loop (including the input capacitor, the power MOSFET and the free wheeling diode) is the most critical one. This is due to the fact that the high value pulsed current are flowing through it. In order to minimize the EMI, this loop has to be as short as possible. To filter the high frequency noise, a small capacitor can be added as close as possible to the input voltage pin of the device. The feedback pin (FB) connection to external resistor divider is a high impedance node, so the interferences can be minimized placing the routing of feedback node as far as possible from the high current paths. To reduce the pick up noise the resistor divider has to be placed very close to the device. Thanks to the exposed pad of the device, the ground plane helps to reduce the thermal resistance junction to ambient; so a large ground plane enhances the thermal performance of the converter allowing high power conversion. In Figure 17 a layout example is shown.
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Application information Figure 17. Layout example
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Application information
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5.7
Application circuit
In Figure 18 the demonstration board application circuit is shown. Figure 18. Demonstration board application circuit
VIN=3.3V to 18V
VCC
OUT
L1 6.8uH D1 STPS2L25U
Vout=3.3V
8
INH GND
1 2
SYNCH
3
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7 5 6
FSW COMP FB
C2 22uF
C1 10uF
C6 68nF
R1 4.99K
4 C4 10nF R4 2.49K R3 330 R2 1.1K C5 220pF C3 2.2nF
R5 100K
Table 9.
Component list
Part number GRM31CR61E106KA12 GRM31CR61C226KE15B Description 10 F, 25 V 22 f, 16 V 2.2 nF, 50 V 10 nF, 50 V 220 pF, 50 V 68 nF, 25 V 4.99 k, 1 %, 0.1 W 0603 1.1 k, 1 %, 0.1 W 0603 330 , 1 %, 0.1 W 0603 2.99 k, 1 %, 0.1 W 0603 100 k, 1 %, 0.1 W 0603 7447779006 STPS2L25V 6.8 uH, 30 %, 2.91 A 2 A, 2 5V Coilcraft STMicroelectronics Manufacturer Murata Murata
Reference C1 C2 C3 C4 C5 C6 R1 R2 R3 R4 R5 L1 D1
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Application information Figure 19. PCB layout (component side)
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Figure 20. PCB layout (bottom side)
Figure 21. PCB layout (front side)
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Application information
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Figure 22. Junction temperature vs output current
Figure 23. Junction temperature vs output current
Figure 24. Junction temperature vs output current
Figure 25. Efficiency vs output current
95
Vo=5V
90
Efficiency [%]
Vo=3.3V
85
Vo=2.5V
80
75
VCC=12V, FSW =250kHz
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
70
Io [A]
Figure 26. Efficiency vs output current
94 92 90
Figure 27. Efficiency vs output current
Vo=3.3V
95
E f f i c ie n c y [% ]
88 86 84 82 80 78 76 0 0.2 0.4 0.6 0.8 1 1.2
Vo=2.5V
90
Vo=2.5V
E f f ic i e n c y [% ]
85
Vo=1.8V
Vo=1.8V VCC=5V, FSW=250kHz
1.4 1.6 1.8
80
Vo=1.2V VCC=3.3V, FSW=250kHz
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
75
Io [A]
70
Io [A]
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Application information Figure 28. Load regulation
0. 4 0. 35 0. 3
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0 .4
V CC=5V
0.3 5 0 .3
VFB/VFB [%]
V F B / V F B [% ]
0. 25 0. 2 0. 15 0. 1 0. 05 0 0. 2 0. 4 0. 6 0. 8 1 1. 2
V CC=12V V CC=18V
0.2 5 0 .2 0.1 5 0 .1 0.0 5
Io=1A
2 4 6 8 10 12 14 16 18
1. 4
0 - 0. 0 5
IO [A]
VCC [V]
Figure 30. Load transient: from 300 mA to 1.3 A
Figure 31. Soft-start
VOUT AC coupled 100mV/div COUT=47uF L=6.8uH FSW=500kHz
VOUT 0.5V/div
IL 0.5A/div
IL 0.5A/div VFB 200mV/div
Load slew rate = 2.5A/us
Timescale 100us/div
Time base = 1 ms/div
Figure 32. Short circuit behavior
OUT 10V/div
IL 5 00mA/div VOU T 1V/div OUTPU T SHORTED Time base 5ms/div
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Package mechanical data
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6
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a lead-free second level interconnect. The category of the second level interconnect is marked on the package and on the inner box label, in compliance with the JEDEC Standard JESD97. The maximum ratings related to soldering condition are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com
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Package mechanical data
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Table 10.
Dim.
VFQFPN8 (3 x 3 x 1.08 mm) mechanical data
mm Min Typ 0.90 Max 1.00 Min 0.0315 inch Typ 0.0354 Max 0.0394
A
0.80
A1 A2 A3
0.02 0.70 0.20
0.05
0.0008 0.0276 0.0079
0.0020
b D D2
0.18 2.95 2.23
0.23 3.00 2.38
0.30 3.05 2.48
0.0071 0.1161 0.0878
0.0091 0.1181 0.0937
0.0118 0.1200 0.0976
E E2 e L ddd
2.95 1.65
3.00 1.70 0.50
3.05 1.75
0.1161 0.0649
0.1181 0.0669 0.0197
0.1200 0.0689
0.35
0.40
0.45 0.08
0.0137
0.0157
0.0177 0.0031
Figure 33. Package dimensions
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Order codes
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7
Order codes
Table 11. Order codes
Package VFQFPN8 (3 x 3 x 1.08 mm) Packaging Tube Tube and reel
Order codes L5983 L5983TR
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Revision history
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8
Revision history
Table 12.
Date 21-Dec-2006 16-Oct-2007
Document revision history
Revision 1 2 Initial release Document status promoted from preliminary data to datasheet Updated: Cover page, Figure 2 on page 3, Figure 8 on page 13, Figure 5 on page 9, Figure 17 on page 28, Figure 18 on page 29, Table 8 on page 16, Table 10 on page 34 Added: Table 3 on page 4 Updated: Table 4 on page 5 and Figure 18 on page 29 Changes
27-May-2008
3
16-Sep-2008
4
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