STMPE2401
24-bit Enhanced port expander with Keypad and PWM controller Xpander logic
Features
24 GPIOs Operating voltage 1.8V Hardware key pad controller (8*12 matrix max) 3 PWM (8 bit) output for LED brightness control and blinking Interrupt output (open drain) pin Configurable hotkey feature on each GPIO Ultra-low Standby-mode current Package TFBGA - 36 pins 3.6x3.6mm, pitch 0.5mm TFBGA
Description
The STMPE2401 is a GPIO (General Purpose Input / output) port expander able to interface a Main Digital ASIC via the two-line bidirectional bus (I2C); separate GPIO Expander IC is often used in Mobile-Multimedia platforms to solve the problems of the limited amounts of GPIOs usually available on the Digital Engine. The STMPE2401 offers great flexibility as each I/Os is configurable as input, output or specific functions; it's able to scan a keyboard, also provides PWM outputs for brightness control in backlight, rotator decoder interface and GPIO. This device has been designed very low quiescent current, and is including a wake up feature for each I/O, to optimize the power consumption of the IC. Potential application of the STMPE2401 includes portable media player, game console, mobile phone, smart phone Figure 1. Device summary
Part number STMPE2401TBR Package TFBGA36 Packaging Tape and reel
May 2007
Rev 2
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Contents
STMPE2401
Contents
1 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 2.2 2.3 2.4 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin assignment and TFBGA ball location . . . . . . . . . . . . . . . . . . . . . . . . . . 6 GPIO Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pin mapping to TFBGA ( bottom view, balls up) . . . . . . . . . . . . . . . . . . . . . 9
3
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1 3.2 Absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4
Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1 4.2 4.3 4.4 4.5 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 I/O DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 DC input specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 DC output specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5
Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
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STMPE2401
Contents
6
I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.1 6.2 6.3 6.4 6.5 6.6 6.7 Star t condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Slave device address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Memory addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7
System controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.1 7.2 7.3 Identification register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 System control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 States of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
8
Clocking system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8.1 Programming sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
9
Interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
9.1 9.2 9.3 9.4 9.5 9.6 9.7 Register map of interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Interrupt control register (ICR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Interrupt enable mask register (IER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Interrupt status register (ISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Interrupt enable GPIO mask register (IEGPIOR) . . . . . . . . . . . . . . . . . . . 25 Interrupt status GPIO register (ISGPIOR) . . . . . . . . . . . . . . . . . . . . . . . . 26 Programming sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
10
GPIO controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
10.1 10.2 10.3 GPIO control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 GPIO alternate function register (GPAFR) . . . . . . . . . . . . . . . . . . . . . . . . 30 Hot key feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10.3.1 10.3.2 Programming sequence for hot key . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Minimum pulse width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
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Contents
STMPE2401
11
PWM controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
11.1 11.2 11.3 Registers in the PWM controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 PWM control and status register (PWMCS) . . . . . . . . . . . . . . . . . . . . . . . 35 PWM instruction channel x (PWMICx) . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
12 13
PWM commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Keypad controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
13.1 13.2 13.3 13.4 13.5 13.6 13.7 Registers in keypad controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 KPC_col register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 KPC_row_msb register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 KPC_row_lsb register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 KPC_ctrl_msb register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 KPC_ctrl_lsb register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
13.7.1 13.7.2 Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Using the keypad controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
14
Rotator controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
14.1 14.2 Rotator_Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Rotator_Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
15
Miscellaneous features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
15.1 15.2 15.3 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Under voltage lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
16 17
Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
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STMPE2401
Block diagram
1
Block diagram
Figure 1. Block diagram
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Pin settings
STMPE2401
2
2.1
Pin settings
Pin connection
Figure 2. Pin connection
TFBGA
2.2
Pin assignment and TFBGA ball location
Table 1. Pin assignment
Ball C3 C2 C1 B1 A1 B2 A2 B3 A3 C4 A4 Name GND KP_X0 Reset_N KP_X1 KP_X2 KP_X3 KP_X4 KP_X5 KP_X6 GND VCC1 Type IO I IO IO IO IO IO IO 1.8V Input GPIO External reset input, active LOW GPIO GPIO GPIO GPIO GPIO GPIO Name and function
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STMPE2401 Table 1. Pin assignment
Ball B3 A5 A6 B5 B6 C5 C6 D3 D6 D5 E6 F6 E5 F5 E4 F4 D4 F3 E3 F2 F1 E2 E1 D2 D1 Name KP_X7 KP_Y5 KP_Y4 KP_Y3 KP_Y2 KP_Y1 KP_Y0 GND ADDR0 KP_Y9 KP_Y10 KP_Y11 PWM3 PWM2 PWM1 VCC2 GND INT KP_Y8 KP_Y7 KP_Y6 SDATA SCLK XTALIN XTALOUT Type IO IO IO IO IO IO IO IO A/IO A/IO A/IO A/IO A/IO A/IO O IO IO IO A A A A Open drain interrupt output pin GPIO GPIO GPIO I2C DATA I2C Clock GPIO and I2C ADDR 0 (in reset) GPIO GPIO GPIO GPIO and I2C ADDR 1 (in reset) GPIO GPIO 1.8V Input GPIO GPIO GPIO GPIO GPIO GPIO GPIO Name and function
Pin settings
XTAL Oscillator or External 32KHz input XTAL Oscillator
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Pin settings
STMPE2401
2.3
GPIO Pin functions
Table 2. GPIO Pin functions
Pin N 2 4 5 6 7 8 9 12 13 14 15 16 17 18 20 21 22 23 24 25 26 30 31 32 Name KP_X0 KP_X1 KP_X2 KP_X3 KP_X4 KP_X5 KP_X6 KP_X7 KP_Y5 KP_Y4 KP_Y3 KP_Y2 KP_Y1 KP_Y0 ADDR0 KP_Y9 KP_Y10 KP_Y11 PWM3 PWM2 PWM1 KP_Y8 KP_Y7 KP_Y6 Primary Alternate Function 1 Alternate Function 2 Alternate Function 3 Function GPIO 0 GPIO 1 GPIO 2 GPIO 3 GPIO 4 GPIO 5 GPIO 6 GPIO 7 GPIO 13 GPIO 12 GPIO 11 GPIO 10 GPIO 9 GPIO 8 GPIO 15 GPIO 18 GPIO 19 GPIO 20 GPIO 23 GPIO 22 GPIO 21 GPIO 17 GPIO 16 GPIO 14 Keypad output 9 Keypad output 10 Keypad output 11 Channel 3 Channel 2 Channel 1 Keypad output 8 Keypad output 7 Keypad output 6 ClkOut Rotator 0 Rotator 1 Rotator 2 Keypad input 0 Keypad input 1 Keypad input 2 Keypad input 3 Keypad input 4 Keypad input 5 Keypad input 6 Keypad input 7 Keypad output 5 Keypad output 4 Keypad output 3 Keypad output 2 Keypad output 1 Keypad output 0
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STMPE2401
Pin settings
2.4
Pin mapping to TFBGA ( bottom view, balls up)
Table 3. Pin mapping to TFBGA
A 1 2 3 4 5 6 KP-X2 KP-X4 KP-X6 VCC KP-Y5 KP-Y4 B KP-X1 KP-X3 KP-X5 KP-X7 KP-Y3 KP-Y2 C Reset_N KP-X0 GND GND KP-Y1 KP-Y0 D XTALOUT XTALIN GND GND KP-Y9 ADDR0 E SCLK SDATA KP-Y8 PWM-1 PWM-3 KP-Y10 F KP-Y6 KP-Y7 INT VCC PWM-2 KP-Y11
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Maximum rating
STMPE2401
3
Maximum rating
Stressing the device above the rating listed in the "Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
3.1
Absolute maximum rating
Table 4. Absolute maximum rating
Symbol VCC VIN VI2C VESD (HBM) Supply voltage Input voltage on GPIO pin Input voltage on I2C pin (SDATA,SCLK, INT) ESD protection on each GPIO pin Parameter Value 2.5 2.5 4.5 2 Unit V V V KV
3.2
Thermal data
Table 5. Thermal data
Symbol
RthJA
Parameter Thermal resistance junction-ambient Operating ambient temperature Operating junction temperature
Min
Typ 100
Max
Unit C/W
TA TJ
-40 -40
25 25
85 125
C C
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STMPE2401
Electrical specification
4
4.1
Electrical specification
DC electrical characteristics
Table 6. DC electrical characteristics
Value Symbol VCC1,2 IHIBERNATE ISLEEP Icc Parameter 1.8V supply voltage HIBERNATE mode current SLEEP mode current Operating current (FSM working No peripheral activity) Open drain output current Voltage level at INT pin Test conditions Min. 1.65 Typ. 1.8 6 15 0.5 Max. 1.95 12 50 1.0 V uA uA mA Unit
IO_INT V_INT
4 3.6
mA V
4.2
I/O DC electrical characteristics
The 1.8V I/O complies to the EIA/JEDEC standard JESD8-7. Table 7. I/O DC electrical characteristic
Value Symbol Parameter Min. Vil Vih Vhyst Low level input voltage High level input voltage Schmitt trigger hysteresis 0.65*Vcc = 1.17 0.10 Typ. Max. 0.35*Vcc = 0.63 V V V Unit
4.3
DC input specification
(1.55V < VDD < 1.95V) Table 8. DC input specification
Value Symbol Vol Voh Parameter Low level output voltage High level output voltage Test conditions Min. Iol = 4mA Ioh = 4mA Vcc - 0.45 = 1.35 Typ. Max. 0.45 V V Unit
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Electrical specification
STMPE2401
4.4
DC output specification
(1.55V < vdd < 1.95V) Table 9. DC output specification
Symbol Ipu Ipd Rup Rpd Parameter Pull-up current Pull-down current Equivalent pull-up resistance Equivalent pull-down resistance Test conditions Vi = 0V Vi = vdd Vi = 0V Vi = vdd Value Unit Min. 15 14 30 32.5 Typ. 35 35 50 50 Max. 65 60 103.3 110.7 A A K K
Note:
Pull-up and Pull-down characteristics
4.5
AC characteristics
Table 10. AC characteristics
Value Symbol FO CL Frequency Load capacitance Parameter Min. 16 Typ. Max. 32 27 kHz pF Unit
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STMPE2401
Register map
5
Register map
All registers have the size of 8-bit. Some of the registers are composed of 2-byte to form 16bit registers. For each of the module, their registers are residing within the given address range. Table 11. Register map
Address 0x00 0x07 0x80 0x81 0x10 0x1F 0x30 0x37 0x38 0x3F 0x60 0x67 0x68 0x6F 0x70 0x77 0x82 0xBF Rotator Controller Module Keypad Controller Module Module registers Clock and Power Manager module Interrupt Controller module Description Clock and Power Manager register range. Interrupt Controller register range Auto-Increment (during read/write) Yes Yes Yes No Yes No Yes Yes
PWM Controller Module PWM Controller register range PWM Controller register range Keypad Controller register range Keypad Controller register range Rotator Controller register range
GPIO Controller Module GPIO Controller register range
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I2C Interface
STMPE2401
6
I2C Interface
The features that are supported by the I2C interface are as below:
I2C Slave device SDAT and SCLK operates from 1.8V to 3.3V Compliant to Philip I2C specification version 2.1 Suppor ts Standard (up to 100kbps) and Fast (up to 400kbps) modes. 7-bit device addressing mode General Call Star t/Restar t/Stop Address up to 4 STMPE2401 devices via I2C
The address is selected by the state of two pins. The state of the pins will be read upon reset and then the pins can be configured for normal operation. The pins will have a pull-up or down to set the address. The I2C interface module allows the connected host system to access the registers in the STMPE2401.
6.1
Start condition
A Start condition is identified by a falling edge of SDATA while SCLK is stable at high state. A Start condition must precede any data/command transfer. The device continuously monitors for a Start condition and will not respond to any transaction unless one is encountered.
6.2
Stop condition
A Stop condition is identified by a rising edge of SDATA while SCLK is stable at high state. A Stop condition terminates communication between the slave device and bus master. A read command that is followed by NoAck can be followed by a Stop condition to force the slave device into idle mode. When the slave device is in idle mode, it is ready to receive the next I2C transaction. A Stop condition at the end of a write command stops the write operation to registers.
6.3
Acknowledge bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter releases the SDATA after sending eight bits of data. During the ninth bit, the receiver pulls the SDATA low to acknowledge the receipt of the eight bits of data. The receiver may leave the SDATA in high state if it would to not acknowledge the receipt of the data.
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STMPE2401
I2C Interface
6.4
Data input
The device samples the data input on SDATA on the rising edge of the SCLK. The SDATA signal must be stable during the rising edge of SCLK and the SDATA signal must change only when SCLK is driven low.
6.5
Slave device address
The slave device address is a 7 address, where the least significant 2-bit are programmable. These 2-bit values will be loaded in once upon reset and after that these 2 pins no longer be needed with the exception during General Call. Up to 4 STMPE2401 devices can be connected on a single I2C bus. Table 12. Slave device address
ADDR 1 0 0 1 1 ADDR 0 0 1 0 1 Address 0x84 0x86 0x88 0x8A
6.6
Memory addressing
For the bus master to communicate to the slave device, the bus master must initiate a Start condition and followed by the slave device address. Accompanying the slave device address, there is a Read/Write bit (R/W). The bit is set to 1 for Read and 0 for Write operation. If a match occurs on the slave device address, the corresponding device gives an acknowledgement on the SDA during the 9th bit time. If there is no match, it deselects itself from the bus by not responding to the transaction.
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I2C Interface
STMPE2401
6.7
Operation modes
Table 13. Operating modes
Mode Bytes Programming sequence START, Device Address, R/W = 0, Register Address to be read RESTART, Device Address, R/W = 1, Data Read, STOP 1 If no STOP is issued, the Data Read can be continuously preformed. If the register address falls within the range that allows address auto-increment, then register address auto-increments internally after every byte of data being read. For register address that falls within a non-incremental address range, the address will be kept static throughout the entire read operations. Refer to the Memory Map table for the address ranges that are auto and non-increment. An example of such a nonincrement address is FIFO. START, Device Address, R/W=0, Register Address to be written, Data Write, STOP If no STOP is issued, the Data Write can be continuously performed. If the register address falls within the range that allows address auto-increment, then register address auto-increments internally after every byte of data being written in. For register address that falls within a non-incremental address range, the address will be kept static throughout the entire write operations. Refer to the Memory Map table for the address ranges that are auto and non-increment. An example of a nonincrement address is Data Port for initializing the PWM commands.
Read
Write
1
Figure 3.
Master/slave operation modes
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STMPE2401 Figure 4. I2C timing
I2C Interface
Table 14. I2C address
Symbol fSCL tLOW tHIGH tF tHD:STA tSU:STA tSU:DAT tHD:DAT tSU:STO tBUF Parameter SCL clock frequency Clock low period Clock high period SDA and SCL fall time START condition hold time (After this period the first clock is generated) START condition setup time (Only relevant for a repeated start period) Data setup time Data hold time STOP condition setup time Time the bust must be free before a new trasmission can start 600 600 100 0 600 1.3 Min 0 1.3 600 300 Typ Max 400 Unit kHz s ns ns ns ns ns s ns s
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System controller
STMPE2401
7
System controller
The system controller is the heart of the STMPE2401. It contains the registers for power control, and the registers for chip identification. The system registers are: Table 15. System controller
Address 0x00 0x01 0x80 0x81 0x82 0x02 Register_Name Reserved (Reads 0x00) Reserved (Reads 0x00) CHIP_ID VERSION_ID Reserved (Reads 0x00) SYSCON
7.1
Identification register
Table 16. CHIP_ID
Bit 7 6 5 4 3 2 1 0 8-bit LSB of Chip ID Read/Write(IIC) Reset Value R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 1
Table 17. VERSION_ID
Bit 7 6 5 4 3 2 1 0 8-bit Version ID Read/Write(IIC) Reset Value R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 1
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STMPE2401
System controller
7.2
System control register
Table 18. System control register
Bit 7 Soft_Reset Read/Writ e (IIC) Read/Writ e(HW) Reset Value W RW 0 6 5 4 3 2 1 0 Disable_32KHz Sleep Enable_GPIO Enable_PWM Enable_KPC Enable_ROT RW R 0 RW RW 0 RW R 1 RW R 1 RW R 1 RW R 1
Table 19. System control register writing
Bits 0 1 2 3 4 Name Enable_ROT Enable_KPC Enable_PWM Enable_GPIO Sleep Description Writing a `0' to this bit will gate off the clock to the Rotator module, thus stopping its operation Writing a `0' to this bit will gate off the clock to the Keypad Controller module, thus stopping its operation Writing a `0' to this bit will gate off the clock to the PWM module, thus stopping its operation Writing a `0' to this bit will gate off the clock to the GPIO module, thus stopping its operation Writing a `1' to this bit will put the device in sleep mode. When in sleep mode, all the units which need to work on clocks synchronous to 32KHz will get the clocks derived from the 32K domain. The RC Oscillator will be shut off. Set this bit to disable the 32KHz OSC, thus putting the device in hibernate mode. Only a Reset or a wakeup on IIC will reset this bit Writing a `1' to this bit will do a soft reset of the device. Once the reset is done, this bit will be cleared to `0' by the HW.
5 6 7
Disable_32KHz Soft_Reset
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System controller
STMPE2401
7.3
States of operation
The device has three main modes of operation:
Operational Mode: This is the mode, whereby normal operation of the device takes place. In this mode, the RC clock is available and the Main FSM Unit routes this clock and the 32 KHz clock to all the device blocks that are enabled. In this mode, individual blocks that need not be working can be turned off by the master by programming the bits 3 to 0 of the SYSCON register. Sleep Mode: In this low-power mode, the RC Oscillator is powered down. All the blocks which need clocks derived from the 32KHz clock will continue getting a 32KHz clock. In this mode also, individual blocks can be turned off by the master by programming the bits 3 to 0 of the SYSCON register. However, the master needs to program the SYSCON register before coming into this mode, as in the sleep mode, the IIC interface is not active except to detect traffic for wakeup. Any activity on the I2C port or Wakeup pin or Hotkey activity will cause the device to leave this mode and go into the Operational mode. When leaving this mode, the I2C will need to hold the SCLK till the RC clock is ready. Hibernate Mode: This mode is entered when the system writes a `1' to bit 5 of the SYSCON register. In this mode, the device is completely inactive as there is absolutely no clock. Only a Reset or a wakeup on IIC will bring back the System to operational mode. All I2C activities are ignored.
Caution:
Hotkey detection is not possible in hibernate mode. Figure 5. State of operation
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STMPE2401
Clocking system
8
Clocking system
Figure 6. Clocking system
The decision on clocks is based on the bits written into SYSCON registers. Bits 0 to 4 of the SYSCON register control the gating of clocks to the Rotator, Keypad Controller, PWM and GPIO respectively in the operational mode. When in sleep mode, the operating clock is cut off from every functional blocks (including the I2C) except Keypad Controller and GPIO.
8.1
Programming sequence
To put the device in sleep mode, the following needs to be done by the host: 1. 2. 3. 4. 5. 6. 7. 8. 9. Write a `1' to bit 4 of the SYSCON register. To wakeup the device, the following needs to be done by the host: Assert a wakeup routine on the I2C bus by sending the Start Bit, followed by the device address and the R/W bit. If there's a NOACK, keep sending the wakeup routine till there is an ACK from the slave. To do a soft reset to the device, the host needs to do the following: Write a `1' to bit 7 of the SYSCON register. This bit is automatically cleared upon reset. To go into Hibernate mode, the following needs to be done by the host: Set the Disable_32K bit to `1'
10. To come out of the Hibernate mode, the following needs to be done by the host: 11. Assert a system reset or 12. Put a wakeup on the I2C
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STMPE2401
9
Interrupt system
STMPE2401 uses a highly flexible interrupt system. It allows host system to configure the type of system events that should result in an interrupt, and pinpoints the source of interrupt by status register. The INT pin could be configured as ACTIVE HIGH, or ACTIVE LOW. 32KHz clock input or crystal must be available for the interrupt system to be functional. INT pin is 3.3V tolernat. Once asserted, the INT pin would de-assert only if the corresponding bit in the InterruptStatus register is cleared. Figure 7. Interrupt system
9.1
Register map of interrupt system
Table 20. Register map of interrupt system
Address 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B Register Name ICR_msb Interrupt Control Register ICR_lsb IER_msb Interrupt Enable Mask Register IER_lsb ISR_msb Interrupt Status Register ISR_lsb IEGPIOR_msb IEGPIOR_mid IEGPIOR_lsb IEGPIOR_msb ISGPIOR_mid ISGPIOR_lsb Interrupt Status GPIO Register Interrupt Enable GPIO Mask Register Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Description Auto-Increment (during sequential R/W) Yes
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STMPE2401
Interrupt system
9.2
Interrupt control register (ICR)
ICR register is used to configure the Interrupt Controller. It has a global enable interrupt mask bit that controls the interruption to the host.
ICR_msb Bit 15 14 13 12 11 10 9 8 7 6 5 4
ICR_lsb 3 2 IC2 R 0 R 0 R 0 R 0 R 0 R 0 RW 0 1 IC1 RW 0 0 IC0 RW 0
Reser ved R/W Reset Value R 0 R 0 R 0 R 0 R 0 R 0 R 0
Table 21. ICR
Bits 0 Name IC[0] Description Global Interrupt Mask bit When this bit is written a `1', it will allow interruption to the host. If it is written with a `0', then, it disables all interruption to the host. Writing to this bit does not affect the IER value. output Interrupt Type `0' = Level interrupt `1' = Edge interrupt output Interrupt Polarity `0' = Active Low / Falling Edge `1' = Active High / Rising Edge
1
IC[1]
2
IC[2]
9.3
Interrupt enable mask register (IER)
IER register is used to enable the interruption from a particular interrupt source to the host.
IER_msb Bit 15 14 13 12 11 10 9 8 IE8 R 0 R 0 R 0 RW 0 7 I E7 RW 0 6 IE6 RW 0 5 IE5 RW 0
IER_lsb 4 IE4 RW 0 3 IE3 RW 0 2 IE2 RW 0 1 IE1 RW 0 0 IE0 RW 0
Reserved R/W Reset Value R 0 R 0 R 0 R 0
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Interrupt system
STMPE2401
Table 22. IER
Bits 8:0 Name IE[x] Description Interrupt Enable Mask (where x = 8 to 0) IE0 = Wake-up Interrupt Mask IE1 = Keypad Controller Interrupt Mask IE2 = Keypad Controller FIFO Overflow Interrupt Mask IE3 = Rotator Controller Interrupt Mask IE4 = Rotator Controller Buffer Overflow Interrupt Mask IE5 = PWM Channel 0 Interrupt Mask IE6 = PWM Channel 1 Interrupt Mask IE7 = PWM Channel 2 Interrupt Mask IE8 = GPIO Controller Interrupt Mask Writing a `1' to the IE[x] bit will enable the interruption to the host.
9.4
Interrupt status register (ISR)
ISR register monitors the status of the interruption from a particular interrupt source to the host. Regardless whether the IER bits are enabled or not, the ISR bits are still updated.
ISR_msb Bit 15 14 13 12 11 10 9 8 IS8 R 0 R 0 R 0 RW 0 7 I S7 RW 0 6 IS6 RW 0 5 IS5 RW 0
ISR_lsb 4 IS4 RW 0 3 IS3 RW 0 2 IS2 RW 0 1 IS1 RW 0 0 IS0 RW 0
Reserved R/W Reset Value R 0 R 0 R 0 R 0
Table 23. ISR
Bits 8:0 Name IS[x] Description Interrupt Status (where x = 8 to 0) Read: IS0 = Wake-up Interrupt Status IS1 = Keypad Controller Interrupt Status IS2 = Keypad Controller FIFO Overflow Interrupt Status IS3 = Rotator Controller Interrupt Status IS4 = Rotator Controller Buffer Overflow Interrupt Status IS5 = PWM Channel 0 Interrupt Status IS6 = PWM Channel 1 Interrupt Status IS7= PWM Channel 2 Interrupt Status IS8 = GPIO Controller Interrupt Status Write: A write to a IS[x] bit with a value of `1' will clear the interrupt and a write with a value of `0' has no effect on the IS[x] bit.
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STMPE2401
Interrupt system
9.5
Interrupt enable GPIO mask register (IEGPIOR)
IEGPIOR register is used to enable the interruption from a particular GPIO interrupt source to the host. The IEG[15:0] bits are the interrupt enable mask bits correspond to the GPIO[15:0] pins.
IEGPIOR_msb Bit 23 22 21 20 19 18 17 16
IEG IEG IEG IEG IEG IEG IEG IEG 23 22 21 20 19 18 17 16 R/W Reset Value RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0
IEGPIOR _lsb Bit 15 IEG 15 R/W Reset Value RW 0 14 IEG 14 RW 0 13 IEG 13 RW 0 12 IEG 12 RW 0 11 IEG 11 RW 0 10 9 8 7 6 5 4 3 2 1 0
IEG IEG IEG IEG IEG IEG IEG IEG IEG IEG IEG 10 9 8 7 6 5 4 3 2 1 0 RW RW RW RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 0 0 0
Table 24. GPIO
Bits 23:0 Name IEG[x] Description Interrupt Enable GPIO Mask (where x = 23 to 0) Writing a `1' to the IE[x] bit will enable the interruption to the host.
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Interrupt system
STMPE2401
9.6
Interrupt status GPIO register (ISGPIOR)
ISGPIOR register monitors the status of the interruption from a particular GPIO pin interrupt source to the host. Regardless whether the IEGPIOR bits are enabled or not, the ISGPIOR bits are still updated. The ISG[15:0] bits are the interrupt status bits correspond to the GPIO[15:0] pins.
ISGPIOR _lsb Bit 23 22 21 20 19 18 17 16
IEG IEG IEG IEG IEG IEG IEG IEG 23 22 21 20 19 18 17 16 R/W Reset Value RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0
ISGPIOR_msb Bit 15 ISG 15 R/W Reset Value RW 0 14 ISG 14 RW 0 13 ISG 13 RW 0 12 ISG 12 RW 0 11 ISG 11 RW 0 10 9 8 7 6 5
ISGPIOR _lsb 4 3 2 1 0
ISG ISG ISG ISG ISG ISG ISG ISG ISG ISG ISG 10 9 8 7 6 5 4 3 2 1 0 RW RW RW RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 0 0 0
Table 25. GPIO
Bits 23:0 Name Description ISG[x] Interrupt Status GPIO (where x = 23 to 0) Read: Interrupt Status of the GPIO[x]. Write: A write to a ISG[x] bit with a value of `1' will clear the interrupt and a write with a value of `0' has no effect on the ISG[x] bit.
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STMPE2401
Interrupt system
9.7
Programming sequence
To configure and initialize the Interrupt Controller to allow interruption to host, observe the following steps:
Set the IER and IEGPIOR registers to the desired values to enable the interrupt sources that are to be expected to receive from. Configure the output interrupt type and polarity and enable the global interrupt mask by writing to the ICR. Wait for interrupt. Upon receiving an interrupt, the INT pin is asserted. The host comes to read the ISR through I2C interface. A `1' in the ISR bits indicates that the corresponding interrupt source is triggered. If the IS8 bit in ISR is set, the interrupt is coming from the GPIO Controller. Then, a subsequent read is performed on the ISGPIOR to obtain the interrupt status of all 16 GPIOs to locate the GPIO that triggers the interrupt. This is a feature so-called `Hot Key'. After obtaining the interrupt source that triggers the interrupt, the host performs the necessary processing and operations related to the interrupt source. If the interrupt source is from the GPIO Controller, two write operations with value of `1' are performed to the ISG[x] bit (ISGPIOR) and the IS[8] (ISR) to clear the corresponding GPIO interrupt. If the interrupt source is from other module, a write operation with value of `1' is performed to the IS[x] (ISR) to clear the corresponding interrupt. Once the interrupt is being cleared, the INT pin will also be de-asserted if the interrupt type is level interrupt. An edge interrupt will only assert a pulse width of 250ns. When the interrupt is no longer required, the IC0 bit in ICR may be set to `0' to disable the global interrupt mask bit.
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GPIO controller
STMPE2401
10
GPIO controller
A total of 24 GPIOs are available in the STMPE2401 port expander IC. Most of the GPIOs are sharing physical pins with some alternate functions. The GPIO controller contains the registers that allow the host system to configure each of the pins into either a GPIO, or one of the alternate functions. Unused GPIOs should be configured as outputs to minimize the power consumption. Table 26. GPIO controller
Address 0xA2 0xA3 0xA4 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A Register name GPMR_msb GPMR_csb GPMR_lsb GPSR_msb GPSR_csb GPSR_lsb GPCR_msb GPCR_csb GPCR_lsb GPDR_msb GPDR_csb GPDR_lsb GPEDR_msb GPEDR_csb GPEDR_lsb GPRER_msb GPRER_csb GPRER_lsb GPFER_msb GPFER_csb GPFER_lsb GPPUR_msb GPPUR_csb GPPUR_lsb GPPDR_msb GPPDR_csb GPPDR_lsb GPIO Pull Down Register GPIO Pull Up Register GPIO Falling Edge Register GPIO Rising Edge Register GPIO Edge Detect Status Register GPIO Set Pin Direction Register GPIO Clear Pin State Register GPIO Set Pin State Register GPIO Monitor Pin State Register Description Auto-Increment (during sequential R/W) Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
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STMPE2401 Table 26. GPIO controller
Address 0x9B 0x9C 0x9D 0x9E 0x9F 0xA0 Register name GPAFR_U_msb GPAFR_U_csb GPAFR_U_lsb GPAFR_L_msb GPAFR_L_csb GPAFR_L_lsb Reserved GPIO Alternate Function Register (Lower Bit) GPIO Alternate Function Register (Upper Bit) Description
GPIO controller
Auto-Increment (during sequential R/W) Yes Yes Yes Yes Yes Yes Yes
0xA5 0xAF RESERVED
10.1
GPIO control registers
A group of registers are used to control the exact function of each of the 24 GPIO. All GPIO registers are named as GPxxx_yyy, where
Xxx represents the functional group
Yyy represents the byte position of the GPIO Lsb registers controls GPIO[7:0] Csb registers controls GPIO[15:8] Msb registers controls GPIO[23:16] Table 27. Register
Bit GPxxx_msb GPxxx_csb GPxxx_lsb 7 IO-23 IO-15 IO-7 6 IO-22 IO-14 IO-6 5 IO-21 IO-13 IO-5 4 IO-20 IO-12 IO-4 3 IO-19 IO-11 IO-3 2 IO-18 IO-10 IO-2 1 IO-17 IO-9 IO-1 0 IO-16 IO-8 IO-0
Note:
This convention does not apply to the GPIO Alternate Function Registers The function of each bit is shown in the following table: Table 28. Bit's function
Register name GPIO Monitor Pin State GPIO Set Pin State GPIO Clear Pin State GPIO Set Pin Direction Function Reading this bit yields the current state of the bit. Writing has no effect. Writing `1' to this bit causes the corresponding GPIO to go to `1' state. Writing `0' has no effect. Writing `1' to this bit causes the corresponding GPIO to go to `0' state. Writing `0' has no effect. `0' sets the corresponding GPIO to input state, and `1' sets it to output state 29/55
GPIO controller Table 28. Bit's function
Register name GPIO Edge Detect Status GPIO Rising Edge GPIO Falling Edge GPIO Pull Up GPIO Pull Down Function
STMPE2401
Set to `1' by hardware when there is a rising/falling edge on the corresponding GPIO. Writing `1' clears the bit. Writing `0' has no effect. Set to `1' to enable rising edge detection on the corresponding GPIO. Set to `1' to enable falling edge detection on the corresponding GPIO. Set to `1' to enable internal pull-up resistor Set to `1' to enable internal pull-down resistor
10.2
GPIO alternate function register (GPAFR)
GPAFR is to select the functionality of the GPIO pin. To select a function for a GPIO pin, a bit-pair in the register (GPAFR_U or GPAFR_L) has to be set.
GPAFR_U_msb Bit 23 AF23 R/W Reset Value RW 0 RW 0 RW 0 22 21 AF22 RW 0 RW 0 20 19 AF21 RW 0 RW 0 18 17 AF20 RW 0 16
GPAFR_U_csb Bit 15 AF19 R/W Reset Value RW 0 RW 0 RW 0 14 13 AF18 RW 0 RW 0 12 11 AF17 RW 0 RW 0 10 9 AF16 RW 0 8
GPAFR_U_lsb Bit 7 AF15 R/W Reset Value RW 0 RW 0 RW 0 6 5 AF14 RW 0 RW 0 4 3 AF13 RW 0 RW 0 2 1 AF12 RW 0 0
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STMPE2401
GPIO controller
Table 29. Bit description
Bits 23:0 Name AF[x] Description GPIO Pin `x' Alternate Function Select (where x = 23 to 12). `00' The corresponding GPIO pin (GPIO[x]) is configured to Primary Function. `01' The corresponding GPIO pin (GPIO[x]) is configured to Alternate Function 1. `10' The corresponding GPIO pin (GPIO[x]) is configured to Alternate Function 2. `11' The corresponding GPIO pin (GPIO[x]) is configured to Alternate Function 3.
GPAFR_L_msb Bit 23 AF11 R/W Reset Value RW 0 RW 0 RW 0 22 21 AF10 RW 0 RW 0 20 19 AF9 RW 0 RW 0 18 17 AF8 RW 0 16
GPAFR_L_csb Bit 15 AF7 R/W Reset Value RW 0 RW 0 RW 0 14 13 AF6 RW 0 RW 0 12 11 AF5 RW 0 RW 0 10 9 AF4 RW 0 8
GPAFR_L_lsb Bit 7 AF3 R/W Reset Value RW 0 RW 0 RW 0 6 5 AF2 RW 0 RW 0 4 3 AF1 RW 0 RW 0 2 1 AF0 RW 0 0
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GPIO controller
STMPE2401
Table 30. Bit description
Bits 23:0 Name AF[x] Description GPIO Pin `x' Alternate Function Select (where x = 11 to 0). `00' The corresponding GPIO pin (GPIO[x]) is configured to Primary Function. `01' The corresponding GPIO pin (GPIO[x]) is configured to Alternate Function 1. `10' The corresponding GPIO pin (GPIO[x]) is configured to Alternate Function 2. `11' The corresponding GPIO pin (GPIO[x]) is configured to Alternate Function 3.
10.3
Hot key feature
A GPIO is known as `Hot Key' when it is configured to trigger an interruption to the host whenever the GPIO input is being asserted. This feature is applicable in Operational mode (RC clock is present) as well as Sleep mode (32kHz clock is present).
10.3.1
Programming sequence for hot key
1. 2. 3. 4. 5. 6. Configures the GPIO pin into GPIO mode by setting the corresponding bits in the GPAFR. Configures the GPIO pin into input direction by setting the corresponding bit in GPDR. Set the GPRER and GPFER to the desired values to enable the rising edge or falling edge detection. Configures and enables the interrupt controller to allow the interruption to the host. Now, the GPIO Expander may be put into Sleep mode if it is desired. Upon any Hot Key being asserted, the device will wake-up and issue an interrupt to the host. The pin is configured into GPIO mode and as input pin. The global interrupt mask bit is enabled. The corresponding GPIO interrupt mask bit is enabled.
Below are the conditions to be fulfilled in order to configure a Hot Key: 1. 2. 3.
10.3.2
Minimum pulse width
The minimum pulse width of the assertion of the Hot Key must be at least 62.5us. Any pulse width less than the stated value may not be registered.
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STMPE2401
PWM controller
11
PWM controller
The STMPE2401 PWM controller provides 3 independent PWM outputs used to generate light effect; if the PWM outputs are not used, these pins can be used as GPIO. Figure 8. PWM controller
Instructions are downloaded into the memory via the I2C connection.
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PWM controller
STMPE2401
11.1
Registers in the PWM controller
The main system registers are: Table 31. Main system registers
Address 0x30 Register Name PWMCS Description PWM Control and Status register PWM instructions are initialized through this data port. Every instruction is 16-bit width and therefore, the MSB of the first word is written first, then, followed by LSB of the first word. Subsequently, MSB of second word and LSB of second word and so on. PWM instructions are initialized through this data port. Every instruction is 16-bit width and therefore, the MSB of the first word is written first, then, followed by LSB of the first word. Subsequently, MSB of second word and LSB of second word and so on. PWM instructions are initialized through this data port. Every instruction is 16-bit width and therefore, the MSB of the first word is written first, then, followed by LSB of the first word. Subsequently, MSB of second word and LSB of second word and so on. Auto-Increment (during Read/Write) Yes
0x38
PWMIC0
No
0x39
PWMIC1
No
0x3A
PWMIC2
No
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PWM controller
11.2
PWM control and status register (PWMCS)
Bit
7 Reser ved
6
5 II2
4 II1 R 0
3 II0 R 0
2 EN2 RW 0
1 EN1 RW 0
0 EN0 RW 0
Read/Write Reset Value
R 0
R 0
R 0
Table 32. Bit description
Bits 0 Name EN0 Description PWM Channel 0 Enable bit. `1' Enable the PWM Channel 0 `0' Reset the PWM Channel 0. Only when the PWM channel is in reset state, the stream of commands can be written into its data port, which in this case is PWM_Command_Channel_0. PWM Channel 1 Enable bit. `1' Enable the PWM Channel 1 `0' Reset the PWM Channel 1. Only when the PWM channel is in reset state, the stream of commands can be written into its data port, which in this case is PWM_Command_Channel_1. PWM Channel 2 Enable bit. `1' Enable the PWM Channel 2 `0' Reset the PWM Channel 2. Only when the PWM channel is in reset state, the stream of commands can be written into its data port, which in this case is PWM_Command_Channel_2. PWM Invalid Instruction Status bit for PWM Channel 0 `0' No invalid command encountered during the instruction execution. `1' Invalid command encountered and this puts the PWM Channel 0 into reset state. PWM Invalid Instruction Status bit for PWM Channel 1 `0' No invalid command encountered during the instruction execution. `1' Invalid command encountered and this puts the PWM Channel 1 into reset state. PWM Invalid Instruction Status bit for PWM Channel 2 `0' No invalid command encountered during the instruction execution. `1' Invalid command encountered and this puts the PWM Channel 2 into reset state.
1
EN1
2
EN2
3
II0
4
II1
5
II2
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PWM controller
STMPE2401
11.3
PWM instruction channel x (PWMICx)
This PWMICx is the dataport that allows the instructions to be loaded into the PWM channel. The loading of the instructions is achieved by continuously writing to this dataport. As this dataport address falls on the non-auto increment region, continuous write operation on I2C will write into the same dataport address. The `x' value is from 0 to 2 as there are 3 independent PWM channels. To access these dataports, the corresponding ENx in the PWMCS register must be set to 0 first to put the PWM channel in reset state.
B it
7
IB7
6
IB6
5
IB5
4
IB4
3
IB3
2
IB2
1
IB1
0
IB0
Read/Write
RW
RW 0
RW 0
RW 0
RW 0
RW 0
RW 0
RW 0
Reset Value 0
Table 33. Pin description
Bits 7:0 Name IB[x] Description PWM Instruction Channel x, where x is 7 to 0 As an instruction is 16-bit width, writing the instruction into this 8-bit PWMICx dataport requires two 8-bit data write. The most significant byte of the 16-bit instruction is to be written in first and followed by the least significant byte of the instruction. The same effect applies to the read operation.
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STMPE2401
PWM commands
12
PWM commands
The STMPE2401 PWM Controller works as a simple MCU, with program space of 64 instructions and a simple instruction set. The instructions are all 16 bits in length. The 3 most significant bits are used to identify the commands. Table 34. PWM commands
Instruction RAMP Set Maximum (SMAX) Description This instruction starts the PWM counters and set the pwm_x_out with the result from the counting. Load the PWM counter with the value of 0xff and the pwm_x_out will result in logic level low.
Set Minimum (SMIN) Load the PWM counter with the value of 0x0 and the pwm_x_out will result in logic level high. Go to Start (GTS) BRANCH Branch to the address 0x0 and execute from 0x0 and onwards. Branch to a relative or an absolute address to execute with the looping capability. There are 4 loop counters available and these allow 4 nested loops. End the instruction execution by resetting and interrupting to the host. Capable of waiting as well as sending triggers to another PWM channel.
END Trigger (TRIG)
Table 35. Identification of instructions
Instruction Ramp SetFullScale SetMinimum GoToStart Branch End Trigger Reserved Bit 15 0 0 0 0 1 1 1 1 Bit 14 0 1 1 0 Bit 13 1 0 1 0
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PWM commands Table 36. Instruction
Bit Instruction 15 RAMP 0 14 Prescale 0=16 1=512 13 12 11 10 9 8 7 6 5 4321 0 Step Time 0 - 63 0 = immediate action Sign Increment 0=step- 1 126 up 1=stepdown
STMPE2401
Timing in 2kHz Increment value of 0 is not allowed. prescale = 16 :Consumes [(step time)(1)(increme nt)] cycles prescale = 512 :Consumes [(32)(1) (step time)(1)(increme nt)] cycles
SMAX SMIN GTS BRANCH
0 0 0 1
x(2) x(2) 0 01
0 0 0
0 1 0 Loop Counter to Loop Count use 0 15 0-3 0 = forever loop
127 127 0 0=absol Step Size ute step 0 63(1) size 1=relativ e step size(1)
Consumes 1 cycle Consumes 1 cycle Consumes 1 cycle Consumes 1 cycle Once the loop count has been reached, the loop counter resets. Consumes 1 cycle
END
1
10
Interr Reset upt to instructi host on counter and output level to zero
RESERVED
TRIG
1
11
Wait for Trigger on channel 0 2 Continues if all selected triggers present. Each bit signifies wait for the corresponding channel. RESERVED
Send Trigger on channel 0 2 Continues if no Wait for Trigger in this instruction.
x
(2)
Consumes 1 or more cycles
reser ved
1
00
Reserved.
1. Absolute Branch jumps to the absolute address (relative to address 0x0) using the value of step size. The Relative Branch jumps in a backward manner relative to the current address location, ie. 1 means jump to the previous instruction location and 0 means NOP. 2. Don't care.
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STMPE2401
PWM commands In order to enable a PWM channel, the programming sequence below should be observed.
The ENx of the PWMCS register should be kept in `0'. By default, it has a value of `0'. Loads the instructions into the PWM channel x by writing the corresponding PWMICx. The PWM channel x has a 64-word depth (16-bit width). Any instructions of size less than or equal to 64 words can be loaded into the channel. Any attempt to load beyond 64 words will result in internal address pointer to roll-over (0x1f 0x00) and the excess instructions to be over-written into the first address location of the channel and onwards. After the instructions are loaded in, then, the PWM channel x can be enabled by setting a `1' to the ENx bit. Enables the corresponding interrupt mask bit to allow interruption to the host.
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Keypad controller
STMPE2401
13
Keypad controller
The main operations of the keypad controller are controlled by four dedicated key controllers that support up to four simultaneous dedicated key presses and a key scan controller and two normal key controllers that support a maximum of 12x8 key matrix with detection of two simultaneous key presses. Four of the column inputs can be configured as dedicated keys through the setting of Dkey0~3 bits of KPC_ctrl register. The normal key matrix size is configurable through the setting of KPC_row and KPC_col registers. The scanning of each individual row output and column input can be enabled or masked to support a key matrix of variable size from 1x1 to 12x8. The operation of the keypad controller is enabled by the SCAN bit of KPC_ctrl register. Every key activity detected will be de-bounced for a period set by the DB_0~7 bits of KPC_ctrl register before a key press or key release is confirmed and updated into the output FIFO. The key data, indicating the key coordinates and its status (up or down), is loaded into the FIFO at the end of a specified number of scanning cycles (set by ScanCount0~3 bits of KPC_row_msb register). An interrupt will be generated when a new set of key data is loaded. The FIFO has a capacity for four sets of key data. Each set of key data consists of three bytes of information when any of the four dedicated keys is enabled. It is reduced to two bytes when no dedicated key is involved. When the FIFO is full before its content is read, an overflow signal will be generated while the FIFO will continue to hold its content but forbid loading of new key data set. Figure 9. Keypad controller
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STMPE2401
Keypad controller The keypad column inputs enabled by the KPC_col register are normally `HIGH', with the corresponding input pins pulled up by resistors internally. After reset, all the keypad row outputs enabled by the KPC_row register are driven `LOW'. If a key is pressed, its corresponding column input will become `LOW' after making contact with the `LOW' voltage on its corresponding row output.
Once the key scan controller senses a `LOW' input on any of the column inputs, the scanning cycles will then start to determine the exact key that has been pressed. The twelve row outputs will be driven `LOW' one by one (if the row output is enabled) during each scanning cycle. While one row is driven `LOW', the other rows are driven `HIGH'. (The pullups and pull-downs of row outputs are always disabled). If there is any column input sensed as `LOW' when a row is driven `LOW', the key scan controller will then decode the key coordinates (its corresponding row number and column number), save the key data into a de-bounce buffer if available, confirm if it is a valid key press after de-bouncing, and update the key data into output data FIFO if valid.
13.1
Registers in keypad controller
Table 37. Register in keypad controller
Address 0x60 0x61 0x62 0x63 0x64 0x68 0x69 0x6A Register name KPC_col KPC_row_msb KPC_row_lsb KPC_ctrl_msb KPC_ctrl_lsb KPC_data_byte0 KPC_data_byte1 KPC_data_byte2 Keypad data register Keypad control register Description Keypad column scanning register Keypad row scanning register Auto-Increment (during sequential R/W) Yes Yes Yes Yes Yes No No No
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Keypad controller
STMPE2401
13.2
KPC_col register
Table 38. KPC_col Register
Bit Name Read/Write Reset Value Bit 7 6 5 4 3 2 1 0 W 0 W 0 Name Input Column 7 Input Column 6 Input Column 5 Input Column 4 Input Column 3 Input Column 2 Input Column 1 Input Column 0 W 0 7 6 5 4 3 2 1 0 Input Column 0 ~ 7 W 0 W 0 W 0 Description `1' to turn on scanning of column 7; `0' to turn off `1' to turn on scanning of column 6; `0' to turn off `1' to turn on scanning of column 5; `0' to turn off `1' to turn on scanning of column 4; `0' to turn off `1' to turn on scanning of column 3; `0' to turn off `1' to turn on scanning of column 2; `0' to turn off `1' to turn on scanning of column 1; `0' to turn off `1' to turn on scanning of column 0; `0' to turn off W 0 W 0
13.3
KPC_row_msb register
Table 39. KPC_row_msb register
Bit Name Read/Write Reset Value Bit 7 6 5 4 3 2 1 0 7 ScanPW1 1 Name ScanPW1 ScanPW0 Output Row 11 Output Row 10 Output Row 9 Output Row 8 `1' to turn on scanning of row 11; `0' to turn off `1' to turn on scanning of row 10; `0' to turn off `1' to turn on scanning of row 9; `0' to turn off `1' to turn on scanning of row 8; `0' to turn off 6 ScanPW0 1 5 0 4 0 W 0 3 2 1 0 Output Row 8 ~ 11 W 0 Description Pulse width setting of keypad scanning. Use "11" at all times W 0 W 0
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STMPE2401
Keypad controller
13.4
KPC_row_lsb register
Table 40. KPC_row_lsb register
Bit Name Read/Write Reset Value Bit 7 6 5 4 3 2 1 0 W 0 W 0 Name output Row 7 output Row 6 output Row 5 output Row 4 output Row 3 output Row 2 output Row 1 output Row 0 W 0 7 6 5 4 3 2 1 0 output Row 0 ~ 7 W 0 W 0 W 0 Description `1' to turn on scanning of row 7; `0' to turn off `1' to turn on scanning of row 6; `0' to turn off `1' to turn on scanning of row 5; `0' to turn off `1' to turn on scanning of row 4; `0' to turn off `1' to turn on scanning of row 3; `0' to turn off `1' to turn on scanning of row 2; `0' to turn off `1' to turn on scanning of row 1; `0' to turn off `1' to turn on scanning of row 0; `0' to turn off W 0 W 0
13.5
KPC_ctrl_msb register
Table 41. KPC_ctrl_msb register
Bit Name Read/Write Reset Value Bit 7 6 5 4 3 2 1 0 W 0 7 6 5 4 3 2 1 0 ScanCount0 ~ 3 W 0 Name ScanCount3 ScanCount2 ScanCount1 ScanCount0 DKey_3 DKey_2 DKey_1 DKey_0 Set `1' to use Input Column 3 as dedicated key Set `1' to use Input Column 2 as dedicated key Set `1' to use Input Column 1 as dedicated key Set `1' to use Input Column 0 as dedicated key W 0 W 0 W 0 DKey_0 ~ 3 W 0 Description Number of key scanning cycles elapsed before a confirmed key data is updated into output data FIFO (0 ~ 15 cycles) W 0 W 0
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Keypad controller
STMPE2401
13.6
KPC_ctrl_lsb register
Table 42. KPC_ctrl_lsb register
Bit Name Read/Write Reset Value Bit 7 6 5 4 3 2 1 0 W 0 W 0 Name DB_6 DB_5 DB_4 DB_3 DB_2 DB_1 DB_0 SCAN `1' to start scanning; `0' to stop W 0 7 6 5 4 DB_0 ~ 5 W 0 W 0 W 0 Description 0-128ms of de-bounce time W 0 3 2 1 0 SCAN W 0
13.7
Data registers
The KPC_DATA register contains three bytes of information. The first two bytes store the key coordinates and status of any two keys from the normal key matrix, while the third byte store the status of dedicated keys. Table 43. KPC_data_byte0 register
Bit Name Read/Write Reset Value Bit 7 6 7 Up/Down R 1 Name Up/Down R3 6 R3 R 1 5 R2 R 1 4 R1 R 1 3 R0 R 1 2 C2 R 0 1 C1 R 0 0 C0 R 0
Description `0' for key-down, `1' for key-up row number of key 1 (valid range : 0-11) 0x1111 for No Key
5 4 3 2 1 0
R2 R1 R0 C2 C1 C0 column number of key 1 (valid range : 0-7)
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STMPE2401
Keypad controller
Table 44. KPC_data_byte1 register
Bit Name Read/Write Reset Value Bit 7 6 5 4 3 2 1 0 7 Up/Down R 1 6 R3 R 1 Name Up/Down R3 R2 R1 R0 C2 C1 C0 column number of key 2 (valid range : 0-7) 5 R2 R 1 4 R1 R 1 3 R0 R 1 2 C2 R 0 Description `0' for key-down, `1' for key-up row number of key 2 (valid range : 0-11) 0x1111 for No Key 1 C1 R 0 0 C0 R 0
Table 45. KPC_data_byte2 register
Bit Name Read/Write Reset Value Bit 7 6 5 4 3 2 1 0 7 R 0 6 R 0 Name Dedicated Key 3 Dedicated Key 2 Dedicated Key 1 Dedicated Key 0 `0' for key-down, `1' for key-up `0' for key-down, `1' for key-up `0' for key-down, `1' for key-up `0' for key-down, `1' for key-up 5 R 0 4 R 0 R 1 3 2 1 0 Dedicated Key 0 ~ 3 R 1 Description R 1 R 1
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Keypad controller
STMPE2401
13.7.1
Resistance
Maximum resistance between keypad output and keypad input, inclusive of switch resistance, protection circuit resistance and connection, must be less than 3.2 K
13.7.2
Using the keypad controller
Before enabling the keypad controller operation, proper setup should be done by configuring the input and output ports involved. This is achieved by programming the corresponding GPIO control registers that determine the port direction and the necessary internal pull-up or pull-down. For the GPIO ports that are used as keypad inputs, internal pull-up should be enabled. For those that are used as keypad outputs, no internal pull-up or pull-down should be enabled.
The scanning of column inputs should then be enabled for those GPIO ports that are configured as keypad inputs by writing `1's to the corresponding bits in the KPC_col register. If any of the first three column inputs is to be used as dedicated key input, the corresponding bits in the KPC_ctrl_msb register should be set to `1'. The bits in the KPC_row_msb and KPC_row_lsb registers should also be set correctly to enable the row output scanning for the corresponding GPIO ports programmed as keypad outputs.
The scan count and de-bounce count should also be programmed into the keypad control registers before enabling the keypad controller operation. To enable the keypad controller operation, the Enable_KPC bit in the system control register must be set to `1' to provide the required clock signals. The keypad controller will then start its operation by setting the SCAN bit in the KPC_ctrl_lsb register to `1'.
The keypad controller operation can be disabled by setting the SCAN bit back to `0'. To further reduce the power consumption, the clock signals can be cut off from the keypad controller by setting the Enable_KPC bit to `0'.
ScanCount value is programmable to any value between 1-15 by writing into the scancount register. If scan count is programmed to N, the Keypad Controller scans the entire matrix for N times, collecting up to 2 matrix key and 4 dedicated keys, loads the keys into 1 set of keypad data buffer and interrupts the host system.
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STMPE2401
Rotator controller
14
Rotator controller
Rotator controller consists of 3 terminal, each capable of becoming an input with internal pull-up, or and output. At any moment, 2 terminals are inputs and one terminal is output. Figure 10. Rotator controller
The Rotator Controller is responsible for the detection of the direction of rotator and the reporting of these direction sequences. The direction of a rotator can be either up or down. A rotator has 3 contacts and detection of shorts on these contacts is used to determine the direction of rotation. Following diagram shows the definition of the direction of rotation and how the FSM states and driven outputs correspond to rotation. Table 46. 3 possible conditions: A-B short, B-C short, C-A short.
LO Input C B A C A B Current State State 1 1 2 2 3 3 Output A A B B C C Input B B A A A A Input C C C C B B State 2 3 3 1 2 1 Next State Result Output B C C A B A Input A A A B A B Input C B B C C C Up Down Down Up Up Down
Figure 11. Possible conditions
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Rotator controller
STMPE2401
Table 47. Registers for rotator control
Address 0x70 0x72 Register name Rotator_Control Rotator_Buffer Register Size 8 8
14.1
Rotator_Control
Bit
7 Star t_FSM
6
5
4
3
2
1
0
Reserved R 0 R 0 R 0 R 0 R 0 R 0 R 0
Read/Write
RW
Reset Value 0
Bits 7
Name Star t_FSM
Description Rotator FSM start bit. `1' Activate the FSM `0' Stop sampling rotator symbols
14.2
Rotator_Buffer
Bit
7 Symbol_Type
6
5
4
3 Symbol_Count
2
1
0
Read/Write Reset Value
R 0
R 0
R 0
R 0
R 0
R 0
R 0
R 0
Bits 7
Name Symbol_Type Symbol type to be reported `1' Down `0' Up
Description
6~0
Symbol_Count Number of symbols of the type specified by bit 7 Minimum of 0 (b'0 0 000) to Maximum of 127 (b'1111111)
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STMPE2401
Rotator controller The host should do the following on the I2C bus to start the Rotator controller: 1. 2. The host writes to GPIO Controller to configure the PU/PD bit and select the Rotator Bits on the relevant IO. Write Rotator_Control data register to start the rotator controller. A maximum of 2 rotations later, the correct initial state on the rotator FSM is obtained. Scanning for rotator movement continues. The host waits for interrupt from the rotator controller. The host reads Rotator_Buffer The host can stop rotator controller operation by writing to Rotator_Control register.
3. 4. 5.
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Miscellaneous features
STMPE2401
15
15.1
Miscellaneous features
Reset
STMPE2401 is equipped with an internal POR circuit that holds the device in reset state, until the clock is steady and VCC input is valid. Host system may choose to reset the STMPE2401 by asserting Reset_N pin.
15.2
Under voltage lockout
STMPE2401 is equipped with an internal UVLO circuit that generates a RESET signal, when the main supply voltage falls below the allowed threshold.
15.3
Clock output
STMPE2401 provides a buffered 32KHz clock output at one of the GPIO as alternate function. This clock could be used for cascading of multiple port expander devices, using just 1 XTAL unit.
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STMPE2401
Mechanical data
16
Mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com
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Mechanical data
STMPE2401
Table 48. TFBGA Mechanical data
mm. Dim. Min A A1 A2 b D D1 E E1 e F 0.30 3.60 3.50 3.50 2.50 0.50 0.55 3.60 3.70 0.78 0.25 3.50 1.1 Typ 1 Max 1.16 0.25 0.86 0.35 3.70 0.012 0.142 0.138 0.142 0.098 0.020 0.022 0.138 0.146 0.031 0.010 0.138 Min 0.043 Typ 0.039 Max 0.046 0.010 0.034 0.014 0.146 inch
Figure 12. Package dimensions
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STMPE2401 Figure 13. Recommended footprint
Mechanical data
Figure 14. Tape and reel information
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Revision history
STMPE2401
17
Revision history
Table 49. Revision history
Date 08-Jan-2007 29-May-2007 Revision 1 2 Initial release Cover page updated Changes
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STMPE2401
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