STS9D8NH3LL
Dual N-channel 30 V - 0.012 - 9 A - SO-8 low on-resistance STripFETTM Power MOSFET
Features
Type STS9D8NH3LL
VDSS Q1 Q2 30V 30V
RDS(on) < 0.022 < 0.015
Qg 7nC 8nC
ID 8A 9A
Optimal RDS(on) x Qg trade-off @ 4.5V Conduction losses reduced Switching losses reduced
S0-8
Application
Switching applications Figure 1. Internal schematic diagram
Description
This device uses the latest advanced design rules of ST's STrip based technology. The Q1 and Q2 transistors, show respectively, the best gate charge and on-resistance for minimizing the switching and conduction losses. This application specific Power MOSFET has been designed to replace two SO-8 packages in DC-DC converters.
Table 1.
Device summary
Order code Marking 9D8H3LLPackage SO-8 Packaging Tape & reel
STS9D8NH3LL
December 2007
Rev 3
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www.st.com 14
Contents
STS9D8NH3LL
Contents
1 2 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Electrical characteristics (curves) . . .. . .. . .. . .. . ..... 5
3 4 5
Test circuit
. . .. . .. . .. . .. . .. . .. . .. . .. . .... 8
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
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STS9D8NH3LL
Electrical ratings
1
Electrical ratings
Table 2.
Symbol VDS VGS ID ID IDM (1) PTOT EAS(2)
Absolute maximum ratings
Parameter Drain-source voltage (vGS = 0) Gate- source voltage Drain current (continuous) at TC = 25C Drain current (continuous) at TC = 100C Drain current (pulsed) Total dissipation at TC = 25C Single pulse avalanche energy Type Q1 Q2 Q1 Q2 Q1 Q2 Q1 Q2 Q1 Q2 Q1 Q2 Value 30 30 16 16 8 9 5 6.3 32 36 2 2 150 Unit V V V V A A A A A A W W mJ
1. Pulse width limited by safe operating area 2. Starting TJ = 25 C, ID = 7.5 A
Table 3.
Symbol Rthj-a (1) TJ Tstg
Thermal data
Parameter Thermal resistance junction-ambient max Thermal operating junction-ambient Storage temperature Value 62.5 150 -55 to 150 Unit C/W C C
1. When mounted on 1 inch² FR-4 board, 2 oz. Cu., t < 10s
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Electrical characteristics
ST S 9 D 8 N H 3 L L
2
Electrical characteristics
(TCASE=25C unless otherwise specified) Table 4.
Symbol V(BR)DSS IDSS IDSS IGSS VGS(th) RDS(on) RDS(on)
On/off states
Parameter Drain-source Breakdown voltage Zero gate voltage Drain current (VGS = 0) Zero gate voltage Drain current (VGS = 0) Gate-body leakage current (VDS = 0) Gate threshold voltage Static drain-source on resistance Static drain-source on resistance Test conditions ID = 250 A, VGS = 0 VDS = Max rating VDS =Max rating @125C VGS = 16 V VDS = VGS, ID = 250 A VGS = 10 V, ID = 4 A VGS = 10 V, ID = 4.5 A VGS = 4.5 V, ID = 4 A VGS = 4.5 V, ID = 4.5 A Type Q1 Q2 Q1 Q2 Q1 Q2 Q1 Q2 Q1 Q2 Q1 Q2 Q1 Q2 1 1 0.018 0.012 0.020 0.014 0.022 0.015 0.025 0.0175 Min. 30 30 1 1 10 10 100 100 Typ. Max. Unit V V A A A A nA nA V V
Table 5.
Symbol Ciss Coss Crss Qg Qgs Qgd
Dynamic
Parameter Input capacitance Output capacitance Reverse transfer capacitance Total gate charge Gate-source charge Gate-drain charge VDD = 15 V, ID = 8 A, VGS = 4.5 V (see Figure 25) VDS = 25 V, f = 1 MHz, VGS = 0 Test conditions Type Q1 Q2 Q1 Q2 Q1 Q2 Q1 Q2 Q1 Q2 Q1 Q2 Min. Typ. 857 1070 147 290 20 34 7 8 2.5 2 2.3 2.8 10 11 Max. Unit pF pF pF pF pF pF nC nC nC nC nC nC
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STS9D8NH3LL Table 6.
Symbol td(on) tr td(off) tf Turn-off delay time Fall time Turn-on delay time Rise time
Electrical characteristics Switching times
Parameter Test conditions VDD=15 V, ID=4 A, RG=4.7 , VGS= 4.5 V (see Figure 27) VDD=15 V, ID=4 A, RG=4.7 , VGS= 4.5V (see Figure 27) Type Q1 Q2 Q1 Q2 Q1 Q2 Q1 Q2 Min. Typ. 12 8.2 14.5 6 23 27.8 8 3.6 Max. Unit ns ns ns ns ns ns ns ns
Table 7.
Symbol
Source drain diode
Parameter Test conditions VDD=15 V, ID=4 A , RG=4.7 VGS=4.5 V VDD=15 V, ID= 4A , RG=4.7 VGS=4.5 V ISD = 8 A, VGS = 0 Type Q1 Q2 Q1 Q2 Q1 Q2 Q1 Q2 Q1 Q2 Q1 Q2 15 22.8 5.7 14.9 0.76 1.3 Min Typ. Max 8 9 32 36 1.5 1.5 Unit A A A A V V ns ns nC nC A A
ISD
Source-drain current
ISDM (1)
Source-drain current (pulsed)
VSD (2) t rr Qrr IRRM
Forward on voltage Reverse recovery time
ISD = 8 A, VDD = 15 V Reverse recovery charge di/dt = 100 A/s, T = 150C Reverse recovery current j (see Figure 26)
1. Pulse width limited by safe operating area. 2. Pulsed: Pulse duration = 300 s, duty cycle 1.5%
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Electrical characteristics
ST S 9 D 8 N H 3 L L
2.1
Figure 2.
Electrical characteristics (curves)
Safe operating area for Q1 Figure 3. Safe operating area for Q2
Figure 4.
Thermal impedance for Q1
Figure 5.
Thermal impedance for Q2
Figure 6.
Output characteristics for Q1
Figure 7.
Output characteristics for Q2
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STS9D8NH3LL Figure 8. Transfer characteristics for Q1 Figure 9.
Electrical characteristics Transfer characteristics for Q2
Figure 10. Static drain-source on resistance for Q1
Figure 11. Static drain-source on resistance for Q2
Figure 12. Normalized BVDSS vs temperature for Q1
Figure 13. Normalized BVDSS vs temperature for Q2
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Electrical characteristics
ST S 9 D 8 N H 3 L L
Figure 14. Gate charge vs gate-source voltage Figure 15. Gate charge vs gate-source voltage for Q1 for Q2
Figure 16. Capacitance variations for Q1
Figure 17. Capacitance variations for Q2
Figure 18. Normalized gate threshold voltage vs temperature for Q1
Figure 19. Normalized gate threshold voltage vs temperature for Q2
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STS9D8NH3LL Figure 20. Normalized on resistance vs temperature for Q1
Electrical characteristics Figure 21. Normalized on resistance vs temperature for Q2
Figure 22. Source-drain diode forward characteristics for Q1
Figure 23. Source-drain diode forward characteristics for Q2
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Test circuit
STS9D8NH3LL
3
Test circuit
Figure 25. Gate charge test circuit
Figure 24. Switching times test circuit for resistive load
Figure 26. Test circuit for inductive load Figure 27. Unclamped Inductive load test switching and diode recovery times circuit
Figure 28. Unclamped inductive waveform
Figure 29. Switching time waveform
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STS9D8NH3LL
Package mechanical data
4
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a Lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com
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Package mechanical data
ST S9 D8 NH3 L L
SO-8 MECHANICAL DATA
DIM. A a1 a2 a3 b b1 C c1 D E e e3 F L M S 3.8 0.4 4.8 5.8 1.27 3.81 4.0 1.27 0.6 8 (max.) 0.14 0.015 5.0 6.2 0.65 0.35 0.19 0.25 0.1 mm. MIN. TYP M AX. 1.75 0.25 1.65 0.85 0.48 0.25 0.5 45 (typ.) 0.188 0.228 0.050 0.150 0.157 0.050 0.023 0.196 0.244 0.025 0.013 0.007 0.010 0.003 MIN. inch TYP. M AX . 0.068 0.009 0.064 0.033 0.018 0.010 0.019
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STS9D8NH3LL
Revision history
5
Revision history
Table 8.
Date 05-Jan-2007 06-Mar-2007 10-Dec-2007
Document revision history
Revision 1 2 3 First release Some value changed on Table 4 (RDS(on) for Q2) Added EAS value on Table 2: Absolute maximum ratings Changes
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STS9D8NH3LL
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