STA529
2 x 100 mW class-D amplifier with analog or digital input 2.0 multichannel digital audio processor with FFX
Features
Up to 96 dB dynamic range Sample rates from 8 kHz to 192 kHz FFXTM class-D driver 1.5 V to 1.95 V digital power supply 1.5 V to 1.95 V analog power supply 18-bit audio processing and class-D FFXTM modulator Digital volume control: +36 dB to 105 dB in 0.5 dB steps Software volume update Individual channel and master gain/attenuation Automatic invalid input detect mute 2-channel I2S input/output data interface Digitally controlled POP-free operation Input and output channel mapping 250 m output CMOS Rdson > 90% efficiency Stereo headphone plus mono speaker application: 50 mW stereo into 32 headphone 100 mW stereo into 16 headphone TFBGA48
VFQFPN52
Order codes
Part number STA529B STA529Q Package TFBGA48 (tube) VFQFPN52 (tube)
January 2007
Rev 1
1/58
www.st.com 1
Contents
STA529
Contents
1 2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Connection diagrams and pin descriptions . . . . . . . . . . . . . . . . . . . . . . 5
2.1 TFBGA48 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1.1 2.1.2 2.1.3 Connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2
VFQFPN52 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2.1 2.2.2 Connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1 3.2 3.3 3.4 Maximum and recommended operating conditions . . . . . . . . . . . . . . . . . 11 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Lock time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 ADC performance values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4
Digital processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.1 4.2 4.3 Signal processing flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 I2C interface disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Volume control and gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5
PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.1 5.2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Configuration examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6
ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.1.1 6.1.2 6.1.3 Digital filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 High-pass filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Programmable gain amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.2 6.3
Application scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Configuration examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
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STA529
Contents
7
Driver configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.1 I2S bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8
Serial audio interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8.1 8.2 8.3 8.4 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Serial formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.4.1 8.4.2 8.4.3 8.4.4 DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 I2S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 PCM/IF (non-delayed mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 PCM/IF (delayed mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
9
I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
9.1 9.2 9.3 9.4 9.5 9.6 Data transition and change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Star t condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
9.6.1 9.6.2 Byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Multi-byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
9.7
Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
9.7.1 9.7.2 9.7.3 9.7.4 Current address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Current address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Random address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Random address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
10.1 10.2 Summar y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 General registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
11
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
11.1 11.2 Package TFBGA48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Package VFQFPN52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
12
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
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Introduction
STA529
1
Introduction
The STA529 is a digital stereo class-D audio amplifier. It includes an audio DSP, a ST proprietary high-efficiency class-D driver and CMOS power output stage. It is intended for high-efficiency digital-to-power-audio conversion for portable applications. The STA529 also provides output capabilities for FFXTM. In conjunction with a power device, the STA529 provides high-quality digital amplification. The STA529 contains an on-chip volume/gain control. The PWM amplifier achieves greater than 90% efficiency for longer battery life for portable systems. The innovative class-D modulation, allows the STA529 to work without external LC filters and without a heatsink. The STA529 I2CDIS pin disables the audio DSP functions to provide a direct conversion of the input signal into output power (the I2C interface is disabled). This conversion is done without the microcontroller. The STA529 is designed for low-power operation with extremely low-current consumption in standby mode. It is available in two packages: the TFBGA48 and the VFQFPN52. These are very thin packages (1.2 mm thick) intended for small portable applications.
Figure 1.
Block diagram
LRCLKO/PWM1B SDATAO/PWM2A BICLKO/PWM1A POWERFAULT/ EADP
LRCLKI
SDATAI
RST_N STBY
GNDIO
GND33
MUTE
VDDIO
VCC33
BICLKI
GND2
GND1
Serial digital audio interface Power driver Digital volume
MUX OUT1A OUT1B MUX
TM
VBIAS INL VHI VCM VLO INR
FFX modulator Power driver PWM out I/F Control interface
OUT2A OUT2B
ADC
PGA ADC OSC PLL
Divider
SELCLK33
CLKOUT/ PWM2B
XTI
MCLK33
GNDPLL
FILT VDDPLL
4/58
I2CDIS
AVCC
AGND
XTO
SDA
SCL
VCC2
VCC1
GND
VDD
MUX
STA529
Connection diagrams and pin descriptions
2
Connection diagrams and pin descriptions
This section includes connection diagrams and pin descriptions for the following packages:
TFBGA48 VFQFPN 52
2.1
2.1.1
TFBGA48 package
Connection diagram
Figure 2 shows the connection diagram for the TFBGA48 package. Figure 2. Package: TFBGA48
H G F E D C B A
1
2
3
4
5
6
7
8
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Connection diagrams and pin descriptions
STA529
2.1.2
Pin description
Table 1.
Pin # D7 D1 E1
Package: TFBGA48
Name RST_N XTI MCLK33 Type Digital input Digital input Digital input Reset (active low) Crystal input or master clock input Master clock input 3.3 V capable XTI: crystal input or master clock input 3.3 V capable Master clock input selector: SELCLK33 = 1 -> MCLK33 selected SELCLK33 = 0 -> XTI selected Crystal output Buffered clock output / PWM2B FFXTm I2C serial clock I2C serial data I2C disable pin (active high) Standby (active high) Mute (active high) Input serial audio interface bit-clock Input serial audio interface L/R-clock Input serial audio interface data Output serial audio interface bit-clock (volume DOWN when I2CDIS = 1) / PWM1A FFXTm Output serial audio interface L/R-clock (volume UP when I2CDIS = 1) / PWM1B FFXTm Output serial audio interface data / PWM2A FFXTm Test mode (active high) ADC left channel line input or microphone input ADC right channel line input ADC microphone bias voltage ADC common mode voltage ADC analog supply ADC analog ground Description
G3 D2 C7 F1 G1 G2 G8 B7 H6 H5 E2 G6 G5 G4 H2 H7 H8 G7 D8 F8 E8
SELCLK33 XTO CLKOUT/ PWM2B SCL SDA I2CDIS STBY MUTE BICLKI LRCLKI SDATAI BICLKO/ PWM1A LRCLKO/ PWM1B SDATAO/ PWM2A TM INL INR VBIAS VCM AVDD AGND
Digital input Digital output Digital output Digital input Digital input/output Digital input Digital input Digital input Digital input/output Digital input/output Digital input Digital input/output Digital input/output Digital output Digital input Analog input Analog input/output Analog input/output Analog input/output Supply Ground
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STA529 Table 1.
Pin # F7 E7 H1 H4 H3 A6 B6 A5 B5 A3 B3 A4 B4 F2 A8 A1 A7 A2 C2 B2 C8 B8 C1 B1
Connection diagrams and pin descriptions Package: TFBGA48 (continued)
Name VHI VLO FILT VDDPLL GNDPLL OUT1A OUT1A OUT1B OUT1B OUT2A OUT2A OUT2B OUT2B Type Analog input Analog input Analog input/output Supply Ground Analog output Analog output Analog output Analog output Analog output Analog output Analog output Analog output Description ADC high reference voltage ADC low reference voltage PLL loop filter terminal PLL analog supply PLL analog ground Channel 1 half-bridge A output Channel 1 half-bridge A output Channel 1 half-bridge B output Channel 1 half-bridge B output Channel 2 half-bridge A output Channel 2 half-bridge A output Channel 2 half-bridge B output Channel 2 half-bridge B output Power fault signal (active high) / external audio power-down signal Channel 1 power supply Channel 2 power supply Channel 1 power ground Channel 2 power ground Pre-driver supply Pre-driver ground Digital supply Digital ground I/O ring supply I/O ring ground
POWERFAULT/ Digital output EADP VCC1 VCC2 GND1 GND2 VCC33 GND33 VDD GND VDDIO GNDIO Supply Supply Ground Ground Supply Ground Supply Ground Supply Ground
2.1.3
Thermal data
Table 2 gives the thermal resistance specifications for the TFBGA48 and the VFQFPN52. Table 2.
Device TFBGA48 VFQFPN52
Thermal data
Parameter Thermal resistance junction to ambient Thermal resistance junction to ambient Min Typ 72 22 Ma x Unit
oC/W oC/W
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Connection diagrams and pin descriptions
STA529
2.2
2.2.1
VFQFPN52 package
Connection diagram
Figure 3 shows the connection diagram for the VFQFPN52 package. Figure 3. Package: VFQFPN52
27 39
26
40
14
52
13
1
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STA529
Connection diagrams and pin descriptions
2.2.2
Pin description
Table 3.
Pin # 10 38 37
Package: VFQFPN52
Name RST_N XTI MCLK33 Type Digital input Digital input Digital input Reset (active low) Crystal input or master clock input Master clock input 3.3 V capable XTI: crystal input or master clock input 3.3 V capable Master clock input selector: SELCLK33 = 1 -> MCLK33 selected SELCLK33 = 0 -> XTI selected Crystal output Buffered clock output I2C serial clock I2C serial data I2C disable pin (active high) Standby (active high) Mute (active high) Input serial audio interface bit-clock Input serial audio interface L/R-clock Input serial audio interface data Output serial audio interface bit-clock (volume DOWN when I2CDIS=1) Output serial audio interface L/R-clock (volume UP when I2CDIS=1) Output serial audio interface data Test mode (active high) ADC left channel line input or microphone input ADC right channel line input ADC microphone bias voltage ADC Common mode voltage ADC analog supply ADC analog ground ADC High reference voltage Description
36 39 11 34 35 33 1 14 51 47 45 52 48 46 32 2 3 4 9 5 8 6
SELCLK33 XTO CLKOUT SCL SDA I2CDIS STBY MUTE BICLKI LRCLKI SDATAI BICLKO LRCLKO SDATAO TM INL INR VBIAS VCM AVDD AGND VHI
Digital input Digital output Digital output Digital input Digital input/output Digital input Digital input Digital input Digital input/output Digital input/output Digital input Digital input/output Digital input/output Digital output Digital input Analog input Analog input/output Analog input/output Analog input/output Supply Ground Analog input
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Connection diagrams and pin descriptions Table 3.
Pin # 7 40 42 41 16 19 25 22 31 15 20 26 21 17 18 24 23 30 27 13 12 44 43 29 28 50 49
STA529
Package: VFQFPN52 (continued)
Name VLO FILT VDDPLL GNDPLL OUT1A OUT1B OUT2A OUT2B Type Analog input Analog input/output Supply Ground Analog output Analog output Analog output Analog output Description ADC Low reference voltage PLL loop filter terminal PLL analog supply PLL analog ground Channel 1 half-bridge A output Channel 1 half-bridge B output Channel 2 half-bridge A output Channel 2 half-bridge B output Power fault signal (active high)/external audio power down signal Channel 1 half-bridge A power supply Channel 1 half-bridge B power supply Channel 2 half-bridge A power supply Channel 2 half-bridge B power supply Channel 1 half-bridge A power ground Channel 1 half-bridge B power ground Channel 2 half-bridge A power ground Channel 2 half-bridge B power ground Pre-driver supply Pre-driver ground Digital supply Digital ground Digital supply Digital ground I/O ring supply I/O ring ground I/O ring supply I/O ring ground
POWERFAULT/ Digital output EADP VCC1A VCC1B VCC2A VCC2B GND1A GND1B GND2A GND2B VCC33 GND33 VDD1 GND1 VDD2 GND2 VDDIO1 GNDIO1 VDDIO2 GNDIO2 Supply Supply Supply Supply Ground Ground Ground Ground Supply Ground Supply Ground Supply Ground Supply Ground Supply Ground
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STA529
Electrical specifications
3
Electrical specifications
This section includes the electrical specifications for the STA529.
3.1
Maximum and recommended operating conditions
Table 4 provides the maximum ratings and Table 5 the recommended operating conditions. Table 4. Absolute maximum ratings
Description Digital supply voltage ADC supply voltage PLL analog supply voltage Power stage supply voltage Pre-driver supply Digital I/O supply Voltage range digital in Voltage range analog in Voltage on output pins Storage temperature Ambient operating temperature Min -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -4 0 -2 0 Ma x +2.5 +4 +2.5 +4 +4 +4 VDDIO +0.3 AVDD +0.3 VDDIO +0.3 150 85 Unit V V V V V V V V V
oC oC
Signal VDD/VDD1/VDD2 AVDD VDDPLL VCC1A/1B/2A/2B VCC33 VDDIO VDI VAI Vo TSTG TAMB
Note:
All grounds must be within 0.3 V of each other. Table 5. Recommended operating conditions
Parameter Digital supply voltage ADC supply voltage PLL analog supply voltage Power stage supply voltage Pre-driver supply Channel 1 and 2 power ground, pre-driver ground Ambient operating temperature 0 Min 1.55 1.8 1.55 1.8 1.8 Typ 1.8 3.3 1.8 3.3 3.3 0 25 70
o
Symbol VDD/VDD1/VDD2 AVDD VDDPLL VCC1A/1B/2A/2B VCC33 GND1, GND2, GND33 TAMB
Max 1.95 3.6 1.95 3.6 3.6
Unit V V V V V
C
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Electrical specifications
ST A 5 2 9
3.2
Table 6.
Symbol Eff Rdson IstbyL IstbyP IddL IddP Tds Tdd Tr Tf THDN THDN
Electrical characteristics
Table 6 lists the device's electrical characteristics (see also Table 5 for supply voltages). Electrical characteristics
Parameter Output power efficiency Output stage N/PMOS onresistance Logic power supply current at standby Bridges power supply current in standby Logic power supply current at operating Bridges power supply current at operating Low current dead time (static) High current dead time (dynamic) Rise time Fall time Total harmonic distortion Total harmonic distortion 0 dBFS input, 32 load headphone -6 dBFS input, 32 load headphone Test conditions Min Typ 90 250 1.3 0.7 15 0.5 1 2.5 3 3 0.1 0.05 Max Unit % m A A mA mA ns ns ns ns % %
Note:
LRCLKI frequency (Fs) = 48 kHz, input frequency = 1 kHz, and Rload = 32 unless otherwise specified.
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STA529
Electrical specifications The following tables give the distortion values for headphones and speakers. Table 7. Load power at 1% distortion headphone mode
P (mW) at 1.8 V 20 10 P (mW) at 3.3 V 70 32 P (mW) at 3.6 V 80 40
Load () 16 32
3.3
Lock time
Table 8 gives the typical lock time of the PLL using the suggested loop filter, 1.8 V supply voltage and 30 oC junction temperature. Table 8. PLL lock time
Parameter Lock time Value 200 s
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Electrical specifications
ST A 5 2 9
3.4
ADC performance values
Table 9. Programmable gain performance
Parameter Dynamic range 1 kHz 1.8 V supply Dynamic range 1 kHz 1.8 V supply A-weighted SNDR 1 kHz 1.8 V supply SNDR 1 kHz 1.8 V supply A-weighted THD 1 kHz (-1 dB input) 1.8 V supply Deviation from linear phase Pass band Pass band ripple Stop band Stop band attenuation Group delay 8 kHz Group delay 48 kHz Cross talk 1.8 V Cross talk 3.3 V 84 75 84 Min Typ Max Unit dB dB dB dB dB degree kHz dB kHz dB ms ms dB dB
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STA529
Digital processing
4
Digital processing
The STA529 processor block is a digital block providing two channels of audio processing and channel-mapping capability.
4.1
Signal processing flow
I2S or stereo ADC data can be selected. The I2S frequency range is from 8 kHz to 192 kHz. ADC sampling frequency can be selected from 8 kHz to 48 kHz.
4.2
I2C interface disabled
When pin I2CDIS = 1, the SDA, SCL, LRCLKO and BICLKO pins can be pulled high or low to change certain parameters of operation.
SDA = 0: FFX input comes from ADC SDA = 1: FFX input comes from digital audio interface SCL = 0: binary output mode (binary soft start/stop enabled) SCL = 1: phase shift output mode LRCLKO = 0: no volume change LRCLKO = 1: volume up BICLKO = 0: no volume change BICLKO = 1: volume down
At power up, the master volume is set to -60 dB. When holding pin LRCLKO = 1 and pin BICLKO = 1 simultaneously, the master volume is set to 0 dB. A high pulse on pin LRCLKO causes a master volume change of +0.5 dB and a high pulse on pin BICLKO causes a master volume change of -0.5 dB.
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Digital processing
STA529
4.3
Volume control and gain
The volume control structure of the STA529 consists of individual volume registers for each channel and a master volume register that provides an offset to each channel's volume setting. The individual channel volumes are adjustable in 0.5 dB steps from +36 dB to -91.5 dB. As an example, if register LVOL = 0x00 or +36 dB and register MVOL = 0x18 or -12 dB, then the total gain for the left channel is +24 dB. When the mute bit is set to 1, all channels are muted. The volume control provides a soft mute with the volume ramping down to mute in 4096 samples from the maximum volume setting at the internal processing rate (~48 kHz). Table 10. Master volume offset as a function of register MVOL
MVOL[7:0] 0x00 0x01 0x02 ... 0x78 ... 0xFE 0xFF Volume offset from channel value 0 dB -0.5 dB -1dB ... -60 dB ... -105 dB Hard master mute
Table 11.
Channel volume as a function of registers LVOL and RVOL
Volume +36 dB +35.5 dB +35 dB ... +0.5 dB 0 dB -0.5 dB ... ... -91.5 dB
LVOL/RVOL[7:0] 0x00 0x01 0x02 ... 0x47 0x48 0x49 ... ... 0xFF
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STA529
PLL
5
PLL
Figure 4 shows the main components of the PLL.
Figure 4.
PLL block diagram
INFIN
CLKIN IDF
Input frequency divider
FBCLK
Lock detect
LOCKP
FILT INFIN Buffer INFOUT REFOUT FBCLK VCO LF Charge pump and loop filter VCONT
Phase frequency divider (PFD)
Loop frequency divider
FVCO
STRB STRB_ BYPASS FRAC_CTRL Fractional controller
Output frequency divider
PHI
DITHER_DISABLE FRAC_INPUT
NDIV
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PLL
STA529
5.1
Functional description
Phase/frequency detector
The phase/frequency detector (PFD) compares the phase difference between the corresponding rising edges of INFIN and FBCLK, (clock output from the loop frequency divider) by generating voltage pulses with widths proportional to the input phase error.
Charge pump and loop filter
This block converts the voltage pulses from the phase/frequency detector to current pulses which charge the loop filter and generate the control voltage for the voltage-controlled oscillator. The loop filter is placed external to the PLL on pin FILT.
Voltage controlled oscillator
The voltage controlled oscillator (VCO) is the oscillator inside the PLL. It produces a frequency output (FVCO) proportional to the input control voltage.
Input frequency divider
This frequency divider divides the PLL input clock CLKIN by a factor called the input division factor (IDF) to generate the PFD input frequency INFIN.
Loop frequency divider
This frequency divider is present within the PLL for dividing FVCO by a factor called the loop division factor (LDF). The output of this block is the FBCLK.
Output frequency divider
The PLL output PHI is generated by dividing the FVCO by the output division factor (ODF). The divider that divides the FVCO to generate the clock to the core is called the output frequency divider. In the STA529, the ODF is fixed to be divisible by 2 and cannot be configured.
Lock-detect circuit
The output of this block (the LOCKP signal) is asserted high when the PLL enters the state of COARSE LOCK in which the output frequency is within +/-10% (approximately) of the desired frequency. The LOCKP signal is refreshed every 32 cycles of the INFIN. The generated value is based on the result of comparing the number of FBCLK cycles in a window of 14 INFIN cycles. The different cases generated after comparison are as follows.
If LOCKP is already at 0, then in the next refresh cycle LOCKP goes to 1 if the number of FBCLK cycles in the 14-cycle INFIN window is 13, 14, or 15. Otherwise LOCKP stays at 0. If LOCKP is already at 1, then in the next refresh cycle LOCKP goes to 0 if the number of FBCLK cycles in the 25-cycle INFIN window is less than 11 or higher than 17, otherwise LOCKP stays at 1. If LOCKP is already at 1 and CLKIN is lost (no longer present on the input pin), LOCKP stays at 1. In this case, the PLL is unlocked.
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STA529
PLL
PLL filter
Figure 5 shows the PLL filter scheme. Recommended values are R1 = 12.5 k , C1 = 250 pF, and C2 = 82 pF. Figure 5. PLL filter scheme
Vc
R1 C2 C1
Ground
Table 8 on page 13 gives a typical lock time value for the PLL.
5.2
Configuration examples
The STA529 PLL can be configured in two ways:
default startup configuration direct PLL programming
The default startup configuration reads the device's defaults. With this configuration, it is not necessary to program the PLL dividers directly as some presets are used. In this mode, the oversampling ratio between pins XTI (or MCLK33) and LRCLKI is fixed to 256. The direct PLL programming bypasses the automatic presets allowing direct programming of the PLL dividers. The output PLL frequency can be determined as following: Output division factor: ODF = 2 Relation between input and output clock frequency: FINFIN = FXTI / IDF If register bit PLLCFG0.FRAC_CTRL = 1 FVCO = FINFIN * (LDF + FRACT/216 + 1/217) FPHI = FVCO / ODF When register bit PLLCFG0.DITHER_DISABLE[1] = 1, the 1/217 factor is not in the multiplication. This is recommended in order to keep register bit PLLCFG0.DITHER_DISABLE[1] = 0, otherwise there can be spurious signals in the output clock spectrum.
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PLL If register bit PLLCFG0.FRAC_CTRL = 0, then: FVCO = FINFIN * LDF FPHI = FVCO / ODF In the above equations: FRACT = Decimal equivalent of register bit PLLCFG1.FRAC_INPUT[15:0] IDF = Input division factor (refer to previous formulas) LDF = Loop division factor (refer to previous formulas) ODF = Output division factor = 2 FINFIN = INFIN frequency FXTI = XTI frequency FVCO = VCO frequency FPHI = Frequency of the PLL output clock
STA529
When selecting the value of IDF, LDF and FRACT make sure the following limits are maintained: 2.048 MHz < FXTI < 49.152 MHz 2.048 MHz < FINFIN < 16.384 MHz 65.536 MHz < FVCO < 98.304 MHz There are also some additional constraints on IDF and LDF. IDF should be greater than 0, LDF should be greater than 5 if FRAC_CTRL = 0 and greater than 8 if FRAC_CTRL = 1. When automatic settings are not used, the PLL must be configured to generate an internal frequency of N * Fs, where Fs is the LRCLKI pin frequency. Values of N are given in Table 12. Table 12. Oversampling table
Fs (kHz) 8 11.025 12 16 22.05 24 32 44.1 48 64 88.2 96 128 176.4 192 N 4096 4096 4096 2048 2048 2048 1024 1024 1024 512 512 512 256 256 256 FPHI (MHz) 32.768 45.1584 49.152 32.768 45.1584 49.152 32.768 45.1584 49.152 32.768 45.1584 49.152 32.768 45.1584 49.152
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STA529
PLL
Example 1:
FXTI = 13 MHz Fs = 44.1 kHz IDF should be equal to 3 otherwise LDF become less than 8 (FRAC_CTRL must be 1): LDF = floor(45.1584/(13/IDF)) = 10 FRACT = round([(45.1584/(13/ IDF))-floor(45.1584/(13/ IDF))]*216) = 27602 (where: floor: rounded towards zero round: rounded real number to nearest integer) Using the above configuration, the system clock is 45.15841675 MHz, the approximate static error is 16 Hz (that is, 0.5 ppm).
Example 2:
FXTI = 19.2 MHz Fs = 48 kHz IDF should be equal to 4 otherwise LDF become less than 8 (FRAC_CTRL must be 1): LDF = floor(49.152/(19.2/IDF)) = 10 FRACT = round([(49.152/(19.2/IDF))-floor(49.152/(19.2/IDF))]*216) = 15728 Using the above configuration, the system clock is 49.151953125 MHz, the approximate static error is 47 Hz (that is, 1 ppm).
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ADC
STA529
6
ADC
This section describes the analog-to-digital converter (ADC).
6.1
Functional description
The STA529 analog input is provided through a low power, low voltage, stereo audio analogto-digital converter front-end designed for audio applications. It includes a programmable gain amplifier, anti-aliasing filter, low-noise microphone biasing circuit, a third-order MASH2-1 delta-sigma modulator, digital decimating filter, and a first-order DC-removal filter. This device is fabricated using a 0.18 m CMOS process, where high-speed precision analog circuits are combined with high-density logic circuits. The ADC works in a microphone input (mic-in) mode and in a line-input mode. If the line input mode is selected, the ADC is configured in stereo and all conversion channels are active. If the microphone input mode is selected, the ADC is configured in mono. The mono channel is routed through the left conversion path, and the right conversion path is kept in power-down mode to minimize power consumption. A programmable gain amplifier (PGA) is available in mic-in mode, giving the possibility to amplify the signal from 0 to +42 dB in steps of 6 dB.
6.1.1
Digital filter characteristics
The digital filter characteristics are shown in Table 13. Table 13. Digital filter characteristics
Parameter Passband Passband ripple: Fs mode Fs_by_2 mode Fs_by_4 mode Stop band attenuation: Fs mode Fs_by_2 mode Fs_by_4 mode Group delay: Fs mode Fs_by_2 mode Fs_by_4 mode Typical 0.4535 * Fs 0.08 at 44.1 kHz 0.08 at 22.05 kHz 0.08 at 11.025 kHz 45 at 44.1 kHz 45 at 22.05 kHz 45 at 11.025 kHz 0.4 at 32 kHz 0.7 at 16 kHz 1.4 at 8 kHz Unit kHz dB dB dB dB dB dB ms ms ms
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STA529
A DC
6.1.2
High-pass filter characteristics
Table 14. High-pass filter characteristics
Parameter Frequency response: -3 dB -0.08 dB Phase deviation at 20 Hz Passband ripple Typical Unit
7 50 19.35 0.08
Hz Hz degree dB
6.1.3
Programmable gain amplifier
The programmable gain amplifier (PGA) is available in mic-in mode only. It is possible to amplify the input signal from 0 to 42 db in steps of 6 db. The setting is done through PGA bits of the ADCCFG register (see ADCCFG on page 49 for details). See Table 9 on page 14 for performance values.
6.2
Application scheme
Figure 6 shows the filter circuit. Figure 6. Block diagram
C9 AC coupled DC coupled C0 AC coupled DC coupled 1.8 V supply VSSA R1 VHI VSSA C6 C2 VLO VCM C7 C3 R1 = 500 C8 = 10 F C9, C0 = 1 F 3 V, 3 A must be a low-noise supply and separate from other supplies C5 C1 AGND VSSA plane must be different from other ground plane AVDD INR INL C1, C2, C3, C4 = 10 nF (These capacitors must be placed very close to their respective pins) C5, C6, C7 = 33 F (Low ESR and ESL capacitors are recommended)
VBIAS C8 C4
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ADC
STA529
6.3
Configuration examples
The ADC sampling frequency can be selected from three values:
normal (from 32 kHz to 48 kHz) low (from 16 kHz to 24 kHz) very-low (from 8 kHz to 12 kHz)
The setting is done through register bits MISC.ADC_FS_RANGE (see MISC on page 50 for details). For all other settings, register ADCCFG is used (see ADCCFG on page 49 for details).
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STA529
Driver configuration
7
Driver configuration
A driver configuration is available that allows PWM commands to be used on an external power device. For this purpose, the output serial audio interface is disabled and the respective pins have an alternative name and new functionality, as shown in Table 15. Table 15. Pin functionality in driver-configuration mode
Pin Alternative pin name and functionality
BICLKO LRCLKO SDATAO CLKOUT POWERFAULT
PWM1A (external bridge PWM command for output 1A) PWM1B (external bridge PWM command for output 1B) PWM2A (external bridge PWM command for output 2A) PWM2B (external bridge PWM command for output 2B) EADP (external audio power-down signal)
The driver configuration is selected with two programmable registers PWMINT1 = 0x93 and PWMINT2 = 0x81 (see PWMINT1 on page 51 and PWMINT2 on page 51).
7.1
I2S bypass
A configuration is available which allows the bypassing of the I2S input signal straight to the I2S output signal. This configuration is set using two programmable registers PWMINT1 = 0x93 and PWMINT2 = 0x80 (see PWMINT1 on page 51 and PWMINT2 on page 51).
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Serial audio interface
STA529
8
Serial audio interface
This section includes information about the audio interface.
8.1
Specifications
The serial-to-parallel interface and the parallel-to-serial interface can have different sampling rates. The following terms are used in this section:
BICLK active edge: Pins SDATAI, SDATAO, LRCLKI, LRCLKO always change synchronously with BITCLK active edges. The active edge can be configured to a rising or falling edge via register programming. BICLK strobe edge: Pins SDATAI, SDATAO, LRCLKI, LRCLKO should be stable near BICLK strobe edges, the slave device is able to use strobe edges to latch serial data internally.
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STA529
Serial audio interface
8.2
Master mode
In this mode, pins BICLKI/BICLKO and pins LRCLKI/LRCLKO are configured as outputs. Figure 7.
BICLKI/ BICLKO tDL
Master mode
LRCLKI/ LRCLKO
tDDA SDATAO
SDATAI tDST tDHT
Table 16.
Master mode
Parameter Symbol tDL tDDA t DST tDHT Min 0 0 10 10 Typ Max 10 15 Unit ns ns ns ns
LRCLKI/LRCLKO propagation delay from BICLK active edge SDATAI propagation delay from BICLKI/O active edge Sdatao setup time to BICLKI/O strobing edge Sdatao hold time from BICLKI/O strobing edge
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Serial audio interface
STA529
8.3
Slave mode
In this mode, pins BICLKI/O and pins LRCLKI/O are configured as inputs. Figure 8.
BICLKI/ BICLKO tBCY LRCLKI/ LRCLKO tDS SDATAO tDH SDATAI tDD tLRH tLRSU
Slave mode
tBCH tBCL
Table 17.
Slave mode
Parameter Symbol tBCY t BCH tBCL tLRSU tLRH tD S tD H tD D Min 50 20 20 10 10 10 10 0 10 Typ Max Unit ns ns ns ns ns ns ns ns
BICLK cycle time BICLK pulse width high BICLK pulse width low LRCLKI/LRCLKO setup time to BICLK strobing edge LRCLKI/LRCLKO hold time to BICLK strobing edge SDATAO setup time to BICLK strobing edge SDATAO hold time to BICLK strobing edge SDATAI propagation delay from BICLK active edge
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STA529
Serial audio interface
8.4
Serial formats
Different audio formats are supported in both master and slave modes. Clock and data configurations can be customized to match most of the serial audio protocols available on the market. Data length can be customized for 8-, 16-, 24-, and 32-bit. Figure 9. Right justified
LRCLKI/ LRCLKO
BICLKI/ BICLKO
SDATAI/ SDATAO
123
n-1 n
123
n-1 n
Figure 10. Left justified
LRCLKI/ LRCLKO
BICLKI/ BICLKO
SDATAI/ SDATAO
123
n-1 n
123
n -1 n
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Serial audio interface
STA529
8.4.1
DSP
Figure 11. DSP
LRCLKI/ LRCLKO
BICLKI/ BICLKO Left SDATAI/ SDATAO
123
Right n -1 n 1 2 3 n-1 n
8.4.2
I2S
Figure 12. I2S
LRCLKI/ LRCLKO
BICLKI/ BICLKO
SDATAI/ SDATAO
123
n-1 n
123
n-1 n
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STA529
Serial audio interface
8.4.3
PCM/IF (non-delayed mode)
MSB first 16-bit data
Figure 13. PCM/IF (non delayed mode)
Any width LRCLKI/ LRCLKO
BICLKI/ BICLKO
SDATAI/ SDATAO
123
n-1 n
8.4.4
PCM/IF (delayed mode)
MSB first 16-bit data
Figure 14. PCM/IF (delayed mode)
LRCLKI/ LRCLKO
BICLKI/ BICLKO
SDATAI/ SDATAO
123
n-1 n
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I2C interface
STA529
9
I2C interface
This section describes the communication protocol of the I2C interface.
9.1
Data transition and change
Data changes on the SDA line must only occur when the SCL clock is low. SDA transition while the clock is high is used to identify a start or stop condition.
9.2
Start condition
A start condition is identified by a high to low transition of the data bus SDA signal while the clock signal SCL is stable in the high state. A start condition must precede any command for data transfer.
9.3
Stop condition
A stop condition is identified by low to high transition of the data bus SDA signal while the clock signal SCL is stable in the high state. A stop condition terminates communication between the STA529 and the master bus.
9.4
Data input
During data input, the STA529 samples the SDA signal on the rising edge of clock SCL. For correct device operation the SDA signal must be stable during the rising edge of the clock and the data can change only when the SCL line is low.
9.5
Device addressing
To start communication between the master and the STA529, the master must initiate with a start condition. Following this, the master sends onto the SDA line 8 bits (MSB first) corresponding to the device select address and read or write mode. The 7 most significant bits are the device address identifiers, corresponding to the I2C bus definition. In the STA529, the I2C interface has the device address 0x34. The 8th bit (LSB) identifies read or write operation (R/W), this bit is set to 1 in read mode and 0 in write mode. After a start condition, the STA529 identifies on the bus the device address and if a match is found, it acknowledges the identification on SDA bus during the 9th bit time. The byte following the device identification byte is the internal space address.
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STA529
I2C interface
9.6
Write operation
Following the start condition the master sends a device select code with the R/W bit set to 0. The STA529 acknowledges this and the writes to the byte of the internal address. After receiving the internal byte address, the STA529 responds with an acknowledgement.
9.6.1
Byte write
In the byte-write mode the master sends one data byte. This is acknowledged by the STA529. The master then terminates the transfer by generating a stop condition.
9.6.2
Multi-byte write
The multi-byte write modes can start from any internal address. The master generates a stop condition which terminates the transfer.
9.7
9.7.1
Read operation
Current address byte read
Following the start condition the master sends a device select code with the R/W bit set to 1. The STA529 acknowledges this and then responds by sending one byte of data. The master then terminates the transfer by generating a stop condition.
9.7.2
Current address multi-byte read
The multi-byte read modes can start from any internal address. Sequential data bytes are read from sequential addresses within the STA529. The master acknowledges each data byte read and then generates a stop condition terminating the transfer.
9.7.3
Random address byte read
Following the start condition the master sends a device select code with the R/W bit set to 0. The STA529 acknowledges this and then the master writes the internal address byte. After receiving the internal byte address, the STA529 again responds with an acknowledgement. The master then initiates another start condition and sends the device select code with the R/W bit set to 1. The STA529 acknowledges this and then responds by sending one byte of data. The master then terminates the transfer by generating a stop condition.
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I2C interface
STA529
9.7.4
Random address multi-byte read
The multi-byte read modes could start from any internal address. Sequential data bytes are read from sequential addresses within the STA529. The master acknowledges each data byte read and then generates a stop condition terminating the transfer.
Figure 15. I2C write operations
ACK Byte Write ACK ACK
Star t
Dev address
R/W ACK
Sub address ACK
Data in ACK
Stop ACK Stop
Multibyte Write Star t
Dev address
R/W
Sub address
Data in
Data in
Figure 16. I2C read operations
ACK Current address read Star t No ACK
Dev address
R/W ACK
Data
Stop ACK ACK No ACK
Random address read Star t
Dev address
R/W
Sub address
Star t
Dev address
R/W
Data
Stop
ACK Sequential current read Star t
ACK
ACK
No ACK
Dev address
R/W=High
Data
Data
Data
Stop
ACK Sequential random read Star t
ACK
ACK
ACK
Dev address
R/W
Sub address
Star t
Dev address
R/W ACK
Data No ACK
Data
Data
Stop
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STA529
Registers
10
Registers
This section includes register information.
10.1
Table 18.
Address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x0A 0x0B 0x0C 0x0D 0x14 0x15 0x16 0x17 0x18 0x19 0x1E 0x1F 0x20 0x21 0x22 0x23 0x28
Summary
Register summary
Name FFXCFG0 FFXCFG1 MVOL LVOL RVOL TT F0 TT F1 TTP0 TTP1 S2PCFG0 S2PCFG1 P2SCFG0 P2SCFG1 PLLCFG0 PLLCFG1 PLLCFG2 PLLCFG3 PLLPFE PLLST ADCCFG CKOCFG MISC PADST0 PADST1 FFXST BISTRUN Reserved CLKOUT_ DIS OSC_DIS S TRB PLL_BYP_ UNL PLL_UNLO CK STRB_BYP ASS BICLK2PLL PLL_PWD_ STATE PGA[2:0] CLKOUT_SEL[1:0] P2P_FS_RANGE[2:0] ADC_FS_RANGE[1:0] Reserved Reserved INVALID_ INP_FBK MUTE_ INT_FBK BINSS_FBK P2P_IN_ ADC CORE_ CLKENBL PLL_PWDN PLL_BYP_ STATE INSEL S TBY BYPASS_ CALIB CLKENBL PFE1A BICLK_ STRB LRCLK_ LEFT SHARE_ BILR Bit 7 MUT E L1_R2 Bit 6 POW_STBY MUTE_ON_ INVALID Bit 5 SOFT_ VOL_ON Bi t 4 BIN_SO FTS TART Bit 3 Bit 2 Bit 1 Bi t 0
TIM_SOFT_VOL[3:0] PWM_SHIFT[1:0]
PWM_MODE[1:0]
SET_VOL_MASTER[7:0] SET_VOL_LEFT[7:0] SET_VOL_RIGHT[7:0] TIM_TS_FAULT[15:8] TIM_TS_FAULT[7:0] TIM_TS_POWUP[15:8] TIM_TS_POWUP[7:0] MSB_FIRST DATA_FORMAT[2:0] MAP_L[1:0] DATA_FORMAT[2:0] MAP_L[1:0] IDF[3:0] MASTER_ MODE
PDATA_LENGTH[1:0] BICLK_ STRB LRCLK_ LEFT
BICLK_OS[1:0] SDATAO_ ACT MSB_FIRST
MAP_R[1:0] MASTER_ MODE MAP_R[1:0]
PDATA_LENGTH[1:0] PLL_DIREC T_PROG FRAC_ CTRL
BICLK_OS[1:0] DITHER_DISABLE[1:0]
FRAC_INPUT[15:8] FRAC_INPUT[7:0] NDIV[5:0] PFE1B P FE2A PFE2B RESET_FA ULT
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Registers Table 18.
Address 0x29 0x2A 0x2B 0x2D 0x2E 0x32
STA529 Register summary (continued)
Name BISTST0 BISTST1 BISTST2 PWMINT1 PWMINT2 POWST POWER DOWN POW_ TRISTATE POW_ FAULT1A Bit 7 Bit 6 Bit 5 Bi t 4 Reserved Reserved Reserved PWM_INT[15:8] PWM_INT[7:0] POW_ FAULT1B POW_ FAULT2A POW_ FAULT2B Bit 3 Bit 2 Bit 1 Bi t 0
10.2
FFXCFG0
Bit 7 MU TE
General registers
FFX configuration register 0
B it 6 POW_STBY Bit 5 SOFT_VOL_ON Bit 4 BIN_ SOFTSTART B it 3 B it 2 Bit 1 B it 0 TIM_SOFT_VOL[3:0]
Address: Type: Buffer: Reset: Description:
0x00 R/W No 0x75
7 MUTE: 0: default 1: FFX output is zero 6 POW_STBY: 0: FFX bridge is in power-up mode 1: FFX bridge is put in standby mode (default) 5 SOFT_VOL_ON: 0: smooth transition not active 1: smooth transition when changing volume control (default) 4 BIN_SOFTSTART: Reserved (1: default) 3:0 TIM_SOFT_VOL: volume control time step for any 0.5 dB volume change Time is (2TIM_SOFT_VOL) * 20.83 s Default is 666.66 s
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STA529
Registers
FFXCFG1
Bit 7 L1_R2 B it 6 MUTE_ON_ INVALID Bit 5
Configuration register 1
Bit 4 B it 3 B it 2 Bit 1 B it 0 PWM_MODE[1:0] PWM_SHIFT[1:0]
Address: Type: Buffer: Reset: Description:
0x01 R/W No 0xf8
7 L1_R2: channel mapping: 0: right channel is mapped to output channel 1 and left channel is mapped to output channel 2 1: left channel is mapped to output channel 1 and right channel is mapped to output channel 2 (default) 6 MUTE_ON_ INVALID: mutes PWM outputs if invalid digital data is received: 0: outputs are not muted 1: outputs are muted (default) 5:4 PWM_MODE[1:0]: 00: binary (output B is opposite of output A) 01: binary headphones (output B is 50 % duty cycle) 10: ternary 11: phase shift (default) 3:2 PWM_SHIFT[1:0]: 10: default PWM period-shift between channels 1 and 2 Value is N * 90o Default is 180o 1:0 Reserved (00: default)
MVOL
Bit 7 B it 6 Bit 5
Master volume control register
Bit 4 B it 3 B it 2 Bit 1 B it 0 SET_VOL_MASTER[7:0]
Address: Type: Buffer: Reset: Description:
0x02 R/W No 0x00
7:0 SET_VOL_MASTER[7:0]: master volume control: From 0 dB to -127.5 dB in 0.5 dB steps
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Registers
STA529
LVOL
Bit 7 B it 6 Bit 5
Left channel volume control register
Bit 4 B it 3 B it 2 Bit 1 B it 0 SET_VOL_LEFT[7:0]
Address: Type: Buffer: Reset: Description:
0x03 R/W No 0x48
7:0 SET_VOL_LEFT[7:0]: left channel volume control: 0100 1000: default Left channel volume control (from +36 dB to -91.5 dB in 0.5 dB steps) Default value corresponds to 0 dB
RVOL
Bit 7 B it 6 Bit 5
Right channel volume control register
Bit 4 B it 3 B it 2 Bit 1 B it 0 SET_VOL_RIGHT[7:0]
Address: Type: Buffer: Reset: Description:
0x04 R/W No 0x48
7:0 SET_VOL_RIGHT[7:0]: right channel volume control: 0100 1000: default Right channel volume control (from +36 dB to -91.5 dB in 0.5 dB steps) Default value corresponds to 0 dB
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STA529
Registers
TTF0
Bit 7 B it 6 Bit 5
Tri-state time-after-fault register 0
Bit 4 B it 3 B it 2 Bit 1 B it 0 TIM_TS_FAULT[15:8]
Address: Type: Buffer: Reset: Description:
0x05 R/W No 0x00
7:0 MSBs of TIM_TS_FAULT[15:8]: See TTF1 on page 39.
TTF1
Bit 7 B it 6 Bit 5
Tri-state time-after-fault register 1
Bit 4 B it 3 B it 2 Bit 1 B it 0 TIM_TS_FAULT(7:0)
Address: Type: Buffer: Reset: Description:
0x06 R/W No 0x02
7:0 LSBs of TIM_TS_FAULT[7:0]: time in which power is held in tri-state mode after a fault signal: Time is TIM_TS_FAULT * 83.33 s. Default value corresponds to 166.66 s tri-state time after fault
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Registers
STA529
TTP0
Bit 7 B it 6 Bit 5
Tri-state time-after-power-up register 0
Bit 4 B it 3 B it 2 Bit 1 B it 0 TIM_TS_POWUP[15:8]
Address: Type: Buffer: Reset: Description:
0x07 R/W No 0x00
7:0 MSBs of TIM_TS_POWUP[15:8]: See register TTP1.
TTP1
Bit 7 B it 6 Bit 5
Tri-state time-after-power-up register 1
Bit 4 B it 3 B it 2 Bit 1 B it 0 TIM_TS_POWUP[7:0]
Address: Type: Buffer: Reset: Description:
0x08 R/W No 0x02
7:0 LSBs of TIM_TS_POWUP[7:0]: time in which power is held in tri-state mode after a powerup signal: Time is TIM_TS_POWUP * 83.33 s Default value corresponds to 166.66 s tri-state time after power-up
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STA529
Registers
S2PCFG0
Bit 7 BICLK_STRB B it 6 LRCLK_LEFT Bit 5 SHARE_BILR
Serial-to-parallel audio interface configuration register 0
Bit 4 MSB_FIRST B it 3 B it 2 DATA_FORMAT[2:0] Bit 1 B it 0 MASTER_ MODE
Address: Type: Buffer: Reset: Description:
0x0A R/W No 0xD2
7 BICLK_STRB: 0: bit clock strobe edge is falling edge, bit clock active edge is rising edge 1: bit clock strobe edge is rising edge, bit clock active edge is falling edge (default) 6 LRCLK_LEFT: 0: left/right clock is low for left channel, high for right channel 1: left/right clock is high for left channel, low for right channel (default) 5 SHARE_BILR: 0: default 1: left/right clock and bit clock are shared between serial-parallel interface and parallel-toserial interface, BICLKI and LRCLKI are used 4 MSB_FIRST: 0: LSB first 1: MSB first (default) 3:1 DATA_FORMAT[2:0]: serial interface protocol format: 000: left Justified 001: I2S (default) 010: right justified 100: PCM no delay 101: PCM delay 111: DSP 001: default 0 MASTER_MODE: 0: default 1: serial interface is in master mode
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Registers
STA529
S2PCFG1
Bit 7 B it 6 Bit 5
Serial-to-parallel audio interface configuration register 1
Bit 4 B it 3 MAP_L[1:0] B it 2 Bit 1 MAP_R[1:0] B it 0 BICLK_OS[1:0]
PDATA_LENGTH[1:0]
Address: Type: Buffer: Reset: Description:
0x0B R/W No 0x91
7:6 PDATA_LENGTH[1:0]: serial-to-parallel interface data length: 10: default Length is (N+1) * 8 bit Default is 24 bit 5:4 BICLK_OS[1:0]: bit clock oversampling: 01: default Value is (N+1) * 32 fs (where fs = sampling frequency) Default is 64 fs 3:2 MAP_L[1:0]: left data-mapping slot: 00: default Value is nth slot Default is slot0 1:0 MAP_R[1:0]: right data-mapping slot: 01: default Value is nth slot Default is slot
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STA529
Registers
P2SCFG0
Bit 7 BICLK_ STRB B it 6 LRCLK_LEFT Bit 5 SDATAO_ACT
Parallel-to-serial audio interface configuration register 0
Bit 4 MSB_FIRST B it 3 B it 2 DATA_FORMAT[2:0] Bit 1 B it 0 MASTER_ MODE
Address: Type: Buffer: Reset: Description:
0x0C R/W No 0xD3
7 BICLK_STRB: defines the bit clock edges: 0: strobe is falling edge, active edge is rising 1: strobe is rising edge, active edge is falling (default) 6 LRCLK_LEFT: defines the channel for the LR clock: 0: clock is low for left channel, high for right channel 1: clock is high for left channel, low for right channel (default) 5 SDATAO_ ACT: sets the behavior of pin SDATAO: 0: output is tri-stated when no data is sent (default) 1: output is never in tri-state (it is 0 when no data is sent) 4 MSB_FIRST: data alignment in the protocol for SDATAI and SDATAO: 0: LSB is the first bit 1: MSB is the first bit (default) 3:1 DATA_FORMAT[2:0]: serial interface protocol format: 000: left justified 001: I2S (default) 010: right justified 100: PCM no delay 101: PCM delay 111: DSP 0 MASTER_ MODE: selects serial interface master/slave mode: 0: slave 1: master (default)
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Registers
STA529
P2SCFG1
Bit 7 B it 6 Bit 5
Parallel-to-serial audio interface configuration register 1
Bit 4 B it 3 MAP_L[1:0] B it 2 Bit 1 MAP_R[1:0] B it 0 BICLK_OS[1:0]
PDATA_LENGTH[1:0]
Address: Type: Buffer: Reset: Description:
0x0D R/W No 0x91
7:6 PDATA_LENGTH[1:0]: serial-to-parallel interface data length: 10: default Length is (PDATA_LENGTH+1) * 8 bit Default is 24 bits 5:4 BICLK_OS[1:0]: bit clock oversampling: 01: default Value is (BICLK_OS+1) * 32 fs Default is 64 fs 3:2 MAP_L[1:0]: left data-mapping slot: 00: default Value is nth slot Default is slot0 1:0 MAP_R[1:0]: right channel data-mapping slot: 01: default Value is nth slot Default is slot1
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STA529
Registers
PLLCFG0
Bit 7 PLL_DIRECT_ PROG B it 6 FRAC_CTRL Bit 5
PLL configuration register 0
Bit 4 B it 3 B it 2 IDF[3:0] Bit 1 B it 0 DITHER_DISABLE[1:0]
Address: Type: Buffer: Reset: Description:
0x14 R/W No 0x00
7 PLL_DIRECT_PROG: PLL programming: 0: default 1: PLL is programmed according to the PLLCFG register settings 6 FRAC_CTRL: 0: default 1: PLL fractional-frequency synthesis is enabled 5:4 DITHER_DISABLE[1:0]: 00: default MSB = 1: disables rectangular PDF dither input to SDM LSB = 1: disables triangular PDF dither input to SDM 3:0 IDF[3:0]: PLL input division factor: 0000: IDF = 1 (default) 0001: IDF = 1 0010: IDF = 2 ... 1111: IDF = 15
PLLCFG1
Bit 7 B it 6 Bit 5
PLL configuration register 1
Bit 4 B it 3 B it 2 Bit 1 B it 0 FRAC_INPUT[15:8]
Address: Type: Buffer: Reset: Description:
0x15 R/W No 0x00
7:0 FRAC_INPUT[15:8]: 16 bits are used to set the fractional part of PLL multiplication factor: 0000 0000: default
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Registers
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PLLCFG2
Bit 7 B it 6 Bit 5
PLL configuration register 2
Bit 4 B it 3 B it 2 Bit 1 B it 0 FRAC_INPUT[7:0]
Address: Type: Buffer: Reset: Description:
0x16 R/W No 0x00
7:0 FRAC_INPUT[7:0]: 16 bits are used to set the fractional part of PLL multiplication factor: 0000 0000: default
PLLCFG3
Bit 7 STRB B it 6 STRB_BYPASS Bit 5
PLL configuration register 3
Bit 4 B it 3 NDIV[5:0] B it 2 Bit 1 B it 0
Address: Type: Buffer: Reset: Description:
0x17 R/W No 0x00
7 STRB: asynchronous strobe input to the fractional controller: 0: default 6 STRB_BYPASS: standby bypass: 0: STRB signal is not bypassed (default) 1: STRB signal is bypassed 5:0 NDIV[5:0]: PLL multiplication factor (integral part) named as loop division factor: 0000 XX: LDF = NA 0001 00: LDF = NA 0001 01: LDF = 5 ... 1101 11: LDF = 55 111X XX: LDF = NA 0000 00: default
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Registers
PLLPFE
Bit 7 PLL_BYP_UNL B it 6 BICLK2PLL Bit 5 PLL_PWDN
PLL/POP-free configuration register
Bit 4 PFE1A B it 3 PFE1B B it 2 PFE2A Bit 1 PFE2B B it 0 RESET_FAULT
Address: Type: Buffer: Reset: Description:
0x18 R/W No 0x00
7 PLL_BYP_UNL: PLL bypass: 0: PLL is not bypassed (default) 1: PLL is bypassed when not locked 6 BICLK2PLL: 0: default 1: BICLKI is input to PLL 5 PLL_PWDN: 0: default 1: PLL is put in power-down mode 4 PFE1A: 0: default 1: POP-free resistances are connected to output 1A 3 PFE1B: 0: default 1: POP-free resistances are connected to output 1B 2 PFE2A: 0: default 1: POP-free resistances are connected to output 2A 1 PFE2B: 0: default 1: POP-free resistances are connected to output 2B 0 RESET_FAULT: 0: default 1: fault signal in the i2c register POWST is reset
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Registers
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PLLST
Bit 7 PLL_UNLOCK B it 6 PLL_PWD_ STATE Bit 5 PLL_BYP_ STATE
PLL status register (RO)
Bit 4 B it 3 B it 2 Bit 1 B it 0
Address: Type: Buffer: Reset: Description:
0x19 RO No Undefined
7 PLL_UNLOCK: PLL unlock state: 0: PLL is not in unlock state 1: PLL is in unlock state 6 PLL_PWD_ STATE: PLL power-down state: 0: PLL is not in power-down state 1: PLL is in power-down state 5 PLL_BYP_STATE: PLL bypass state: 0: PLL is not in bypass state 1: PLL is in bypass state 4:0 Reserved
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Registers
ADCCFG
Bit 7 B it 6 PGA[2:0] Bit 5
ADC configuration register
Bit 4 INSEL B it 3 STBY B it 2 BYPASS_CALIB Bit 1 CLKENBL B it 0
Address: Type: Buffer: Reset: Description:
0x1E RO No Undefined
7:5 PGA[2:0]: gain selection bits for the ADC programmable gain amplifier: 000: default Values are from 0 to 42 dB in 6 dB steps 4 INSEL: 0: line input selected (default) 1: microphone input selected (it must be applied to INL line) 3 STBY: ADC standby mode: 0: ADC in power-up mode (default) 1: ADC in standby mode 2 BYPASS_CALIB: 0: ADC DC-removal block not bypassed (default) 1: ADC DC-removal block bypassed 1 CLKENBL: Clock enable: 0: system clock not enabled 1: system clock available at ADC input (default) 0 Reserved
CKOCFG
Bit 7 CLKOUT_DIS B it 6 Bit 5 CLKOUT_SEL[1:]]
Clock-out configuration register
Bit 4 B it 3 B it 2 Bit 1 B it 0
Address: Type: Buffer: Reset: Description:
0x1F R/W No Undefined
7 CLKOUT_DIS: CLKOUT PAD disabled 0: default 1: enabled 6:5 CLKOUT_SEL[1:0]: 00: default The CLKOUT output frequency is the PLL output frequency divided by 2CLKOUT_SEL. 4:0 Reserved
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Registers
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MISC
Bit 7 OSC_DIS B it 6 Bit 5
Miscellaneous configuration register
Bit 4 B it 3 B it 2 Bit 1 P2P_IN_ADC B it 0 CORE_ CLKENBL P2P_FS_RANGE[2:0] ADC_FS_RANGE[1:0]
Address: Type: Buffer: Reset: Description:
0x20 R/W No 0x21
7 OSC_DIS: enable/disable crystal oscillator: 0: default 1: disabled 6:4 P2P_FS_RANGE[2:0]: FFX audio frequency range: 000: very low (fs = 8 to 12 kHz) (default) 001: low (fs = 16 to 24 kHz) (default) 010: normal (fs = 32 to 48 kHz) 011: high (fs = 64 to 96 kHz) 1X: very high (fs = 128 to 192 kHz) 3:2 ADC_FS_RANGE[2:0]: ADC audio frequency range: 00: normal (fs = 32 to 48 kHz) 00: low (fs = 16 to 24 kHz) 1X: very low (fs = 8 to 12 kHz) 00: default 1 P2P_IN_ADC: FFX input: 0: FFX input is from serial-to-parallel audio interface (default) 1: FFX input is from ADC 0 CORE_CLKENBL: availability of system clock: 0: FFX system clock disabled 1: FFX system clock enabled (default)
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STA529
Registers
FFXST
Bit 7 B it 6 Bit 5
FFX status register
Bit 4 B it 3 B it 2 INVALID_INP_ FBK Bit 1 MUTE_INT_FBK B it 0
Address: Type: Buffer: Reset: Description:
0x23 RO No Undefined
7:3 Reserved 2 INVALID_INP_FBK: invalid input status: 1: invalid input sent to FFX 1 MUTE_INT_FBK: FFX mute status 1: FFX is in mute state 0 Reserved
PWMINT1
Bit 7 B it 6 Bit 5
PWM driver configuration register 1
Bit 4 B it 3 B it 2 Bit 1 B it 0 PWM_INT1[7:0]
Address: Type: Buffer: Reset: Description:
0x2D R/W No 0x00
7:0 PWM_INT1[7:0]: see Section 7: Driver configuration on page 25: 0000 0000: default
PWMINT2
Bit 7 B it 6 Bit 5
PWM driver configuration register 2
Bit 4 B it 3 B it 2 Bit 1 B it 0 PWM_INT1[7:0]
Address: Type: Buffer: Reset: Description:
0x2E R/W No 0x00
7:0 PWM_INT1[7:0]: see Section 7: Driver configuration on page 25: 0000 0000: default
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Registers
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POWST
Bit 7 POW_ POWERDOWN B it 6 POW_ TRISTATE Bit 5 POW_FAULT1A
Power bridge status register
Bit 4 POW_FAULT1B B it 3 POW_FAULT2A B it 2 POW_FAULT2B Bit 1 B it 0
Address: Type: Buffer: Reset: Description:
0x32 RO No Undefined
7 POW_POWERDOWN: power-down bridge: 0: not in power-down state 1: power-down state 6 POW_TRISTATE: 1: power bridge is in tri-state 5 POW_FAULT1A: 1: power bridge 1A is in fault state 4 POW_FAULT1B: 1: power bridge 1B is in fault state 3 POW_FAULT2A: 1: power bridge 2A is in fault state 2 POW_FAULT2B: 1: power bridge 2B is in fault state 1:0 Reserved
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Package information
11
Package information
This section includes packaging information for the following packages:
TFBGA48 VFQFPN 52
In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These package have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
11.1
Package TFBGA48
Figure 17. Mechanical data (TFBGA48)
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Package information Table 19 gives the package dimensions. Table 19. Package dimensions (TFBGA48)
Databook mm Reference A A1 A2 A3 A4 b D D1 E E1 e F ddd eee fff 4.85 0.25 4.85 0.30 5.00 3.50 5.00 3.50 0.50 0.75 0.08 0.15 0.05 5.15 0.15 0.785 0.20 0.60 0.35 5.15 Min Typical Max 1.20
STA529
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Package information
11.2
Package VFQFPN52
Figure 18. Mechanical data (VFQFPN52)
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Package information Table 20 gives the package dimensions. Table 20. Package dimensions (VFQFPN52)
Databook mm Reference A A1 A2 A3 b D D2 E E2 e L ddd 0.180 7.875 2.750 7.875 2.750 0.450 0.350 Min 0.800 Typical 0.900 0.020 0.650 0.250 0.230 8.000 5.700 8.000 5.700 0.500 0.550 0.300 8.125 6.250 8.125 6.250 0.550 0.750 0.080 Max 1.000 0.050 1.000
STA529
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Revision history
12
Revision history
Table 21.
Date 10-Jan-2007
Document revision history
Revision 1 Initial release Changes
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