STCF03
High power white LED driver with I²C interface
Features
Buck-boost dc/dc converter Drives one power white LED up to 800 mA from 2.7 V to 5.5 V in QFN Drives one power white LED up to 800 mA from 3.3 V to 5.5 V in BGA Efficient up to 92% Output current control 1.8 MHz typ. fixed frequency PWM Synchronous rectification Full I²C control Operational modes: Shutdown mode Shutdown + NTC Ready mode + auxiliary red LED Flash mode: up to 800 mA Torch mode: up to 200 mA Soft and hard triggering of flash Flash and torch dimming with 16 exponential values Dimmable red LED indicator auxiliary output Internally or externally timed flash operation Digitally programmable safety time-out in flash mode LED overtemperature detection and protection with external NTC resistor Opened and shorted LED failure detection and protection Chip over temperature detection and protection < 1 A shutdown current Device summary
Order code STCF03PNR STCF03TBR
(1)
QFN20 (4x4)
TFBGA25 (3x3)
Packages: QFN20 (4x4) TFBGA25 (3x3)
Applications
Cell phone and smart phone Camera flashes/strobe PDAs and digital still cameras
Description
The STCF03 is a high efficiency power supply solution to drive a single flash LED in camera phone, PDAs and other hand-held devices. It is a buck - boost converter to guarantee a proper LED current control over all possible conditions of battery voltage and output voltage; the output current control ensure a good current regulation over the forward voltage spread characteristics of the flash LED. Thanks to the high efficiency of the converter allows having the input current taken from the battery remain under 1.5 A. (See 1: Description (continued))
Table 1.
Package QFN20 (4x4 mm) TFBGA25 (3x3 mm)
Packaging 4500 parts per reel 3000 parts per reel
1. Available on request.
September 2008
Rev 5
1/35
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Contents
STCF03
Contents
1 2 3 4 5 6 7 Description (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7.1 7.2 Buck-Boost converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Logic pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 SCL, SDA pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 TRIG pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 ATN pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 ADD pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 TMSK pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12
I²C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Star t and stop conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Writing to a single register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Writing to multiple registers with incremental addressing . . . . . . . . . . . . 18 Reading from a single register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Reading from multiple registers with incremental addressing . . . . . . . . . 19
8
Description of internal registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
8.1 8.2 PWR_ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 TRIG_EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
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Contents
STCF03
8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 8.12 8.13 8.14 8.15
TCH_ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 NTC_ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 FTIM_0~3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 TDIM_0~3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 FDIM_0~3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 AUXI_0~3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 AUXT_0~3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 F_RUN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 LED_F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 NTC_W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 NTC_H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 OT_F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 VOUTOK_N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
9
Detailed description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
9.1 9.2 9.3 9.4 9.5 9.6 9.7 PowerON reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Shutdown, shutdown with NTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Ready mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Single or multiple Flash using external (P) temporization . . . . . . . . . . . 25 External (P) temporization using TRIG_EN bit . . . . . . . . . . . . . . . . . . . . 26 Single Flash using internal temporization . . . . . . . . . . . . . . . . . . . . . . . . 26 Multiple Flash using internal temporization . . . . . . . . . . . . . . . . . . . . . . . 26
10 11 12
Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
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List of tables
STCF03
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Absolute maximum ratings (see Note:). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 List of external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Address table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 I²C register mapping function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Command register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Dimming register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Auxiliary register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Auxiliary LED dimming table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Torch mode and Flash mode dimming registers settings . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Status register details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
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List of figures
STCF03
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin connections (bottom view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Procedure for assigning a non-default I²C address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Data validity on the I²C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Timing diagram on I²C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Acknowledge on I²C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Writing to a single register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Writing to multiple register with incremental addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Reading from a single register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Reading from multiple registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Flash and Torch current vs. dimming value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 VOUTOK_N behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 IOTORCH vs T_DIMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 IOFLASH vs F_DIMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 IOAUX vs AUXI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 IOFLASH vs Temp. VI = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 VFB2 vs Temp. at IO = 800 mA, VI = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 IQ vs Temp. VI = 5.5 V ready-mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Start-up in Flash mode 800 mA at VI = 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Line transient in Flash mode 800 mA, change of VI from 2.7 V to 3.3 V in 10 s. . . . . . . . 28
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Description (continued)
STCF03
1
Description (continued)
All the functions of the device are controlled through the I²C which helps bus that allows to reduce logic pins on the package and to save PCB tracks on the board. Hard and softtriggering of flash are both supported. The device includes many functions to protect the chip and the power LED such as: a soft start control, chip over temperature detection and protection as well as opened and shorted LED detection and protection. Besides, a digital programmable time out function protects the LED in case of a wrong command from the P. An optional external NTC resistor is supported to protect the LED against over heating. In mobile phone applications it is possible to reduce immediately the flash LED current during the signal transmission using the TMSK pin. This saves battery life and gives more priority to supply RF transmission instead of flash function. It is possible by I²C to separately program the current intensity in flash and torch mode using exponential steps. An auxiliary output can control an optional red LED to be used as a recording indicator. The device is packaged in QFN 4x4 20L with a height less than 1 mm and in TFBGA25 3x3.
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Diagram
STCF03
2
Figure 1.
Diagram
Block diagram
7/35
Pin configuration
STCF03
3
Figure 2.
Pin configuration
Pin connections (bottom view)
QFN20 (3x3)
TFBGA25 (3x3)
Table 2.
Pin n for QFN20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Exposed pad
Pin description
Pin n for TFBGA25 E1, D2 B3 A4 D1, C2 B5 A5 B4 E2 D4 D5 C5 B1, C1 A3 A2 A1, B2 E5 E3 C3, D3 E4 C4 Symbol VLX2 RX NTC VOUT FB1 FB2 FB2S GND ADD AUXL TMSK PVBAT VBAT VLX1A VLX1B SCL SDA PGND ATN TRIG PGND Inductor connection Rx resistor connection NTC resistor connection Output voltage Feedback pin [ILED*(RFL+RTR)] RTR bypass Feedback sensing pin [ILED*RFL] Signal ground I²C address selection Auxiliary LED output TX mask input. Power supply voltage Supply voltage Inductor connection Inductor connection I²C clock signal I²C data Power ground Attention (open drain output, active LOW) Flash trigger input To be connected to the PCB ground plane for optimal electrical and thermal performance Name and function
8/35
Maximum ratings
STCF03
4
Table 3.
Maximum ratings
Absolute maximum ratings (see Note:)
Parameter Signal supply voltage Power supply voltage Inductor connection 1 Inductor connection 2 Output voltage Auxiliary LED Feedback and sense voltage Logic Pin Connection for reference resistor Connection for LED Temperature sensing Human body model
(1)
Symbol VBAT PVBAT VLX1A, VLX1B VLX2 VOUT AUXL FB1, FB2, FB2S SCL, SDA, TRIG, ATN, ADD TMSK RX NTC ESD PTOT (BGA) TOP TJ TSTG
Value -0.3 to 6 -0.3 to 6 0.3 to VI+0.3 0.3 to VO+0.3 -0.3 to 6 0.3 to VI+0.3 -0.3 to 3 -0.3 to VI+0.3 -0.3 to 3 -0.3 to 3 2 800 -40 to 85 -40 to 150 -65 to 150
Unit V V V V V V V V V V kV mW C C C
Continuous power dissipation (at TA=70C) Operating junction temperature range Junction temperature Storage temperature range
1. Power dissipation is related parameter to used PCB. The recommended PCB design is included in the application note.
Note:
Absolute maximum ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied. Thermal data
Parameter Thermal resistance junction-ambient QFN20 59 TFBGA25 150 Unit C/W
Table 4.
Symbol RthJA
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Application
STCF03
5
Figure 3.
Application
Application schematic
**: Connect to VI, or GND or SDA or SCL to choose one of the 4 different I²C Slave Addresses. ***: Optional components to support auxiliary functions.
Table 5.
List of external components
Manufacturer TDK TDK TDK TDK Murata Part number X5R0J106M X5R0J105M VLF3012ST-4R7MR91 VLF4012AT-4R7M1R1 NCP21WF104J03RA Value 10 F 1 F 4.7 H 4.7 H 100 k 0.27 1.8 15 k Size 0603 0603 2.6 x 2.8 x 1.2 mm 3.7 x 3.5 x 1.2 mm 0805 0603 0402 0402
Component CI CO L (IFLASH = 0.5A) L (IFLASH = 0.8A) NTC RFL RTR RX
Note:
All of the above listed components refer to typical application. Operation of the STCF03 is not limited to the choice of these external components.
10/35
Electrical characteristics
ST C F 0 3
6
Table 6.
Electrical characteristics
Electrical characteristics (TJ = 25C, VI = 3.6 V, 2xCI = 10 F, CO = 1 F, L = 4.7 H, RFL = 0.27 RTR = 1.8 , RX = 15 k, Typ. values @25C, unless otherwise specified).
Parameter Input operation supply voltage Power ON reset threshold VI rising Flash mode for VI = 2.7 V to 5.5 V (STCF03PNR) Output current adjustment range IFLASH IO Output current adjustment range ITORCH Auxiliary LED output current adjustment range IAUXLED VO FB1 FB2 I O RON_ Regulated voltage range Feedback voltage Feedback voltage Output current tolerance FB1-FB2 ON resistance Quiescent current in SHUTDOWN mode IQ Quiescent current in ready mode fs Frequency Efficiency of the chip itself VI = 2.7 V VI = 3.2 to 4.2 V, flash mode, IO = 800 mA VI = 3.2 to 4.2 V, flash mode, IO = 800 mA, VO=VfLED_max + VFB2 = 5.02 V See the typical application schematic It is included losses of inductor and sensing resistor 5.3 0.3 140 20 25 Torch mode Flash mode Flash mode, IO = 160 mV/RFL Torch mode, IO = 200 mA NTC_ON=0 NTC_ON=1 Flash mode for VI = 2.7 V to 3.3 V (STCF03TBR) Flash mode for VI=3.3 V to 5.5 V (STCF03TBR) Torch mode VI = 2.7 V to 5.5 V Ready mode, VI = 3.3 V to 5.5 V 60 60 60 15 0 2.5 30 30 -10 90 1 A 1 1.8 1.8 87 mA MHz Test condition Min. 2.7 2.3 800 600 800 200 20 5.3 250 250 10 V mV mV % m mA Typ. Ma x . 5.5 Unit V V
Symbol VI VPW_ON
RESET
% 76
Efficiency of the whole application
OVP OVHYST OTP OTHYST RONT1
Output over voltage protection VI = 5.5 V, No Load Over voltage hysteresis Over temperature protection Over temperature hysteresis VI = 5.5 V, No Load VI = 5.5 V VI = 5.5 V
V V C C
RX-NTC switch ON resistance Ready mode
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Electrical characteristics Table 6.
ST C F 0 3
Electrical characteristics (continued) (TJ = 25C, VI = 3.6 V, 2xCI = 10 F, CO = 1 F, L = 4.7 H, RFL = 0.27 RTR = 1.8 , RX = 15 k, Typ. values @25C, unless otherwise specified).
Parameter Test condition Shutdown mode, VNTC = 2 V VRX = GND IOL = 10 mA VOZ = 3.3 V VI = 2.7 V to 5.5 V 0 1.4 Min. Typ. Ma x . 1 0.2 1 0.4 3 2 ms Unit A V mA V
Symbol
NTCLEAK RX-NTC switch OFF leakage VOL IOZ VIL VIH TON Output logic signal level low ATN Output logic leakage current ATN Input logic signal level SCL, SDA, TRIG, TEST, ADD LED current rise time ILED = 0 to ILED = max
Note:
Typical value, not production tested.
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Introduction
STCF03
7
Introduction
The STCF03 is a buck-boost converter, dedicated to power and control the current of a power white LED in a camera cell phone. The device operates at a constant switching frequency of 1.8 MHz typ. It provides an output voltage down to 2.5 V and up to 5.3 V, from a 2.7 V to 5.5 V supply voltage. This supply range allows operation from a single cell Lithium-Ion battery. The I²C bus is used to control the device operation and for diagnostic purposes. The current in torch mode is adjustable from 15 mA to 200 mA. Flash mode current is adjustable up to 800 mA, BGA version is able to deliver 600 mA at battery range 2.7 V to 3.3 V. The Aux LED current can be adjusted from 0 to 20 mA. The device uses an external NTC resistor to sense the temperature of the white LED. These two last functions may not be needed in all applications, and in these cases the relevant external components can be omitted.
7.1
Buck-Boost converter
The regulation of the PWM controller is done by sensing the current of the LED through external sensing resistors (RFL and RTR, see application schematic). Depending on the forward voltage of the flash LED, the device automatically can change the operation mode between buck (step down) and boost (step up) mode. Three cases can occur: Boost region (VO > VBAT): this configuration is used in most of the cases, as the output voltage VO = VfLED + ILED x RFL) is higher than VBAT; Buck region (VO < VBAT); Buck / Boost region (VO ~ VBAT).
7.2
7.2.1
Logic pin description
SCL, SDA pins
These are the standard clock and data pins as defined in the I²C bus specification. External pull-up is required according to I²C bus specifications. The recommended maximum voltage of these signals should be 3.0 V.
7.2.2
TRIG pin
This input pin is internally AND-ed with the TRIG_EN bit to generate the internal signal that activates the flash operation. This gives to the user the possibility to accurately control the flash duration using a dedicated pin, avoiding the I²C bus latencies (hard-triggering). No internal pull-up nor pull-down is provided.
7.2.3
ATN pin
This output pin (open-drain, active LOW) is provided to better manage the information transfer from the STCF03 to the P. Because of the limitations of a single master I²C bus configuration, the P should regularly poll the STCF03 to verify if certain operations have been completed, or to check diagnostic information. Alternatively, the P can use the ATN pin to be advised that new data are available in the STAT_REG, thus avoiding continuous polling. Then the information can be read in the STAT_REG by a read operation via I²C that, besides, automatically resets the ATN pin. The STAT_REG bits affecting the ATN pin status are mapped in Table 16. No internal pull-up is provided.
13/35
Introduction
STCF03
7.2.4
ADD pin
With this pin it is possible to select one of the 4 possible I²C slave addresses. No internal pull-up nor pull-down is provided. The pin has to be connected either GND, VI, SCL or SDA to select the desired I²C slave address (see Table 6)
Table 7.
ADD pin GND VBAT SDAL SCL
Address table
A7 0 0 0 0 A6 1 1 1 1 A5 1 1 1 1 A4 0 0 0 0 A3 0 0 0 0 A2 0 0 1 1 A1 0 1 0 1 A0 R/W R/W R/W R/W
When ADD is connected to GND the I²C address is assigned automatically while in the other three configurations in which ADD pin is connected to VBAT or SDA or SCL, the following procedure must be activated in order that the right address is assigned. After applying VBAT to the chip, the VBAT voltage must be pulled down to GND for a time longer than 100 ms. After that time the right I²C address is assigned to the chip. This procedure must be repeated every time the VBAT voltage is disconnected (see Figure 4 below) Figure 4. Procedure for assigning a non-default I²C address
Address is assigned. The new I²C address can be used for SCL and SDA
VBAT
1 0 0m s
....
S T A R T DEVICE ADDRESS 7 bits W R I T E
SCL LINE
ADDRESS OF REGISTER
DATA
M S B
LRAM S/CS BWKB
LAM SCS BKB
SDA SDA LINE
S T O P
LA SC BK
7.2.5
TMSK pin
This pin can be used to implement the TX masking function. This function has effect only for flash current settings higher than 200 mA (bit FDIM_3 = 1). Under this condition, when this pin is pulled high by the P, the current flowing in the LED is forced at 200 mA typ. No internal pull-up nor pull-down is provided: to be externally wired to GND if TX masking function is not used.
14/35
Introduction
STCF03
7.3
I²C bus interface
Data transmission from the main P STCF03 and vice versa takes place through the 2 wires I²C bus interface wires, consisting of the two lines SDA and SCL (pull-up resistors to a positive supply voltage must be externally connected). The recommended maximum voltage of these signals should be 3.0 V.
7.4
Data validity
As shown in Figure 5, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW.
Figure 5.
Data validity on the I²C Bus
7.5
Start and stop conditions
Both DATA and CLOCK lines remain HIGH when the bus is not busy. As shown in Figure 6 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. A STOP condition must be sent before each START condition
Figure 6.
Timing diagram on I²C Bus
15/35
Introduction
STCF03
7.6
Byte format
Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first. One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse. Any change in the SDA line at this time will be interpreted as a control signal.
Figure 7.
Bit transfer
7.7
Acknowledge
The master (P) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see Figure 8). The peripheral (STCF03) that acknowledges has to pull-down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse. The peripheral which has been addressed has to generate an acknowledge pulse after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse duration. In this case the master transmitter can generate the STOP information in order to abort the transfer. The STCF03 won't generate the acknowledge if the VI supply is below the undervoltage lockout threshold.
Figure 8.
Acknowledge on I²C Bus
16/35
Introduction
STCF03
Table 8.
Interface protocol
Register address 7 6 5 4 3 2 1 0 L S B 7 AM CS KB 6 5 Data 4 3 2 1 0 L S B A C K S T O P
Device address + R/W bit 7 S TM AS RB T 6 5 4 3 2 1 0
L AM R S CS W B KB
7.8
Writing to a single register
Writing to a single register starts with a START bit followed by the 7 bit device address of STCF03. The 8th bit is the R/W bit, which is 0 in this case. R/W = 1 means a reading operation. Then the master waits for an acknowledge from STCF03. Then the 8 bit address of register is sent to STCF03. It is also followed by an acknowledge pulse. The last transmitted byte is the data that is going to be written to the register. It is again followed by an acknowledge pulse from STCF03. Then master generates a STOP bit and the communication is over. See Figure 9 below.
Figure 9.
Writing to a single register
DEVICE ADDRESS 7 bits W R I T E
ADDRESS OF REGISTER
DATA
SM TS AB R T
LRAM S/CS BWKB SDA LINE
LAM SCS BKB
LAS SCT BKO P
7.9
Interface protocol
The interface protocol is composed: A start condition (START) A Device address + R/W bit (read =1 / write =0) A Register address byte A sequence of data n* (1 byte + acknowledge) A stop condition (STOP)
17/35
Introduction
STCF03
The register address byte determines the first register in which the read or write operation takes place. When the read or write operation is finished, the register address is automatically increased.
7.10
Writing to multiple registers with incremental addressing
It would be unpractical to send several times the device address and the address of the register when writing to multiple registers. STCF03 supports writing to multiple registers with incremental addressing. When the data is written to a register, the address register is automatically increased, so the next data can be sent without sending the device address and the register address again. See Figure 10 below.
Figure 10. Writing to multiple register with incremental addressing
DEVICE ADDRESS 7 bits W R I T E
ADDRESS OF REGISTER i
DATA i
DATA i+1
DATA i+2
DATA i+2
DATA i+n
SM TS AB R T
LRAM S/CS BWKB
LAM SCS BKB
LAM SCS BKB
LAM SCS BKB
LAM SCS BKB
LAM SCS BKB
LAS SCT BKO P
SDA LINE
7.11
Reading from a single register
The reading operation starts with a START bit followed by the 7 bit device address of STCF03. The 8th bit is the R/W bit, which is 0 in this case. STCF03 confirms the receiving of the address + R/W bit by an acknowledge pulse. The address of the register which should be read is sent afterwards and confirmed again by an acknowledge pulse of STCF03 again. Then the master generates a START bit again and sends the device address followed by the R/W bit, which is 1 now. STCF03 confirms the receiving of the address + R/W bit by an acknowledge pulse and starts to send the data to the master. No acknowledge pulse from the master is required after receiving the data. Then the master generates a STOP bit to terminate the communication. See Figure 11
18/35
Introduction
STCF03
Figure 11. Reading from a single register
DEVICE ADDRESS 7 bits W R I T E ADDRESS OF REGISTER DEVICE ADDRESS 7 bits R E A D
DATA
SM TS AB R T
LRAM S/ CS B WK B
LAS SCT BKA R T
RA /C WK
L NS S OT O B AP C K
SDA LINE
7.12
Reading from multiple registers with incremental addressing
Reading from multiple registers starts in the same way like reading from a single register. As soon as the first register is read, the register address is automatically increased. If the master generates an acknowledge pulse after receiving the data from the first register, then reading of the next register can start immediately without sending the device address and the register address again. The last acknowledge pulse before the STOP bit is not required. See the Figure 12.
Figure 12. Reading from multiple registers
DEVICE ADDRESS 7 bits W R I T E DEVICE ADDRESS 7 bits R E A D
ADDRESS OF REGISTER i
DATA i
DATA i+1
DATA i+2
DATA i+2
DATA i+n
SM TS AB R T
LRAM S / CS B WK B
LAS SCT BKA R T
RA /C WK
LAM SCS BKB
LAM SCS BKB
LAM SCS BKB
LAM SCS BKB
LNS SOT B O AP C K
SDA LINE
19/35
Description of internal registers
S T CF 0 3
8
Table 9.
Description of internal registers
I²C register mapping function
Register name CMD_REG DIM_REG AUX_REG STAT_REG SUB ADDRESS (hex) 00 01 02 03 Operation R/W R/W R/W R only
Table 10.
Command register
MSB PWR_ON 0 TRIG_EN 0 TCH_ON 0 NTC_ON 0 FTIM_3 0 FTIM_2 0 FTIM_1 0 LSB FTIM_0 0
CMD_REG (write mode) SUB ADD=00 Power ON RESET Value
8.1
PWR_ON
When set, it activates all analog and power internal blocks including the NTC supporting circuit, and the device is ready to operate (ready mode). As long as PWR_ON=0, only the I²C interface is active, minimizing stand-by mode power consumption.
8.2
TRIG_EN
This bit is AND-ed with the TRIG pin to generate the internal signal FL_ON that activates flash mode. By this way, both soft-triggering and hard-triggering of the flash are made possible. If soft-triggering (through I²C) is chosen, the TRIG pin is not used and must be kept HIGH (VI). If hard-triggering is chosen, then the TRIG pin has to be connected to a P I/O devoted to flash timing control, and the TRIG_EN bit must be set in advance. Both triggering modes can benefit of the internal flash time counter, that uses the TRIG_EN bit and can work either as a safety shut-down timer or as a flash duration timer. Flash mode can start only if PWR_ON=1. LED current is controlled by the value set by the FDIM_0~3 of the DIM_REG.
8.3
TCH_ON
When set from ready mode, the STCF03 enters the torch mode. The LED current is controlled by the value set by the TDIM_0~3 of the DIM_REG.
8.4
NTC_ON
In ready mode, the comparators that monitor the LED temperature are activated if NTC_ON bit is set. NTC-related blocks are always active regardless of this bit in torch mode and flash mode.
20/35
Description of internal registers
S T CF 0 3
8.5
FTIM_0~3
This 4bit register defines the maximum flash duration. It is intended to limit the energy dissipated by the LED to a maximum safe value or to leave to the STCF03 the control of the flash duration during normal operation. Values from 0~15 correspond to 0~1.5 s (100 ms steps). The timing accuracy is related to the internal oscillator frequency that clocks the flash time counter (+/- 20 %). Entering flash mode (either by soft or hard triggering) activates the flash time counter, which begins counting down from the value loaded in the F_TIM register. When the counter reaches zero, flash mode is stopped by resetting TRIG_EN bit, and simultaneously the ATN pin is set to true (LOW) to alert the P that the maximum time has been reached. FTIM value remains unaltered at the end of the count.
Table 11.
Dimming register
MSB TDIM_3 0 TDIM_2 0 TDIM_1 0 TDIM_0 0 FDIM_3 0 FDIM_2 0 FDIM_1 0 LSB FDIM_0 0
DIM_REG (write mode) SUB ADD=01
Power ON, SHUTDOWN MODE RESET Value
8.6
TDIM_0~3
These 4 bits define the LED current in torch mode with 16 values fitting an exponential law. Max torch current value is 25% of max flash current. (Figure 13)
8.7
FDIM_0~3
These 4 bits define the LED current in flash mode with 16 values fitting an exponential law. The max value of the current is set by the external resistors RFL and RTR. (Figure 13)
Figure 13. Flash and Torch current vs. dimming value
Current Step Coefficient - 1.19
Note:
LED current values refer to RFL=0.27 , RTR=1.8
21/35
Description of internal registers
S T CF 0 3
Table 12.
Auxiliary register
MSB AUXI_3 0 AUXI_2 0 AUXI_1 0 AUXI_0 0 AUXT_3 0 AUXT_2 0 AUXT_1 0 LSB AUXT_0 0
AUX_REG (write mode) SUB ADD=02 Power ON, SHUTDOWN MODE RESET Value
8.8
AUXI_0~3
This 4 bits register defines the AUX LED current from 0 to 20 mA. See AUX LED dimming table for reference. Loading any value between 1 and 15 also starts the AUX LED current source timer, if enabled. The AUX LED current source is active only in Ready Mode, and is deactivated in any other mode.
8.9
AUXT_0~3
This 4 bit register controls the timer that defines the ON-time of the AUX LED current source. ON-time starts when the AUXI register is loaded with any value other than zero, and stops after the time defined in the AUXT register. Values from 1 to 14 of the AUXT register correspond to an ON-time of the AUX LED ranging from 100 to 1400 ms in 100 ms steps. The value 15 puts the AUX LED to the continuous light mode. The activation/deactivation of the AUX LED current source is controlled using only the AUXI register.
Table 13.
AUXI (hex)
Auxiliary LED dimming table (1)
0 0.0 1 1.3 2 2.6 3 4.0 4 5.3 5 6.6 6 8.0 7 9.3 8 9 A B C D E F
AUX LED current [mA]
10.6 12.0 13.3 14.6 16.0 17.3 18.6 20.0
1. 20 mA output current is achievable only if the supply voltage is higher than 3.3 V.
Table 14.
T_DI M (hex) F_DI M (hex) LED current [mA] Internal step V REF1 [mV] Sense Resist. 16 0
Torch mode and flash mode dimming registers settings
1 2 3 4 5 6 7 8 0 9 1 A 2 B 3 C 4 D 5 E 6 F 7 8 9 A B C D E F
19
23
27
32
39
46
55
65
77
92
109 124 147 175 209 248 296 352 418 498 592 705 840
1 33
2 40
3 47
4 56
5 67
6 80
7 95
8
9
10
11
12 227
13 33
14 40
15 47
16 56
17 67
18 79
19 95
20
21
22
23
24
113 134 160 190
113 134 160 190 227
RFL RFL RFL RFL RFL RFL RFL RFL RFL RFL RFL RFL + + + + + + + + + + + + RFL RFL RFL RFL RFL RFL RFL RFL RFL RFL RFL RFL RTR RTR RTR RTR RTR RTR RTR RTR RTR RTR RTR RTR
Note:
LED current values refer to RFL=0.27 , RTR=1.8 .
22/35
Description of internal registers
S T CF 0 3
Table 15.
Status register
MSB N/A 0 F_RUN 0 LED_F 0 NTC_W 0 NTC_H 0 OT_F 0 N/A 0 LSB VOUTOK_N 0
STAT_REG (read mode) SUB ADD=03 Power ON, SHUTDOWN MODE RESET Value
8.10
F_RUN
This bit is kept HIGH by the STCF03 during flash mode. By checking this bit, the P can verify if the flash mode is running or has been terminated by the time counter.
8.11
LED_F
This bit is set by the STCF03 when the voltage seen on the LED pin is VREF2 > 5.3 V during a torch or flash operation. This condition can be caused by an open LED, indicating a LED failure. The device automatically goes into ready mode to avoid damage. Internal high frequency filtering avoids false detections. This bit is reset by the STCF03 following a read operation of the STAT_REG.
8.12
NTC_W
This bit is set HIGH by the STCF03 and the ATN pin is pulled down, when the voltage seen on the pin Rx exceeds VREF4 = 0.56 V. This threshold corresponds to a warning temperature value at the LED measured by the NTC. The device is still operating, but a warning is sent to the P. This bit is reset by the STCF03 following a read operation of the STAT_REG.
8.13
NTC_H
This bit is set HIGH by the STCF03 and the ATN pin is pulled down, when the voltage seen on the pin Rx exceeds VREF5. This threshold (1.2V) corresponds to an excess temperature value at the LED measured by the NTC. The device is put in Ready mode to avoid damaging the LED. This bit is reset by the STCF03 following a read operation of the STAT_REG.
8.14
OT_F
This bit is set HIGH by the STCF03 and the ATN pin is pulled down, when the chip overtemperature protection (~140 C) has put the device in ready mode. This bit is reset by the STCF03 following a read operation of the STAT_REG.
23/35
Description of internal registers
S T CF 0 3
8.15
VOUTOK_N
This bit is set by the STCF03. It is used to protect the device, if the output is shorted. The VOUTOK_N bit is set to HIGH at the start-up. Then a current generator of 20 mA charges the output capacitor for 360 s typ. and it detects when the output capacitor reaches 100 mV. If this threshold is reached the bit is set to LOW. If the output is shorted to ground or the LED is shorted this threshold is never reached: the bit stays HIGH, ATN pin is pulled down and the device will not start. This bit is reset following a read operation of the STAT_REG.
Figure 14. VOUTOK_N behavior
Table 16.
Bit Name
Status register details
F_RUN LED_F (STAT_REG) (STAT_REG) 0 NO 0 YES NTC_W (STAT_REG) 0 YES NTC_H (STAT_REG) 0 YES OT_F (STAT_REG) 0 YES VOUTOK_N (STAT_REG) 0 YES
Default value Latched (1) Forces Ready mode when set Sets ATN LOW when set
NO
YES
NO
YES
YES
YES
NO
YES
YES
YES
YES
YES
1. YES means that the bit is set by internal signals and is reset to default by an I²C read operation of STAT_REG NO means that the bit is set and reset by internal signals in real-time.
24/35
Detailed description
STCF03
9
9.1
Detailed description
PowerON reset
This mode is initiated by applying a supply voltage above the VPW_ON RESET threshold value. An internal timing (~1 s) defines the duration of this status. The logic blocks are powered, but the device doesn't respond to any input. The registers are reset to their default values, the ATN and SDA pins are in high-Z, and the I²C slave address is internally set by reading the ADD pin configuration. After the internally defined time has elapsed, the STCF03 automatically enters the Stand-by mode.
9.2
Shutdown, shutdown with NTC
In this mode only the I²C interface is alive, accepting I²C commands and register settings. The device enters this mode: automatically from Power ON reset status; by resetting the PWR_ON bit from other operation modes. Power consumption is at the minimum (1 A max) if NTC is not activated (NTC_ON=0). If PWR_ON and NTC_ON is set, the T1 is switched ON (see the block diagram), allowing the P to measure the LED temperature through its A/D converter. When NTC circuits are active and the VREF-EXT is present, the typ. current consumption is increased to 1 A, then it is recommended not to leave the STCF03 in this status if battery drain has to be minimized.
9.3
Ready mode
In this mode all internal blocks are turned ON, but the DC/DC converter is disabled and the White LED is disconnected. The NTC circuit can be activated to monitor the temperature of the LED and I²C commands and register settings are allowed to be executed immediately. Only in this mode the auxiliary LED is operational and can be turned ON and set at the desired brightness using the AUX REGISTER. The device enters this mode: from Stand-by by setting the PWR_ON bit; from flash operation by resetting the TRIG pin or the TRIG_EN bit or automatically from flash operation when the time counter reaches zero; from torch operation by resetting the TCH_ON bit. The device automatically enters this mode also when an overload or an abnormal condition has been detected during flash or torch operation (Table 16: Status register details:).
9.4
Single or multiple Flash using external (P) temporization
To avoid the I²C bus time latency, it is recommended to use the dedicated TRIG pin to define the flash duration (hard-triggering). The TRIG_EN bit of CMD_REG should be set before starting each flash operation, because it could have been reset automatically in the previous flash operation. Flash duration is determined by the pulse length that drives the TRIG pin. As soon as the flash is activated, the system needs typically 1.2 ms to ramp up the output current on the power LED. The internal time counter will time-out flash operation and keep the LED dissipated energy within safe limits in case of software deadlock; FTIM register has to be set first, either in stand-by or in ready mode. Multiple flashes are possible by strobing the TRIG pin. Time out counter will cumulate every flash on-time until the defined time out is reached unless it is reloaded by updating the CMD_REG. If single or multiple flash operation is timed-out, the device automatically goes in Ready mode by resetting the
25/35
Detailed description
STCF03
TRIG_EN bit, and also resets the F_RUN bit. The ATN pin is pulled down to inform the P that the STAT_REG has been updated.
9.5
External (P) temporization using TRIG_EN bit
Even if it is possible, it is not recommended to use the TRIG_EN bit to start and stop the flash operation, because of I²C bus latencies: this would result in inaccurate flash timing. Nevertheless, if this operation mode is chosen, the TRIG pin has to be kept High (logic level or wired to VBAT), leaving the whole flash control to the I²C bus. Also in this operation mode the time counter will time-out flash operation and keep the LED dissipated energy dissipated by the LED within safe limits in case of SW deadlock.
9.6
Single Flash using internal temporization
Flash triggering can be obtained either by TRIG pin (hard-triggering) or by I²C commands (soft-triggering). The first solution is recommended for an accurate start time, while the second is less accurate because of the I²C bus time latency. Stop time is defined by the STCF03 internal temporization and its accuracy is determined by the internal oscillator. For hard-triggering it is necessary to set the TRIG_EN bit in advance. For soft-triggering the TRIG pin has to be kept High (logic level or wired to VBAT) and the flash can be started by setting the FTIM and the TRIG_EN through I²C (both are located in the CMD REG). There is a delay time between the moment the flash is triggered and when it appears. This delay is caused by the time necessary to charge up the output capacitor, which is around 1.2 ms depending on battery voltage and output current value. Once triggered, the flash operation will be stopped when the time counter reaches zero. As soon as the flash is finished, the F_RUN bit is reset, the ATN pin is pulled down for 11 s to inform the P that the STAT_REG has been updated and the device goes back to ready mode. If it is necessary to make a flash longer than the internal timer allows or a continuous flash, then the FTIM must be reloaded through I²C bus every time, before the internal timer reaches zero. For example: To get a continuous flash, set FTIM to 1.5 s and every 1 s reload the CMD_REG.
9.7
Multiple Flash using internal temporization
This operation has to be processed as a sequence of single flashes using internal temporization starting from hard or soft triggering. Since the TRIG_EN bit is reset at the end of each flash, it is necessary to reload the CMD_REG to start the next one.
26/35
Typical performance characteristics
STCF03
10
Typical performance characteristics
Figure 16. IOTORCH vs T_DIMM
Figure 15. Efficiency
Efficiency of the application at Io=800mA Efficiency of the application at Io=55mA
100 90 80 70 60 eff [%]
VI= 2.7V VI= 3.6V V I =5.5V 250 200 mA 150 100 50 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 step
2 2.5 3 3.5 4 VI [V] 4.5 5 5. 5 6
50 40 30 20 10 0
Figure 17. IOFLASH vs F_DIMM
VI 3.3V VI 5.5V 900 800 700 600 500 400 300 200 100 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 step
Figure 18. IOAUX vs AUXI
25 20 mA 15 10 5 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Step
Figure 19. IOFLASH vs Temp. VI = 3.3V
mA
Figure 20. VFB2 vs Temp. at IO = 800mA, VI = 3.3V
900 800 700 600 500 400 300 200 100 0 -40C 25C temp. 80C
26 0 24 0 22 0 20 0 18 0 16 0 14 0 12 0 10 0 -40C 25C temp. 80C
27/35
mA
mV
Typical performance characteristics
STCF03
Figure 21. IQ vs Temp. VI = 5.5 V ready-mode
Figure 22. Start-up in flash mode 800 mA at VI = 3.6 V
TRIG
3 2.5 2 mA 1.5 1 0.5 0 -40C 25C Temp. 85C
Io
I_IN
Figure 23. Line transient in flash mode 800 mA, change of VI from 2.7 V to 3.3 V in 10 s
Io
VI
I_IN
28/35
Package mechanical data
STCF03
11
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com
29/35
Package mechanical data
STCF03
QFN20 (4mm x 4mm) mechanical data
mm . Dim. Min. A A1 A2 A3 b D D1 D2 (A) D2 (B) D2 (C) E E1 E2 (A) E2 (B) E2 (C) e L P K ddd 0 .80 Typ. 0 .90 0.02 0.65 0.20 0.25 4.00 3.75 1.70 2 .10 2. 30 4.00 3.75 1.70 2 .10 2.30 0 .50 0 .55 Max. 1 .00 0.05 1.00 0. 3 0 4.15 1. 85 2.25 2 .45 4.15 1. 85 2.25 2 .45 0.75 0.60 14 0.08 Min. 31.5 Typ. 35.4 0.8 25.6 7.9 9. 8 157.5 147.6 66.9 82.7 90.6 157.5 147.6 66.9 82.7 90.6 19.7 21.7 Max. 39.4 2.0 39.4 11.8 163.4 72.8 88.6 96.5 163.4 72.8 88.6 96.5 29.5 23.6 551.2 3.1 mi l s .
0 . 18 3.85 1 .55 1 .95 2 .15 3.85 1 .55 1 .95 2.15 0 .35
7 .1 151.6 61.0 76.8 84.6 151.6 61.0 76.8 84.6 1 3.8
7366925A
30/35
Package mechanical data
STCF03
TFBGA25 mechanical data
mm . Dim. Min. A A1 A2 b D D1 E E1 e SE 2.9 0.78 0.25 2.9 0 .3 0 3.0 2 3.0 2 0.5 0.25 3.1 114.2 1.0 Typ. 1.1 Max. 1.16 0.25 0.86 0. 35 3.1 30.7 9 .8 114.2 11.8 118.1 78.8 118.1 78.8 19.7 9.8 122.0 Min. 39.4 Typ. 43.3 Max. 45.7 9.8 33.9 13.8 122.0 mi l s .
7539979/A
31/35
Package mechanical data
STCF03
Tape & reel QFNxx/DFNxx (4x4) mechanical data
mm. Dim. Min. A C D N T Ao Bo Ko Po P 4.35 4.35 1.1 4 8 12.8 20.2 99 101 14.4 0.171 0.171 0.043 0.157 0.315 Typ. Max. 330 13.2 0.504 0.795 3.898 3.976 0.567 Min. Typ. Max. 12.992 0.519 inch.
32/35
Package mechanical data
STCF03
Tape & reel TFBGA25 mechanical data
mm. Dim. Min. A C D N T Ao Bo Ko Po P 3.9 7.9 3.3 3.3 1.60 4.1 8.1 0.153 0.311 12.8 20.2 60 14.4 0.130 0.130 0.063 0.161 0.319 Typ. Max. 330 13.2 0.504 0.795 2 .362 0.567 Min. Typ. Max. 12.992 0.519 inch.
33/35
Revision history
STCF03
12
Table 17.
Date
Revision history
Document revision history
Revision 1 2 3 4 5 First Release. The OVP min. value on table 5 is changed: 5.5 V ==> 5.3 V. Modified Table 5. Modified Figure 2. Added Figure 4 on page 14. Changes
30-Jan-2007 27-Mar-2007 28-Aug-2007 12-Sep-2007 10-Sep-2008
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STCF03
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