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SPEAr" Head600

Datasheet

Format: (324 kb)

Last Updated: 04/08/2008

Pages: 40

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SPEAR-09-H122
SPEArTM Head600
Preliminary Data

Features

ARM926EJ-S core @333 MHz 600 Kbyte reconfigurable logic array with 88 dedicated general purposes I/Os, 9 LVDS channels and 128 Kbyte configurable internal memory pool Multilayer AMBA 2.0 compliant bus with fMAX 166 MHz 32 Kbyte ROM 8 Kbyte common static RAM Dynamic power saving features High performance 8 channels DMA Ethernet 10/100/1000 MAC with GMII/MII interface to external PHY USB2.0 device with integrated PHY 2 USB2.0 host with integrated PHY Ext. SDRAM memory interface: 8/16-bit (DDR1@200 MHz) 8/16-bit (DDR2@333 MHz) Flashes interface: Nand 8/16-bit Serial (up to 50 Mbps) 3-SPI master/slave up to 40 Mbps I2C master/slave mode - high, fast and slow speed 2 independent UART up to 460.8 Kbps with software flow control mode IrDA (Fir-Mir-Sir) from 9.6 Kbps to 4 Mbps speed-rate Colour LCD controller: up to 1024x768 resolutions 24 bpp true colour TFT panel Device summary
Order code SPEAR-09-H122 Package PBGA420(23x23x1.81mm) Packing Tray

PBGA420

16 bpp DSTN panel

10 GPIOs bidirectional signals with interrupt capability 88 RAS-GPIOs user customizable bidirectional signals (up to 4 clocks) ADC 10-bit, 1MSPS, 8 analog inputs JPEG codec accelerator 10 independent timers with programmable prescaler Real time clock WatchDog System controller MISC internal control registers JTAG (IEEE1149.1) interface

Description
SPEAr Head600 is a powerful digital engine belonging to SPEAr family, the innovative customizable system-on-chip. The device integrates an ARM 926 core with a large set of proven IPs and a big configurable logic block that allow very fast customization of unique and/or proprietary solution. The SPEAR-09-H122 is designed for the -40 to 85 C ambient temperature range.

Table 1.

July 2008

Rev 2

1/40
www.st.com 1

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

Contents

SPEA R-09-H122

Contents
Reference documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1 Product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1 1.2 1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Architecture properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1 2.2 Functional pin group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Special IOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.2.1 2.2.2 2.2.3 USB 2.0 transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 SSTL_2/SSTL_18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 LVDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3

Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.1 3.2 3.3 3.4 3.5 3.6 Main memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 ICM1 - low speed connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 ICM2 - application subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 ICM4 - high speed connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 ML1, 2 - multi layer CPU subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 ICM3 - basic subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4

Main blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.1 7.1 CPU subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.1.1 4.1.2 Over view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 CPU ARM 926EJ-S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.2 4.3

Clock and reset system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Main oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.3.1 4.3.2 Cr ystal connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Cr ystal equivalent model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.4

RTC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.4.1 4.4.2 RTC crystal connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 RTC crystal equivalent model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

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SPEAR-09-H122

Contents

4.5 4.6 4.7 4.8 4.9

Ethernet controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 USB2 host controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 USB2 device controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Low jitter PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Reconfigurable logic array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.9.1 4.9.2 4.9.3 4.9.4 Over view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Custom project development . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Customization process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 ADC controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4.10

Other interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.10.1 4.10.2 UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.1 5.2 5.3 5.4 5.5 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 General purpose I/O characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 LVDS electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 DDR I & DDR II pads electrical characteristics . . . . . . . . . . . . . . . . . . . . 36

6 7

Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

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List of tables

SPEA R-09-H122

List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin description by functional group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Main memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 ICM1 - low speed connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 ICM2 - application subsystem. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 ICM4 - high speed connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 ML1, 2 - multi layer CPU subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 ICM3 - basic subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Main oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 RTC oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Low voltage TTL DC input specification (3V
4/40

SPEAR-09-H122

List of figures

List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Main SPEAr Head600 functional interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Crystal connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Crystal equivalent model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 RTC crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 RTC crystal equivalent model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 PBGA420 mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

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Reference documentation

SPEA R-09-H122

Reference documentation
1. 2. 3. 4. 5. 6. 7. 8. 9. ARM926EJ-S - technical reference manual AMBA 2.0 specification EIA/JESD8-9 specification USB2.0 specification OHCI specification EHCI specification USB specification IEEE 802.3 specification I2C - bus specification

6/40

SPEAR-09-H122

Product overview

1

Product overview
An outline picture of the main SPEAr Head600 functional interfaces is shown in Figure 1. Figure 1. Main SPEAr Head600 functional interfaces

GM I I / M I I U SB2. 0 dev U SB2. 0 host(2) C LC D D D R 1/2 PL_GPI Os PL_LVD Ss J T AG & Test

I 2C SPI s (3) U AR T s (2) I rD A

SPEAr Head600

GPI Os AD C s F las h Serial F las h Nand

1.1

Features
The following main functionalities are implemented in the SPEAr Head600 SoC device:

ARM926EJ-S core @333 MHz, 16 Kbyte-I/D cache, configurable TMC-I/D size, MMU, TLB, JTAG and ETM trace module (multiplexed interfaces) 600 Kbyte reconfigurable logic array (programmable through 4 Metal and 4 Vias) 128 Kbyte configurable internal memory pool (single and dual port memory) 32 Kbyte ROM (code customizable) 8 Kbyte common SRAM Dynamic power save features High performance linked list 8 channels DMA Ethernet GMII/MII (IEEE802.3/3x/1Q), management i/f USB2.0 device (high-full speed), integrated PHY transceiver 2-USB2.0 host (high-full-low speed), integrated PHY transceiver Ext. memory i/f: 8/16-bit DDR1@200 MHz/DDR2@333 MHz Flash interface: nand 8/16-bit and serial (up to 50 Mbps) 3-SPI master/slave (motorola-texas-national) up to 40 Mbps I2C (high-fast-slow speed) master/slave 2-UART (speed rate up to 460.8 Kbps) IrDA (Fir-Mir-Sir) from 9.6 Kbps to 4 Mbps speed-rate Color LCD up to 1024x768 resolutions, 24 bpp true colour, STN/TFT display panel 10 GPIOs bidirectional signals with interrupt capability 9 LVDS (8 out and 1 input) signals, customizable interface through programmable logic 88 RAS-GPIOs user customizable bidirectional signals (up to 4 clocks)

7/40

Product overview

SPEA R-09-H122

ADC (1 s/1 MSPS) 8 analog input channel, 10-bit approximation JPEG codec accelerator 1clock/pixel 10 independent timers with programmable prescaler RTC - WDOG - SYSCTR - MISC internal control registers JTAG (IEEE1149.1) interface

1.2

Architecture properties

Power save features: Operating frequency SW programmable Clock gating functionality Low frequency operating mode Automatic power saving controlled from application activity demands 600 Kgate standard cell array Internal memory pool (128 Kbyte) full configurable Up to 16 external/internal source clock (some of these programmable) Three memory path toward the SDRAM controller to ensure a good bandwidth

Customizable logic to embed the customer real core competence:

Architecture easily extensible External memory bandwidth of each master tuneable to meet the target performances of different applications

8/40

SPEAR-09-H122

Product overview

1.3
Figure 2.

Block diagram
Block diagram
CPU1

SPEAr Head600
Configurable Cell Array Subsystem

ARM Subsystem
APB

SRAM 32KB

SRAM 32KB

ARM 926EJS 16kI /16kD Coproces. Cache Tcm -I/D I D

Tmr GPIO

Int ctr

I/F Control

Cell Array
(Applic. configurable)

Multi-layer Bus Interconnection Matrix
SDRAM Controller DDR 1- 2
D C B A

Uart
Uart

JPEG (Codec )

Tmr Tmr

Tmr
WDG RTC

DMA (8-chan .) CLCD

Eth . Gmac U S B 2. 0 Dev U S B 2. 0 Host U S B 2. 0 Host
HS connect

SPI SPI SRAM 32KB SRAM 32KB I2C

Flash NAND RAM (8KB )

Gpio SPI

Controller

Gpio Sys Ctr

ROM (32KB ) Flash Serial

ADC

IrDA
Low Speed connect Application Subs .

Misc

Basic Subsystem

Common Subsystems

9/40

Pin description

SPEA R-09-H122

2
2.1

Pin description
Functional pin group
With reference to figure package schematic in Section 6, here follows the pin list, sorted by their belonging IP. All supply and ground pins are classified as power signals and gathered in the Table 3.

Table 2.
Group

Pin description by functional group
Signal name AIN_0 AIN_1 AIN_2 AIN_3 AIN_4 Ball W11 V11 V12 W12 W13 V13 V14 W14 W15 V15 E15 E14 D14 D13 E13 D12 D17 Input Test reset input TTL Schmitt trigger input buffer, 3.3 V tolerant, PU TTL output buffer, 3.3 V capable,4 mA TTL Schmitt trigger input buffer, 3.3 V tolerant, PU Input Test configuration ports. TTL input buffer, For functional mode they have to be set to 3.3 V tolerant, PD zero. ADC negative voltage reference ADC positive voltage reference Input ADC analog input channel Analog buffer 2.5 V tolerant Direction Function Pin type

ADC

AIN_5 AIN_6 AIN_7 ADC_VREFN ADC_VREFP TEST_0 TEST_1 TEST_2 TEST_3 TEST_4 TEST_5 nTRST

DEBUG

TDO

E17

Output

Test data output

TCK TDI TMS PL PL_GPIO_0

E16 D16 D15 P4

Input Input Input I/O

Test clock Test data input Test mode select

TTL BIDIR buffer, Programmable logic I/O 3.3 V capable, 4mA 3.3 V tolerant, PU

10/40

SPEAR-09-H122 Table 2.
Group

Pin description

Pin description by functional group (continued)
Signal name PL_GPIO_1 PL_GPIO_2 PL_GPIO_3 PL_GPIO_4 PL_GPIO_5 PL_GPIO_6 PL_GPIO_7 PL_GPIO_8 PL_GPIO_9 PL_GPIO_10 PL_GPIO_11 PL_GPIO_12 PL_GPIO_13 PL_GPIO_14 PL_GPIO_15 PL_GPIO_16 PL_GPIO_17 Ball N4 N5 N6 M5 M4 M3 M2 M1 L1 L2 L3 L4 L5 K6 K5 K4 K3 K2 K1 J1 J2 J3 J4 J5 H5 H4 H3 H2 H1 G1 G2 G3 G4 G5 F5 I/O TTL BIDIR buffer, Programmable logic I/O 3.3 V capable, 4 mA 3.3 V tolerant, PU Direction Function Pin type

PL

PL_GPIO_18 PL_GPIO_19 PL_GPIO_20 PL_GPIO_21 PL_GPIO_22 PL_GPIO_23 PL_GPIO_24 PL_GPIO_25 PL_GPIO_26 PL_GPIO_27 PL_GPIO_28 PL_GPIO_29 PL_GPIO_30 PL_GPIO_31 PL_GPIO_32 PL_GPIO_33 PL_GPIO_34 PL_GPIO_35

11/40

Pin description Table 2.
Group

SPEA R-09-H122

Pin description by functional group (continued)
Signal name PL_GPIO_36 PL_GPIO_37 PL_GPIO_38 PL_GPIO_39 PL_GPIO_40 PL_GPIO_41 PL_GPIO_42 PL_GPIO_43 PL_GPIO_44 PL_GPIO_45 PL_GPIO_46 PL_GPIO_47 PL_GPIO_48 PL_GPIO_49 PL_GPIO_50 PL_GPIO_51 PL_GPIO_52 Ball F4 F3 F2 F1 E4 E3 E2 E1 D3 D2 D1 C2 C1 B1 A1 B2 A2 C3 B3 A3 B4 C4 D4 E5 D5 C5 B5 B6 C6 D6 E6 F6 F7 E7 D7 I/O TTL BIDIR buffer, Programmable logic I/O 3.3 V capable, 4 mA 3.3 V tolerant, PU Direction Function Pin type

PL

PL_GPIO_53 PL_GPIO_54 PL_GPIO_55 PL_GPIO_56 PL_GPIO_57 PL_GPIO_58 PL_GPIO_59 PL_GPIO_60 PL_GPIO_61 PL_GPIO_62 PL_GPIO_63 PL_GPIO_64 PL_GPIO_65 PL_GPIO_66 PL_GPIO_67 PL_GPIO_68 PL_GPIO_69 PL_GPIO_70

12/40

SPEAR-09-H122 Table 2.
Group

Pin description

Pin description by functional group (continued)
Signal name PL_GPIO_71 PL_GPIO_72 PL_GPIO_73 PL_GPIO_74 PL_GPIO_75 PL_GPIO_76 PL_GPIO_77 PL_GPIO_78 Ball C7 B7 E8 D8 C8 B8 A8 C9 D9 E9 E10 D10 C10 A7 A6 A5 A4 F22 E22 Input MII_TXCLK TXD_0 TXD_1 TXD_2 TXD_3 GMII_TXD_4 D22 F21 E21 Output F20 E20 Transmit data D21 D20 I/O GMII_TXD_6 GMII_TXD_7 TX_ER TX_EN RX_ER RX_DV RX_CLK RXD_0 C22 C21 D18 Output D19 C20 C19 Input A22 B22 Receive clock Receive data Transmit enable Receive error Receive data valid TTL input buffer 3.3 V tolerant, PD Transmit error TTL output buffer 3.3 V capable, 8 mA TTL BIDIR buffer 3.3 V capable, 8 mA 3.3 V tolerant, PD TTL output buffer 3.3 V capable, 8mA Transmit clock MII Output Transmit clock (GMII) Ext. clock TTL output buffer 3.3 V capable, 8 mA TTL input buffer, 3.3 V tolerant, PD Programmable logic external clock TTL BIDIR buffer, 3.3 V capable, 8 mA 3.3 V tolerant, PU I/O TTL output buffer 3.3 V capable, 4 mA Programmable logic I/O TTL input buffer 3.3 V tolerant, PU Direction Function Pin type

PL

PL_GPIO_79 PL_GPIO_80 PL_GPIO_81 PL_GPIO_82 PL_GPIO_83 PL_CLK_1 PL_CLK_2 PL_CLK_3 PL_CLK_4 GMII_TXCLK GMII_TXCLK125

Ethernet

GMII_TXD_5

13/40

Pin description Table 2.
Group

SPEA R-09-H122

Pin description by functional group (continued)
Signal name RXD_1 RXD_2 RXD_3 GMII_RXD_4 GMII_RXD_5 GMII_RXD_6 Ball B21 A21 B20 A20 B19 I/O A18 A19 A17 Input CRS MDIO B17 B18 I/O Carrier sense Management data I/O Collision detect TTL Input buffer 3.3 V tolerant, PD TTL BIDIR buffer 3.3 V capable, 4 mA 3.3 V tolerant, PD TTL output buffer 3.3 V capable, 8 mA Receive data TTL BIDIR buffer 3.3 V capable, 8 mA 3.3 V tolerant, PD Input TTL Input buffer 3.3 V tolerant, PD Direction Function Pin type

Ethernet

GMII_RXD_7 COL

MDC GPIO_0 GPIO_1 GPIO_2 GPIO_3 GPIO_4 GPIO GPIO_5 GPIO_6 GPIO_7 GPIO_8 GPIO_9 CLD_0 CLD_1 CLD_2 CLD_3 CLD_4 LCD I/F CLD_5 CLD_6 CLD_7 CLD_8 CLD_9 CLD_10

C18 W18 V18 U18 T18 W19

Output

Management data clock

I/O V19 U19 T19 R19 R18 Y20 Y21 Y22 W22 W21 W20 V20 V21 V22 U22 U21 Output

General purpose I/O

TTL BIDIR buffer 3.3 V capable, 8 mA 3.3 V tolerant, PU

TTL output buffer 3.3 V capable, 8 mA

LCD data TTL output buffer 3.3 V capable, 8 mA

14/40

SPEAR-09-H122 Table 2.
Group

Pin description

Pin description by functional group (continued)
Signal name CLD_11 CLD_12 CLD_13 CLD_14 CLD_15 CLD_16 CLD_17 CLD_18 CLD_19 CLD_20 Ball U20 T20 T21 R21 R20 P19 P20 P21 N21 N20 N19 M20 M21 T22 R22 P22 Output CLLP CLLE CLPOWER DDR_ADD_0 DDR_ADD_1 DDR_ADD_2 DDR_ADD_3 DDR_ADD_4 DDR_ADD_5 DDR_ADD_6 N22 M22 M19 AB3 AB4 AA4 Y4 W4 W5 Y5 Address line DDR_ADD_7 DDR_ADD_8 DDR_ADD_9 DDR_ADD_10 DDR_ADD_11 DDR_ADD_12 DDR_ADD_13 AA5 AB5 AB6 AA6 Y6 W6 W7 SSTL_2/SSTL_18 STN AC bias drive TFT data enable LCD panel clock STN frame pulse TFT vertical sync STN line pulse TFT horizontal sync Line end LCD power enable TTL output buffer 3.3 V capable, 8 mA LCD data Direction Function Pin type

LCD I/F

CLD_21 CLD_22 CLD_23 CLAC CLCP CLFP

DDR I/F

15/40

Pin description Table 2.
Group

SPEA R-09-H122

Pin description by functional group (continued)
Signal name DDR_ADD_14 DDR_BA_0 DDR_BA_1 DDR_BA_2 DDR_RAS DDR_CAS DDR_WE DDR_CLKEN DDR_CLK_P DDR_CLK_N DDR_CS_0 DDR_CS_1 DDR_ODT_0 DDR_ODT_1 DDR_DATA_0 Ball Y7 Y9 Bank select W9 W10 AB7 AA7 AA8 AB8 AA9 AB9 Y8 W8 AB2 AB1 AB11 AA10 AB10 Y10 Y11 Y12 AB12 AA12 AB13 AA13 AA11 Y13 AB15 AA16 AB16 I/O DDR_DATA_11 DDR_DATA_12 DDR_DATA_13 DDR_DATA_14 Y16 Y15 Y14 AB14 Data lines (upper byte) SSTL_2/SSTL_18 Output Differential lower data strobe Lower data mask Lower gate open Differential SSTL_2/SSTL_18 I/O SSTL_2/SSTL_18 Chip select Chip select On-die termination enable lines Data lines (lower byte) SSTL_2/SSTL_18 Output Bank select SSTL_2/SSTL_18 Row strobe Column strobe Write enable Clock enable Differential clock Differential SSTL_2/SSTL_18 Direction Function Address line Pin type

DDR I/F

DDR_DATA_1 DDR_DATA_2 DDR_DATA_3 DDR_DATA_4 DDR_DATA_5 DDR_DATA_6 DDR_DATA_7 DDR_DQS_0 DDR_nDQS_0 DDR_DM_0 DDR_GATE_0 DDR_DATA_8 DDR_DATA_9 DDR_DATA_10

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SPEAR-09-H122 Table 2.
Group

Pin description

Pin description by functional group (continued)
Signal name DDR_DATA_15 DDR_DQS_1 DDR_nDQS_1 DDR_DM_1 DDR_GATE_1 Ball AA14 AB17 AA17 AA15 Y17 V10 V9 V8 V7 D11 V1 I/O DEV_DM DEV_VBUS HOST1_DP HOST1_DM HOST1_VBUS V2 R4 T1 I/O T2 P5 P6 P1 P2 R5 R6 U4 Y1 Y2 A9 B9 L21 Output Input Output Input Output Input Output Input Output Input I/O USB HOST1 DUSB HOST1 VBUS USB host1 over-current USB HOST2 D+ USB HOST2 DUSB HOST2 VBUS USB host2 over-current Reference resistor 30 MHz crystal I 30 MHz crystal O 32 KHz crystal I Oscillator 1 V capable RTC_XO 32 KHz crystal O Serial Flash input data TTL input buffer 3.3 V tolerant, PU Input USB device DUSB device VBUS USB HOST1 D+ Output I/O Input Output Output input I/O Differential upper data strobe Upper data mask SSTL_2/SSTL_18 Upper gate open Reference voltage Ext. resistor 2.5 V Common return for ext. resistors Ext. resistor 1.8 V Configuration USB device D+ Analog Analog Power Analog TTL input buffer 3.3 V tolerant, PU Bidirectional analog buffer 5V tolerant TTL input buffer 3.3V tolerant, PD Bidirectional analog buffer 5 V tolerant TTL output buffer 3.3 V capable, 4 mA TTL input buffer 3.3 V tolerant, PD Bidirectional analog buffer 5 V tolerant TTL output buffer 3.3 V capable, 4 mA TTL input buffer 3.3 V tolerant, PD Analog Oscillator 2.5 V capable Differential SSTL_2/SSTL_18 Direction Function Data lines (upper byte) Pin type SSTL_2/SSTL_18

DDR I/F

DDR_VREF DDR_COMP_2V5 DDR_COMP_GND DDR_COMP_1V8 DDR2_EN DEV_DP

USB HOST1_OVRC HOST2_DP HOST2_DM HOST2_VBUS HOST2_OVRC USB_RREF Master Clock RTC MCLK_XI MCLK_XO RTC_XI

SMI

SMI_DATAIN

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Pin description Table 2.
Group

SPEA R-09-H122

Pin description by functional group (continued)
Signal name SMI_DATAOUT Ball L20 L22 L19 L18 AA21 AB21 AB22 AA22 K20 K21 K22 K19 K18 J20 J21 J22 J19 AA19 AA20 AB19 AB20 AA18 AB18 Y18 Y19 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Output Serial data out UART2_TXD Output Input Serial data in UART2_RXD FIRDA_TXD Input Output Input I/O I/O Serial data out Serial data in Serial data in/out Serial clock Output Direction Function Serial Flash output data Serial Flash clock Serial Flash chip selects Master out slave in Master in slave out Serial clock Slave select Master out slave in Master in slave out Serial clock Slave select Slave select Master out slave in Master in slave out Serial clock Slave select TTL output buffer 3.3 V capable, 4 mA TTL input buffer 3.3 V tolerant, PD TTL output buffer 3.3 V capable, 4 mA TTL input buffer 3.3 V tolerant, PU TTL BIDIR buffer 3.3 V capable, 4 mA 3.3 V tolerant, PU TTL BIDIR buffer 3.3 V capable, 4 mA 3.3 V tolerant, PU TTL BIDIR buffer 3.3 V capable, 8 mA 3.3 V tolerant, PU TTL output buffer 3.3 V capable, 4 mA Pin type

SMI

SMI_CLK SMI_CS_0 SMI_CS_1 SSP_1_MOSI SSP_1_MISO SSP_1_SCLK SSP_1_SS SSP_2_MOSI SSP_2_MISO

SPI SSP_2_SCLK SSP_2_SS_0 SSP_2_SS_1 SSP_3_MOSI SSP_3_MISO SSP_3_SCLK SSP_3_SS UART1_TXD UART UART1_RXD

FIRDA FIRDA_RXD SDA

I 2C
NAND FLASH I/F

SCL

NF_IO_0

H19

I/O

Data

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SPEAR-09-H122 Table 2.
Group

Pin description

Pin description by functional group (continued)
Signal name NF_IO_1 NF_IO_2 NF_IO_3 NF_IO_4 NF_IO_5 NF_IO_6 Ball H18 G19 G18 F19 F18 E18 E19 G20 G22 H20 Output NF_ALE NF_CLE NF_WP NF_RB H21 G21 J18 H22 Input Address latch enable Command latch enable Write protect Read/busy TTL input buffer 3.3 V tolerant PU TTL Schmitt trigger input buffer, 3.3 V tolerant, PU Chip enable Read enable Write enable TTL output buffer 3.3 V capable, 4 mA I/O Data TTL BIDIR buffer 3.3 V capable, 4 mA 3.3 V tolerant, PU Direction Function Pin type

NAND FLASH I/F

NF_IO_7 NF_CE NF_RE NF_WE

MRESET PH0 PH0n PH1 PH1n PH2 PH2n PH3 PH3n LVDS I/F PH4 PH4n PH5 PH5n PH6 PH6n PH7 PH7n PH8

C17 A16 B16 C16 C15 A15 B15 A14 B14

Input

Main reset

Output C14 C13 A13 B13 A12 B12 C12 C11 A11 Input

General purpose I/O with LVDS transceiver

LVDS driver

LVDS receiver

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Pin description Table 2.
Group LVDS I/F

SPEA R-09-H122

Pin description by functional group (continued)
Signal name PH8n DIGITAL_REXT Ball B11 E11 Direction Input Output Function General purpose I/O with LVDS transceiver Configuration Pin type LVDS receiver Analog 3.3 V capable

Note: Table 3.

PU means pull up and PD means pull down Power supply
Ball J9, J10, J11, J12, J13, J14, K9, K10, K11, K12, K13, K14, L9, L10, L11, L12, L13, L14, M9, M10, M11, M12, M13, M14, N9, N10, N11, N12, N13, N14, P9, P10, P11, P12, P13, P14, M18, N18, P18, T5, V6, N2, R1, U2, T4, W3, W2, Y3, AA3, V5, U5, V17, U17, A10, E12 V16 J6, H6, F8, F9, F16, H17, K17, L17, N17, P17, M6, F17 G6, L6, G17, M17, R17, F10, F13, F15, J17, T6, U13, U10, U16 N1 N3 R3 P3 R2 R3 U1 U3 T3 V3 W1 AA1 AA2 V4 U6 U7, U8, U9, U11, U12, U14, U15 W16 W17 T17 F11, F12, F14 B10 Value

Signal name

GND

0V

AGND

0V 3.3 V 1.0 V 2.5 V 1.0 V 3.3 V 2.5 V 1.0 V 3.3 V 2.5 V 1.0 V 3.3 V 1.0 V 2.5 V 1.0 V 2.5 V 2.5 V 1.0 V 1.8/2.5 V 2.5 V 2.5 V 1.0 V 2.5 V 1.0 V

VDD3 VDD HOST2_VDDbc HOST2_VDDbs HOST2_VDDb3 HOST1_VDDbc HOST1_VDDbs HOST1_VDDb3 DEVICE_VDDbc DEVICE_VDDbs DEVICE_VDDb3 USB_PLL_VDDp USB_PLL_VDDp2v5 MCLK_VDD MCLK_VDD2v5 DITH_VDD2v5 DITH_VDD SSTL_VDDe ADC_AVDD DDR_PLL_AVDD DDR_PLL_VDD LVDS_VDD RTC_VDD

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SPEAR-09-H122

Pin description

2.2
2.2.1

Special IOs
USB 2.0 transceiver
SPEAr Head600 has three USB 2.0 multimode ATX transceivers. One transceiver will be used by the USB device controller, and two will be used by the hosts. These are all integrated into a single USB three-PHY macro.

2.2.2

SSTL_2/SSTL_18
T.B.D.

2.2.3

LVDS
T.B.D.

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Memory map

SPEA R-09-H122

3
3.1

Memory map
Main memory map
Table 4. Main memory map
End address 0x3FFF.FFFF 0xBFFF.FFFF 0xCFFF.F7FF 0xCFFF.FFFF 0xD7FF.FFFF 0xDFFF.FFFF 0xE7FF.FFFF 0xEFFF.FFFF 0xF7FF.FFFF 0xFFFF.FFFF Peripheral External SDRAM RAS_N/M AHB_EH2H exp. interface AHB_EH2H registers ICM1 ICM2 ICM4 Reserved ML1,2 ICM3 Multi layer CPU subsystem Basic subsystem Low speed connection Application subsystem High speed connection Notes DDR1 or DDR2 Programmable logic array Start address 0x0000.0000 0x4000.0000 0xC000.0000 0xCFFF.F800 0xD000.0000 0xD800.0000 0xE000.0000 0xE800.0000 0xF000.0000 0xF800.0000

3.2

ICM1 - low speed connection
Table 5. ICM1 - low speed connection
End address 0xD007.FFFF 0xD00F.FFFF 0xD017.FFFF 0xD01F.FFFF 0xD027.FFFF 0xD07F.FFFF 0xD0FF.FFFF 0xD17F.FFFF 0xD1FF.FFFF 0xD27F.FFFF 0xD7FF.FFFF Peripheral UART 1 UART 2 SPI 1 SPI 2 I2C JPEG codec IrDA FSMC FSMC SRAM NAND Flash controller NAND Flash memory Static RAM shared memory (8 Kbyte) Reserved Notes Bus APB APB APB APB APB AHB AHB AHB AHB AHB Start address 0xD000.0000 0xD008.0000 0xD010.0000 0xD018.0000 0xD020.0000 0xD028.0000 0xD080.0000 0xD100.0000 0xD180.0000 0xD200.0000 0xD280.0000

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SPEAR-09-H122

Memory map

3.3

ICM2 - application subsystem
Table 6. ICM2 - application subsystem
End address 0xD807.FFFF 0xD80F.FFFF 0xD817.FFFF 0xD81F.FFFF 0xD827.FFFF 0xDFFF.FFFF Peripheral Timer 1 Timer 2 GPIO SPI 3 ADC Reserved Notes Bus APB APB APB APB APB Start address 0xD800.0000 0xD808.0000 0xD810.0000 0xD818.0000 0xD820.0000 0xD828.0000

3.4

ICM4 - high speed connection
Table 7. ICM4 - high speed connection
End address 0xe07F.FFFF 0xE0FF.FFFF 0xE10F.FFFF 0xE11F.FFFF 0xE12F.FFFF 0xE17F.FFFF 0xE18F.FFFF 0xE19F.FFFF 0xE1FF.FFFF 0xE20F.FFFF 0xE21F.FFFF 0xE2FF.FFFF 0xE280.FFFF 0xE7FF.FFFF Ethernet ctrl USB2.0 device USB2.0 device USB2.0 device USB2.0 EHCI 1 USB2.0 OHCI 1 USB2.0 EHCI 2 USB2.0 OHCI 2 ML USB ARB Reserved Configuration register Reserved Reserved Peripheral Reserved GMAC FIFO Configuration registers Plug detect Reserved Notes Bus APB AHB AHB AHB AHB AHB AHB AHB AHB AHB AHB AHB AHB AHB Start address 0xE000.0000 0xE080.0000 0xE100.0000 0xE110.0000 0xE120.0000 0xE130.0000 0xE180.0000 0xE190.0000 0xE1A0.0000 0xE200.0000 0xE210.0000 0xE220.0000 0xE280.0000 0xE290.0000

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Memory map

SPEA R-09-H122

3.5

ML1, 2 - multi layer CPU subsystem
Table 8. ML1, 2 - multi layer CPU subsystem
End address 0xF00F.FFFF 0xF01F.FFFF 0xF0FF.FFFF 0xF10F.FFFF 0xF11F.FFFF 0xF7FF.FFFF Peripheral Timer GPIO ITC secondary ITC primary Reserved Reserved Notes Bus APB APB AHB AHB AHB AHB Start address 0xF000.0000 0xF010.0000 0xF020.0000 0xF100.0000 0xF110.0000 0xF120.0000

3.6

ICM3 - basic subsystem
Table 9. ICM3 - basic subsystem
End address 0xFBFF.FFFF 0xFC1F.FFFF 0xFC3F.FFFF 0xFC5F.FFFF 0xFC7F.FFFF 0xFC87.FFFF 0xFC8F.FFFF 0xFC97.FFFF 0xFC9F.FFFF 0xFCA7.FFFF 0xFCAF.FFFF 0xFEFF.FFFF 0xFFFF.FFFF Peripheral Serial Flash memory Serial Flash controller LCD controller DMA controller SDRAM controller Timer Watch dog timer Real time clock General purpose I/O System controller Miscellaneous registers Internal ROM Reserved Boot Notes Start address 0xF800.0000 0xFC00.0000 0xFC20.0000 0xFC40.0000 0xFC60.0000 0xFC80.0000 0xFC88.0000 0xFC90.0000 0xFC98.0000 0xFCA0.0000 0xFCA8.0000 0xFCB0.0000 0xFF00.0000

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SPEAR-09-H122

Main blocks

4
4.1
4.1.1

Main blocks
7.1 CPU subsystem
Overview
The CPU sub-system includes the following blocks:

ARM 926EJS Two timer channels One GPIO block (8 I/O lines) Two interrupt controller (32 IRQ lines)

4.1.2

CPU ARM 926EJ-S
The processor is the powerful ARM926EJ-S, targeted for multi-tasking applications. Belonging to ARM9 general purposes family microprocessor, it principally stands out for the memory management unit, which provides virtually memory features, making it also compliant with WindowsCE, linux and SymbianOS operating systems. The ARM926EJ-S supports the 32-bit ARM and 16-bit thumb instruction sets, enabling the user to trade off between high performance and high code density and includes features for efficient execution of java byte codes. Besides, it has the ARM debug architecture and includes logic to assist in software debug. Its main features are:

Core fMAX 333 MHz independent programmable for each CPU Memory management unit 16 Kbyte of instruction cache 16 Kbyte of data cache Configurable tightly coupled memory (I/D) size trough the configurable logic array ARM-V5TEJ instructions set architecture: ARM (32-bit), Thumb (16-bit) DSP extensions JAVATM (8-bit) instructions

AMBA bus interface Coprocessor interface EmbeddedICE-RT Single mode (two connectors) Two processor daisy chained Single ETM mode (single or double packet configurable) Dual ETM mode (both processors ETM are available in single packet mode)

ETM9 (embedded trace macro-cell)

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Main blocks

SPEA R-09-H122

4.2

Clock and reset system
The clock system block is a fully programmable block able to generate all clocks necessary at the chip. The clocks, at default operative frequency, are:

Clock @ 333 MHz for the CPUs (Note 1) Clock @ 166 MHz for AHB bus and AHB peripherals (Note 1) Clock @ 83 MHz for, APB bus and APB peripherals (Note 1) Clock @ 100-333 MHz for DDR memory interface (Note 2)

The frequencies are the maximum allowed value and the user can modify them by programming dedicated registers. The clock system consists of 2 main parts: a multi-clock generator block and an two internal PLL. The multi-clock generator block, starting from a reference signal (which generally is delivered from the PLL), generates all clocks for the IPs of SPEAr Head600 according to dedicated programmable registers. Each PLL, starting from the oscillator input of 30 MHz, generates a clock signal at a frequency corresponding at the highest of the group, which is the reference signal used by the multi-clock generator block to obtain all the other requested clocks for the group. Its main features is the electro-magnetic Interference reduction capability: user has the possibility to set up the PLL in order to modulate with a triangular wave to the VCO clock, the resulting signal will have the spectrum (and the power) spread on a small range (programmable) of frequencies centered on F0 (VCO Freq.), obtaining minimum electromagnetic emissions. This method replace all the other traditional methods of E.M.I. reduction, as filtering, ferrite beads, chokes, adding power layers and ground planets to PCBs, metal shielding etc., allowing sensible cost saving for customers. Note: 1 2 This frequency is based on the PLL1. This frequency is based on the PLL2.

4.3
4.3.1

Main oscillator
Crystal connection
Figure 3. Crystal connection
Xi 30 MHz Xo

33 pF

33 pF

VDD2V5

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SPEAR-09-H122

Main blocks

4.3.2

Crystal equivalent model
Figure 4. Crystal equivalent model
Xi Co Xo

Cm C l1

Rm

Lm C l2 VDD2V 5

1. Co is the parasitic capacitance of the crystal package 2. Cl1 and Cl2 are the capacitance on each resonator PAD

Table 10.

Main oscillator characteristics
Rm(Ohms) 9.3 9.6 5 Lm(mH) 5.9 2.6 3.2 Cm(fF) 4.8 10.8 8.7 Co(pF) 1.7 3.5 2.7 Q(K) 120 45 121

Supplier Epson (E31821) Raltron (M3000) KSS (KSS3KF)

4.4
4.4.1

RTC oscillator
RTC crystal connection
Figure 5. RTC crystal oscillator
Xi 30 MHz Xo

27 pF

27 pF

GN D

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Main blocks

SPEA R-09-H122

4.4.2

RTC crystal equivalent model
Figure 6. RTC crystal equivalent model
Xi Co Xo

Cm C l1

Rm

Lm C l2

GN D

1. Co is the parasitic capacitance of the crystal package 2. Cl1 and Cl2 are the capacitance on each resonator PAD

Table 11.

RTC oscillator characteristics
Rm(KOhms) <65 Lm(mH) 10 Cm(fF) 1.9 Co(pF) 0.85

Supplier Ecliptek

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Main blocks

4.5

Ethernet controller

Compliant with the IEEE 802.3-2002 standard GMII or MII interface to the external PHY It supports 10/100/1000 Mbps data transfer rates with any one or a combination of the PHY interfaces above Local FIFO available (4 Kbyte RX, 2 Kbyte TX) It supports both half-duplex and full-duplex operation. In half-duplex operation, CSMA/CD protocol is provided for, as well as packet bursting and frame extension at 1000 Mbps Programmable frame length to support both standard and jumbo ethernet frames with size up to 16 Kbytes A variety of flexible addresses filtering modes are supported A set of control and status registers (CSRs) to control GMAC core operation Native DMA with single-channel transmit and receive engines, providing 32/64/128-bit data transfers DMA implements dual-buffer (ring) or linked-list (chained) descriptor chaining An AHB slave acting as programming interface to access all CSRs, for both DMA and GMAC core subsystems An AHB master for data transfer to system memory 32-bit AHB master bus width, supporting 32, 64, and 128-bit wide data transactions

4.6

USB2 host controller
SPEAr Head600 has two fully independent USB 2.0 hosts and each one is constituted with 5 major blocks:

EHCI able to manage the high speed transfer (HS - 480 Mbit) OHCI that manages the full and the low speed transfer (12 and 1.5 Mbit) Local FIFO having size of 2 Kbyte Local DMA Integrated USB2 transceiver (PHY)

Both the hosts are capable to manage an external power switch providing the control line to enable or disable the power and also having an input line to sense the over-current condition detected by the external switch.

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Main blocks

SPEA R-09-H122

4.7

USB2 device controller

It supports the 480 Mbps high-speed (HS) for USB 2.0, as well as the 12 Mbps fullspeed (FS) for USB 1.1 It supports 16 physical endpoints and proper configurations to achieve logical endpoints EP0 EP1~15 Control (IN/OUT) Software configurable to: Bulk in Bulk out Interrupt in Interrupt out Isochronous

Integrated USB transceiver (PHY) Local FIFO having size of 4 Kbyte shared among all the endpoints Both DMA mode and slave-only mode supported In DMA mode, the UDC supports descriptor-based memory structures in application memory In both modes, an AHB slave is provided by UDC-AHB, acting as programming interface to access to memory-mapped control and status registers (CSRs) An AHB master for data transfer to system memory is provided, supporting 8, 16, and 32-bit wide data transactions on the AHB bus A USB plug detect (UPD) which detects the connection of a cable

4.8

Low jitter PLL
Within the USB hosts and device a local low jitter PLL is provided to meet the USB2.0 specification requirements.

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SPEAR-09-H122

Main blocks

4.9
4.9.1

Reconfigurable logic array
Overview
The configurable logic array consists of an embedded macro where it is possible to implement a custom project by mapping up to 600 K equivalent gates. This macro is interfaced with the rest of the system by some AHB bus, some memory channels and has a direct connection to the 1st ARM processor internal bus. In this way is also possible to customize the TCM memory or add a coprocessor using this macro. The following memory cuts are available to this block:

4 cuts single port with size of 8 Kbyte each 8 cuts single port with size of 4 Kbyte each 16 cuts single port with size of 2 Kbyte each 8 cuts dual port with size of 2 Kbyte each 4 cuts dual port with size of 4 Kbyte each

The array is also connected to 88 I/O (3.3 V capable/tolerant and 4 mA sink/source) plus 9 lvds lines (one input and 8 outputs). The following clocks can be used in the integrated logic:

5 different coming from the external balls 4 different coming from the integrated frequency synthesizer PLL1 frequency PLL2 frequency 48 MHz (USB PLL) 30 MHz (MAIN oscillator) 32.768 KHz (RTC oscillator) APB clock (programmable) AHB clock (programmable)

4.9.2

Custom project development
The flow to develop a custom project to embed in the SPEAr Head600 is similar to the standard ASIC flow. The configurable Logic is an empty module of the whole system-on-chip. Pin out and maximum gates are fixed. The HDL project is synthesized using dedicated library and post synthesis simulation is possible to verify the custom net-list. Regarding the back end flow, after the place and route phase the verification procedure is the same as a standard ASIC flow.

4.9.3

Customization process
The layers used for the IP configuration range from 2 metals - 1 via up to 4 metals - 4 vias. Diffusion and remaining metal/vias are invariant across multiple custom designs. Density and performance scale with number of customization layers. The configurable logic included in the SPEAr Head600 chip is a 600 Kgates equivalent array when customized using 4 metals - 4 vias.

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Main blocks

SPEA R-09-H122

4.9.4

ADC controller

Successive approximation ADC 10-bit resolution Up to 1 Msps analog input (AIN) channels, ranging from 0 to 2.5 V INL 1 LSB, DNL 1 LSB Programmable conversion speed, (min conversion time is 1 s) Programmable average results from 1 (No average) up to 128

4.10
4.10.1

Other interfaces
UART
Two UART are provided with the following features:

Separate 16x8 (16 location deep x 8-bit wide) transmit and 16x12 receive FIFOs to reduce CPU interrupts Speed up to 560.8 Kbps

4.10.2

SPI
Three SPI are provided. The main features are:

Max speed of 40 Mbps Programmable choice of interface operation SPI, microwire or TI synchronous serial Programmable data frame size from 4 to 16-bit The SPI controllers can deal with master and slave mode A connection with general purpose DMA is provided to reduce the CPU load

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SPEAR-09-H122

Electrical characteristics

5
5.1

Electrical characteristics
Absolute maximum ratings
This product contains devices to protect the inputs against damage due to high static voltages, however it is advisable to take normal precaution to avoid application of any voltage higher than the specified maximum rated voltages. Table 12.
Symbol VDD core VDD I/O VDD PLL VDD DDR1 VDD DDR2 VDD RTC Supply voltage core Supply voltage I/O Supply voltage PLL Supply voltage DRAM I/F (DDR1) Supply voltage DRAM I/F (DDR2) Supply voltage RTC 4.8 4.8 1.6

Absolute maximum ratings
Parameter Value 1.6 4.8 Unit V V V V V V

TJ TSTG

Junction temperature Storage temperature

-40 ~ 125 -55 ~ 150

C C

The average chip-junction temperature, Tj, can be calculated using the following equation: Tj = TA + (PD · JA) where:

TA is the ambient temperature in C JA is the package Junction-to-Ambient thermal resistance, which is 34 C/W PD = PINT + PPORT PINT is the chip internal power PPORT is the power dissipation on Input and Output pins, user determined

If PPORT is neglected, an approximate relationship between PD is: PD = K / (Tj + 273 C) And, solving first equations: K = PD · (TA + 273 C) + JA x PD2 K is a constant for the particular, which can be determined through last equation by measuring PD at equilibrium, for a know TA Using this value of K, the value of PD and TJ can be obtained by solving first and second equation, iteratively for any value of TA.

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Electrical characteristics

SPEA R-09-H122

5.2

DC electrical characteristics
Supply voltage specifications The recommended operating conditions are listed in the following table: Table 13.
Symbol VDD core VDD I/O VDD PLL VDD OSC VDD DDR1 VDD DDR2 VDD RTC TOP

DC electrical characteristics
Parameter Supply voltage core Supply voltage I/O Supply voltage PLL Supply voltage oscillator Supply voltage DRAM I/F (DDR1) Supply voltage DRAM I/F (DDR2) Supply voltage RTC Operating temperature Min. 0.95 3 2.25 2.25 2.25 1.7 0.95 -40 Typ. 1 3.3 2.5 2.5 2.5 1.8 1 Max. 1.05 3.6 2.75 2.75 2.75 1.9 1.05 85 Unit V V V V V V V C

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SPEAR-09-H122

Electrical characteristics

5.3

General purpose I/O characteristics
The 3.3V I/Os are compliant with JEDEC standard JESD8b Table 14.
Symbol Vil Vih Vhyst

Low voltage TTL DC input specification (3VParameter Low level input voltage High level input voltage Schmitt trigger hysteresis 2 300 800 Test condition Min. Max. 0.8 Unit V V mV

Table 15.
Symbol Vol Voh

Low voltage TTL DC output specification (3VParameter Low level output voltage High level output voltage Test condition Iol = XmA
(1)

Min.

Max. 0.3

Unit V V

Ioh = -XmA (1)

Vdde3V3 - 0.3

1. For the max current value (XmA) refer to Chapter 2: Pin description.

Table 16.
Symbol Rpu Rpd

Pull-up and pull-down characteristics
Parameter Equivalent pull-up resistance Equivalent pull-down resistance Test condition Vi = 0 V Vi = Vdde3V3 Min. 29 29 Max. 67 103 Unit K K

5.4

LVDS electrical characteristics
Table 17.
Symbol Vol Voh Vod Ro Isa,Isb Isab

Driver specification
Parameter Output voltage low, Voa or Vob Output voltage high, Voa or Vob Output differential voltage Output impedance single ended Output current Output current Test condition Rload = 100 ohms 1% Rload = 100 ohms 1% Rload = 100 ohms 1% Vcm = 1.0 V and 1.4 V Drivers shorted to ground Drivers shorted together 250 40 Min. 925 1475 400 140 40 12 Max. Unit mV mV mV mA mA

Table 18.
Symbol Clock tfall trise tskew1

AC output specification (2.2VParameter Clock signal duty cycle Vod fall time 20÷80 Vod rise time 20÷80 [tpHLA-tpLHB] or [tpHLB- tpLHA] Rload = 100 ohms 1% Rload = 100 ohms 1% Any packaged pair Test condition Min. 40 150 150 Max. 60 300 300 50 Unit % pS pS pS

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Electrical characteristics Figure 7. Test circuit
Voa TX line Z0 Cop Vob TX line Z0 Cop Rt

SPEA R-09-H122

Note:

Cop = 5 pF, Rt = 100 , Z0 = 50 Max frequency of operation 400 MHz Table 19.
Symbol Vi Vidth Vhyst Rin

Receiver specification
Parameter Input voltage range, Via or Vib Input differential threshold Input differential hysteresis Receiver differential input impedance Vidthh-Vidthl Test condition Min. 0.4 -100 25 80 120 Max. 2.2 +100 Unit V mV mV

5.5

DDR I & DDR II pads electrical characteristics
Table 20.
Symbol Vil

DC characteristics
Parameter Low level input voltage SSTL18 SSTL2 High level input voltage SSTL18 Input voltage hysteresis -0.3 Vref + 0.15 Vref + 0.125 200 Test condition SSTL2 Min. -0.3 Max. Vref - 0.15 Vref - 0.125 Vdde2V5 + 0.3 Vdde1V8 + 0.3 Unit V V V V mV

Vih Vhyst

Table 21.
Symbol Ro

Driver characteristics
Parameter Output impedance Test condition Min. Typ. 45 Max. Unit

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SPEAR-09-H122 Table 22.
Symbol RT1 (1) RT2 (1)

Electrical characteristics On die termination
Parameter Termination value of resistance for on die termination Termination value of resistance for on die termination Test condition Min. Typ. 75 150 Max. Unit

1. For more detail about RT1/RT2 usage refer to chapter 17.4.10 MEM10_CTL Register of the User Manual (register rrt_0).

Table 23.
Symbol VREFIN

Reference voltage
Parameter Voltage applied at core/pad Test condition Min. Typ. Max. Unit V

0.49 * Vdde 0.500 * Vdde 0.51 * Vdde

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Package information

SPEA R-09-H122

6

Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 8. PBGA420 mechanical data and package dimensions
mm D IM . MIN. A A1 A2 A3 A4 b D D1 E E1 e F ddd eee fff 22.80 0.45 22.80 0.27 1.305 0.52 0.785 0.50 23.00 21.00 23.00 21.00 1.00 1.00 0.20 0.25 0.10 TYP. M AX . 1.81 0.0106 0.0514 0.0205 0.0309 0.55 0.0177 0.0197 0.0217 23.20 0.8976 0.9055 0.9134 0.8268 23.20 0.8976 0.9055 0.9134 0.8268 0.0394 0.0394 0.0079 0.0098 0.0039 MIN. TYP. MAX. 0.0713 inch

OUTLINE AND MECHANICAL DATA

PBGA420 (23x23x1.81mm) Ball Grid Array Package

7859856 A

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SPEAR-09-H122

Revision history

7

Revision history
Table 24.
Date 28-Feb-2007

Document revision history
Revision 1 Initial release. Modified Section 1.1: Features. Modified Table 2: Pin description by functional group Modified Section 4.7: USB2 device controller. Added Section 5.3: General purpose I/O characteristics Added Section 5.4: LVDS electrical characteristics Added Section 5.5: DDR I & DDR II pads electrical characteristics Changes

31-Jul-2008

2

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SPEAR-09-H122

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Document Number: 13289



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