PM6641
Monolithic VR for chipset and DDR2/3 supply for ultra-mobile PC (UMPC) applications
Features
0.8 V 1 % internal voltage reference 2.7 V to 5.5 V input voltage range Fast response, constant frequency, current mode control Three independent, adjustable, out-of-phase SMPS for DDR2/3 (VDDQ) and chipset supply Low noise DDR2/3 reference (VTTREF) 2 Apk LDO for DDR2/3 termination (VTT) with foldback S0-S5 states compliant DDR2/3 section Active soft-end for all outputs Selectable tracking discharge for VDDQ Separate power-good signals Pulse skipping at light load Programmable current limit and soft-start for all outputs Latched OVP, UVP protection Thermal protection VFQFPN-48 7x7
Description
The PM6641 is a monolithic voltage regulator module specifically designed to supply DDR2/3 memory and chipset in ultra-mobile PC and real estate constrained portable systems. It integrates three independent, adjustable, constant frequency buck converters, a 2 Apk Low Drop-Out (LDO) linear regulator and a 15 mA low noise buffered reference. Each regulator provides basic UV and OV Protections, programmable Soft-Start and Current Limit and active Soft-End. Pulse-Skipping technique is performed to increase efficiency at very light load.
Applications
DDR2/3 memory and chipset supply UMPC and portable equipment Handheld and PDAs
Table 1. Device summary
Part number PM6641 PM6641TR January 2008 Package VFQFPN-48 7x7 (exposed pad) VFQFPN-48 7x7 (exposed pad Rev 2 Packaging Tray Tape & reel 1/47
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Contents
PM6641
Contents
1 2 Typical application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 2.2 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1 3.2 3.3 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4 5 6 7
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.1 Memory supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.1.1 7.1.2 7.1.3 7.1.4 VDDQ switching regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 VTT LDO and VTTREF buffered reference . . . . . . . . . . . . . . . . . . . . . . 21 VTT and VTTREF Soft Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 S3 and S5 power management pins . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11
Chipset supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 SW regulators control loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 SW regulators pulse skipping and PWM mode . . . . . . . . . . . . . . . . . . . . 26 Output voltage divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Outputs Soft-Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Outputs Soft-End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Switching frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Phase management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Peak current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Fault management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2/47
PM6641 7.11.1 7.11.2 7.11.3 7.11.4
Contents Output over voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Output under voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Input under voltage lock-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8
Components selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
8.1 8.2 8.3 8.4 8.5 Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 SW regulator compensation components selection . . . . . . . . . . . . . . . . . 38 Layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
9
Application examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
9.1 UMPC DDR2 and chipset power supply . . . . . . . . . . . . . . . . . . . . . . . . . 41
10 11
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3/47
1
AGND
PG_1S05
EN_1S8 (S5)
EN_1S05
PG_1S8
SET_PH1
SGND_1S05
VFB_1S05
S S_ 1 S0 5
3.3V 3.3V
COMP_1S05
VSW_1S05
VIN_1S05
4/47
Figure 1.
VTT VTTREF
3.3V
Typical application circuit
Application circuit
5V
VTT
VTTFB
VCC AVCC VIN_1S5
VTTREF
VTTGND
SET_SWF
EN_VTT (S3)
VIN_1S8 VSW_1S5 VSW_1S8 VFB_1S5 VOUT_1S8 SGND_1S5
LDOIN
1.5V
1 . 8V
VFB_1S8 SGND_1S8
Typical application circuit
PM6641
COMP_1S5 SS_1S5 EN_1S5
COMP_1S8
CSNS
3.3V
SS_1S8
AGND
PG_1S5
PG_1S5
1.05V PG_1S8 PG_1S05
PM6641
PM6641
Pin settings
2
2.1
Pin settings
Connections
Figure 2. Pin connection (through top view)
EN_1S8 (S5) VCC VTTFB DSCG VTTREF LDOIN VTT VTTGND AVCC AGND SET_PH1 AGND
AGND SET_SWF VOUT_1S8 CSNS SGND_1S8 SGND_1S8 VSW_1S8 VSW_1S8 VIN_1S8 VIN_1S8 VFB_1S8 COMP_1S8 SS_1S05 SS_1S8
PM6641
EN_VTT (S3) EN_1S5 EN_1S05 VIN_1S5 VSW_1S5 VSW_1S5 SGND_1S5 SGND_1S5 VFB_1S5 COMP_1S5 SS_1S5 PG_1S5 PG_1S05 PG_1S8
VSW_1S05 VSW_1S05 SGND_1S05 SGND_1S05 VFB_1S05 COMP_1S05
VIN_1S05 VIN_1S05
5/47
Pin settings
PM6641
2.2
Pin description
Table 2. Pin functions
N 1 2 3 4 5 6 7 8 9 10 11 Pin AGND SET_SWF VOUT_1S8 CSNS SGND_1S8 SGND_1S8 VSW_1S8 VSW_1S8 VIN_1S8 VIN_1S8 VFB_1S8 Analog and signal ground. Switching Frequency Setting Input. See Chapter 7.8: Switching frequency selection on page 29 VDDQ/2 Divider Input and Discharge path for 1.8 V rail. Current Limit Setting Input for All rails. See Chapter 7.10: Peak current limit on page 31 Switcher power ground for 1.8 V rail. Switcher power ground for 1.8 V rail. Switch node for 1.8 V rail. Switch node for 1.8 V rail. Power supply input for 1.8 V rail. Power supply input for 1.8 V rail. Feedback Input for 1.8 V rail. See Chapter 7.5: Output voltage divider on page 27 Loop Compensation Output for 1.8 V rail. See Chapter 7.3: SW regulators control loop on page 24 and Chapter 8.4: SW regulator compensation components selection on page 38 sections for details. Positive Terminal of the external Soft-Start Capacitor for 1.8 V rail. See Chapter 7.6: Outputs Soft-Start on page 28 section for details. Positive Terminal of the external Soft-Start Capacitor for 1.05 V rail. See Chapter 7.6: Outputs Soft-Start on page 28 section for details. Loop Compensation Output for 1.05 V rail. See Chapter 7.3: SW regulators control loop on page 24 and Chapter 8.4: SW regulator compensation components selection on page 38 for details. Feedback Input for 1.05 V rail. See Chapter 7.5: Output voltage divider on page 27 section for details Switcher power ground for 1.05 V rail. Switcher power ground for 1.05 V rail. Switch node for 1.05 V rail. Switch node for 1.05 V rail. Power supply input for 1.05 V rail. Power supply input for 1.05 V rail. Power-Good Signal for 1.05 V rail. Open Drain. See Chapter 7.2: Chipset supply on page 22 section for details. Power-Good Signal for 1.8 V rail. Open Drain. See Chapter 7.1.1: VDDQ switching regulator on page 20 section for details. Power-Good Signal for 1.5 V rail. Open Drain. See Chapter 7.2: Chipset supply on page 22 section for details. Function
12
COMP_1S8
13 14
SS_1S8 SS_1S05
15
COMP_1S05
16 17 18 19 20 21 22 23 24 25
VFB_1S05 SGND_1S05 SGND_1S05 VSW_1S05 VSW_1S05 VIN_1S05 VIN_1S05 PG_1S05 PG_1S8 PG_1S5
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PM6641 Table 2. Pin functions (continued)
N 26 Pin SS_1S5 Function
Pin settings
Positive terminal of the external Soft-Start Capacitor for 1.5 V rail. See Chapter 7.6: Outputs Soft-Start on page 28 section for details. Loop Compensation Output for 1.5 V rail. Chapter 7.3: SW regulators control loop on page 24 and Chapter 8.4: SW regulator compensation components selection on page 38 sections for details. Feedback Input for 1.5 V rail. See Chapter 7.5: Output voltage divider on page 27 section for details Switcher power ground for 1.5 V rail. Switcher power ground for 1.5 V rail. Switch node for 1.5 V rail. Switch node for 1.5 V rail. Power supply input for 1.5 V rail. Enable input for 1.05 V rail. Enable input for 1.5 V rail. Enable Input for VTT rail. High in S0 System States. See Chapter 7.1.4: S3 and S5 power management pins on page 22 section for details. Enable Input for 1.8 V (VDDQ) rail. High in S0-S3 System States. See Chapter 7.1.4: S3 and S5 power management pins on page 22 section for details. Analog and Signal Ground. Switching Regulator Phase Control. See Chapter 7.9: Phase management on page 30 section for details. Analog and Signal Ground. Analog Circuitry Supply. Connect to +5 V by a simple RC filter. LDO Linear Regulator Power Ground. LDO Linear Regulator Output. DDR2-3 Termination Voltage. See Chapter 7.1: Memory supply on page 20 and Chapter 7.1.2: VTT LDO and VTTREF buffered reference on page 21 sections for details. LDO Linear Regulator Input. Typically connected to the 1.8 V rail. Reference Voltage Buffer Output. See Chapter 7.1: Memory supply on page 20 and Chapter 7.1.2: VTT LDO and VTTREF buffered reference on page 21 sections for details. Tracking/Non-tracking Discharge Selection for DDR2-3 Section. See Chapter 7.7: Outputs Soft-End on page 29 section for details. Feedback Input for VTT Linear Regulator Output. +5 V Switching Circuitry Supply. Bypass to AGND by a 100 nF capacitor.
27
COMP_1S5
28 29 30 31 32 33 34 35 36
VFB_1S5 SGND_1S5 SGND_1S5 VSW_1S5 VSW_1S5 VIN_1S5 EN_1S05 EN_1S5 EN_VTT
37 38 39 40 41 42 43 44 45
EN_1S8 AGND SET_PH1 AGND AVCC VTTGND VTT LDOIN VTTREF
46 47 48
DSCG VTTFB VCC
7/47
Electrical data
PM6641
3
3.1
Electrical data
Maximum rating
Table 3. Absolute maximum ratings (1)
Symbol VVIN VVCC VAVCC VIN_x to SGND_x VCC to AGND or SGND_x AVCC to AGND or SGND_x AGND to SGND_x -0.3 to 0.3 VTTGND to SGND_x VSW_x to SGND_x VVSW -0.3 to 6 VSW_x to AGND CSNS, PG_x, EN_x, DSCG, COMP_x, VFB_x, SS_x, SET_SWF, SET_PH1, VOUT_1S8 to AGND VTT, VTTREF, VTTFB to AGND LDOIN, VTT, VTTREF, VTTFB to VTTGND PTOT Power dissipation @ TA = 25 C 4 W -0.3 to VAVCC + 0.3 V VIN = VAVCC VVCC = VAVCC -0.3 to 6 Parameter Value Unit
1. Free air operating conditions unless otherwise specified. Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
3.2
Thermal data
Table 4. Thermal data
Symbol RthJA TSTG TA TJ Parameter Thermal resistance junction to ambient Storage temperature range Operating ambient temperature range Junction operating temperature range Value 42 -50 to 150 -40 to 85 -40 to 125 Unit C/W C C C
3.3
Recommended operating conditions
Table 5. Recommended operating conditions
Values Symbol VAVCC VVCC VIN AVCC voltage range VCC IC supply voltage VIN_x input voltage range Parameter Min 4.5 4.5 2.7 Typ Max 5.5 VAVCC VVCC V Unit
8/47
PM6641
Electrical characteristics
4
Electrical characteristics
TA = 0 C to 85 C, AVCC = 5 V, VCC = 5 V , VIN_x = 3.3 V and LDOIN connected to 1.8 V output if not otherwise specified, Note:
Table 6. Electrical characteristics
Values Symbol Supply section all rails ICC I SHDN AVCC+VCC operating current Total shutdown current into VIN_x + AVCC + VCC pins AVCC under voltage lockout upper threshold UVLOth AVCC under voltage lockout lower threshold UVLO hysteresis Error amplifier, FB AND SS all rails VREF IFB ISS Error amplifier reference voltage VAVCC = VVCC = 5 V FB input bias current Soft-star t current VFB_X = 0.8 V 792 800 808 25 10 mV nA A VVCC = +5 V , all switching regulators active without load VIN = VAVCC = VVCC = +5 V, all EN_x low 4.0 3.6 100 4.1 3.9 3 10 4.35 V 4.0 mV mA A Parameter Test condition Min Typ Max Unit
VSS_X = 0.4 V
Oscillator frequency RSETSWF = 140 k fSW Switching frequency SET_SWF to VCC RSETSWF = 70 k Comp all rails gm COMP_x Transconductance 300 S 675 500 750 1000 825 kHz
UVP/OVP protectionS and PGOOD signal (SMPS only) all rails OVPth UVPth PGth IPG,LEAK VPG,LOW Overvoltage threshold Undervoltage threshold Power-good upper threshold Power-good lower threshold PG_x Outputs Leakeage Current PG_x Outputs Low Level PG_x tied to +5 V VFB_X = 0.6 V or 1V, IPG_X = 2 mA 116 56 106 86 120 60 110 90 124 64 % 115 94 1 250 uA mV
Note:
All parameters at operating temperature extremes are guaranteed by design and statistical analysis (not production tested).
9/47
Electrical characteristics Table 6. Electrical characteristics (continued)
Values Symbol Thermal shutdown Thermal shutdown threshold T SHDN Thermal shutdown hysteresis 150 Parameter Test condition Min Typ
PM6641
Unit Max
C 15
Switching node chipset 1.5 V rail tOnmin Minimum On-Time High side PMOS Ron Low side NMOS Ron VAVCC = VVCC = +5 V, all EN_1S5 low RCSNS = 50 k VIN = +5 V 1 VIN = +3.3 V 3.9 A 200 150 100 220 160 ns m
R DSon, HS R DSon ,LS
IINLEAK
VIN_1S5 leakage current
A
Peak current limit Soft end section chipset 1.5 V rail Discharge resistance LS Turn-on VFB_1SX Threshold with internal divider LS Turn-on VFB_1SX Threshold with external divider
25 VFB_S1X to OUT_X VFB_S1X to external dvider 0.29
V 0.16
Power management section chipset 1.5 V rail EN_1S5 Turn-Off level EN_1S5 Turn-On level Switching node chipset 1.05 V rail tOnmin Minimum On-Time High side PMOS Ron Low side NMOS Ron VIN_1S05 leakage current VAVCC = VVCC = +5 V, all EN_1S05 low RCSNS = 50 k VIN = +5 V VIN = +3.3 V 5.1 180 100 70 160 110 1 A 1 A ns m VAVCC = 5 V 0.8 V 2
R DSon, HS R DSon ,LS
IINLEAK
Peak current limit
10/47
PM6641 Table 6. Electrical characteristics (continued)
Electrical characteristics
Values Symbol Parameter Test condition Min Soft end section chipset 1.05 V rail Discharge resistance LS Turn-on VFB_1SX Threshold with internal divider LS Turn-on VFB_1SX Threshold with external divider VFB_S1X to OUT_X VFB_S1X to external divider 25 0.2 V 0.16 Typ Max Unit
Power management section chipset 1.05 V rail EN_1S05 Turn-Off level EN_1S05 Turn-On level Switching node DDR2/3 rails tOnmin Minimum On-Time High side PMOS Ron Low side NMOS Ron VAVCC = VVCC = 5 V, all EN_1S8 low RCSNS = 50 k VIN = +5 V VIN = +3.3 V 6.1 200 90 80 130 120 1 A 1 A ns m VAVCC = +5 V 0.8 V 2
R DSon, HS R DSon ,LS
IINLEAK
VIN_1S8 leakage current
Peak current limit Soft end section DDR2/3 rails VDDQ discharge resistance in non-tracking discharge mode VTTREF discharge resistance in non-tracking discharge mode VTTFB discharge resistance in non-tracking discharge mode
25 200 40
VFB_1SX Threshold for final tracking/Non-tracking discharge VFB_S1X to OUT_X transition with internal divider VFB_1SX Threshold for final tracking/Non-tracking discharge VFB_S1X to external divider transition with external divider
0.340
V
0.160
V
11/47
Electrical characteristics Table 6. Electrical characteristics (continued)
Values Symbol Parameter Test condition Min Power management section DDR2/3 rails DSCG Turn-Off Level DSCG Turn-On Level EN_1S8 (S5), EN_VTT (S3) Turn-Off Level EN_1S8 (S5), EN_VTT (S3) Turn-On Level VTT LDO section DDR2/3 rails Power-good upper threshold
PG_VTT_TH
PM6641
Unit Typ Max
VAVCC = +5 V
1.5 3.5 0.8 V
VAVCC = +5 V 2
106 86 EN_1S8 = EN_VTT = +5 V, No Load on VTT EN_1S8 = +5 V, EN_VTT = 0 V, No Load on VTT EN_1S8 = EN_VTT = 0 V, No Load on VTT EN_1S8 = EN_VTT = +5 V, VVTTFB = VVOUT_1S8 /2 EN_1S8 = +5 V, EN_VTT = 0 V, VVTTFB = VVOUT_1S8 /2 EN_1S8 = +5 V, EN_VTT = 0 V, VVTT = VVOUT_1S8 /2 EN_1S8 = EN_VTT = +5 V, IVTT 0 A, VLDOIN = 1.8 V EN_1S8 = EN_VTT = +5 V, IVTT = 0 A, VLDOIN = 1.5 V EN_1S8 = EN_VTT = +5 V, -1 mA < IVTT < 1 mA -20 -25 -35 -10
110 90 1
114 94 10 10 3 1 1 10
% %
Power-good lower threshold ILDOIN,ON ILDOIN,STR ILDOIN,STD LDO input bias current in fullON State LDO input bias current in suspend-To-RAM State LDO input bias current in suspend-To-Disk State
A
IVTTFB, BIAS VTTFB bias current IVTTFB, LEAK VTTFB leakage current IVTT,LEAK VTT leakage current LDO linear regulator output voltage (DDR2) LDO linear regulator output voltage (DDR3) VVTT
A
0.9 V 0.75 20 25 35 mV
LDO Output accuracy respect to EN_1S8 = EN_VTT = +5 V, -1 A < IVTT < 1 A VTTREF, VLDOIN =1.8 V EN_1S8 = EN_VTT = +5 V, -2 A < IVTT < 2 A
12/47
PM6641 Table 6. Electrical characteristics (continued)
Electrical characteristics
Values Symbol Parameter Test condition Min LDO source current limit IVTT,CL LDO sink current limit VTTREF section DDR2/3 rails VTTREF output voltage VVTTREF VTTREF output voltage accuracy relative to VVOUT_1S8/2 VTTREF short circuit source current IVTTREF VTTREF short circuit sink current IVTTREF = 0A, VVOUT_1S8 = 1.8 V -15 mA < IVTTREF < +15 mA, VVOUT_1S8 = 1.8 V VVOUT_1S8 =1.8 V, VVTTREF = 0 V VVOUT_1S8 =1.8 V, VVTTREF = 1.8 V -2 0.9 2 V % VVTT < 1.10*( VVOUT_1S8 /2) VVTT > 1.10*( VVOUT_1S8 /2) VVTT > 0.90*( VVOUT_1S8 /2) VVTT < 0.90*( VVOUT_1S8 /2) 2 1 -3 -1.5 Typ 2.3 1.25 -2.3 -1.25 Max 3 1.5 A -2 -1 Unit
40 mA -40
13/47
Typical operating characteristics
PM6641
5
Figure 3.
Typical operating characteristics
VDDQ and VTT Soft-Start without load Figure 4. VDDQ and VTT Soft-Start with AVG load
Figure 5.
1V5 Soft-Start without load
Figure 6.
1V5 Soft-Start with load
Figure 7.
1V05 Soft-Start without load
Figure 8.
1V05 Soft-Start without load
14/47
PM6641
Typical operating characteristics
Figure 9.
VDDQ output ripple and phase @ AVG current
Figure 10. VTT, VTTREF output ripple @ AVG current
Figure 11. 1V5 output ripple and phase @ AVG current
Figure 12. 1V05 output ripple and phase @ AVG current
Figure 13. SW reg. efficiency @ VIN = 3.3 V, FSW = 600 kHz
95 90 85 80 75 70 65 65 1,0E-03 1V8 1V5 1V05 1,0E-02 1,0E-01 Load Current [A] 1,0E+00 1,0E+01
Figure 14. VDDQ (1.8 V) load regulation
1,808 1,806 1,804
Output voltage (V)
1,802 1,800 1,798 1,796 1,794 1,792 1,790 1,788 0,00 1V 8
Efficiency %
0,50
1,00
1,50
2,00
L oa d C ur r e n t [ A ]
2,50
3,00
3,50
4,00
15/47
Typical operating characteristics
PM6641
Figure 15. 1.5 V load regulation
1,536 1,534
Output voltage (V)
Figure 16. 1.05 V load regulation
g
1,053 1,052 1,051 1,050 1,049 1,048 1V05
1,532 1,530 1V5 1,528 1,526 1,524 1,522 0,00
Output Voltage [V]
0,50
1,00
Load Current [ A]
1,50
2,00
2,50
1,047 0,00 0,50 1,00 1,50 2,00 2,50 3,00 3,50
Load Current [A]
Figure 17. VDDQ (1.8 V) load transient: 0-AVG
Figure 18. VTT load transient: -1 A +1 A
Figure 19. 1V5 load transient: 0-AVG
Figure 20. 1V05 load transient: 0-AVG
16/47
PM6641 Figure 21. VDDQ e VTT Soft-end with DSCG = AVCC
Typical operating characteristics Figure 22. VDDQ e VTT Soft-end with DSCG = AGND
Figure 23. Current limit
Figure 24. Soft-OV (1V05)
Figure 25. Output OV (1V5) @ RCSNS = 1 M
Figure 26. Output UV (1V5)
Note:
All the above measures and screen captures are based on PM6641EVAL evaluation board. Refer to PM6641 Evaluation Kit for details.
17/47
Block diagram
PM6641
6
Block diagram
Figure 27. Functional and block diagram
VCC VIN_1S8
ANT I X COND
PG_1S8
+ _ + _
VREF+10%
VIMAX ASM
VREF-10%
0.9V
VTTREF VTTFB LDOIN
Z ERO CROSS & VALLEY C.L.
VSW _1S8
1.237V
VREF = 0.8V
VIMIN _
HiZ PE AK CURR. LIMIT
VTT
+ + R
NT D EN
SGND_1S8
VTTGND
R
_
NT D
VIMAX
COMP_1S8 gm VFB_1S8
VREF _ _ + + _ VREF
VOUT_1S8 SET_PH1
+ _
0. 9V ?3 PULSE SKIP
VIMIN OSC
SS CONTROL ?1 ?2
SS_1S8
SET_SW F VIN_1S05
ANT I X COND
VIN_1S5
ANT I X COND
SW _1S05
Z ERO CROSS & VALLEY C.L.
ASM
ASM
Z ERO CROSS & VALLEY C.L.
VSW _1S5
PEAK CURR. LIMIT
PE AK CURR. LIMIT
SGND_1S05
+ + _ VIMAX
SGND_1S5
COMP_1S05 COMP_1S05
_ _
VIMAX
_
COMP_1S5 gm VFB_1S5
VFB_1S05
VREF
gm
PULSE SKIP OV P UV P PULSE SKIP
SS_1S05
SS CONTROL
VREF+10%
PG_1S05
+ _ + _
VREF-10%
OV P UVP UV L O OV P UV P
Table 7. Legend
TD NTD EN HiZ Tracking discharge enable Non-tracking discharge enable VTTREF buffer enable LDO high impedance mode enable
18/47
+ VIMIN
EN HiZ
VIMIN
TD THERM AL PROTECTION NT D SS CONTROL
SS_1S5
CONT ROL LOGIC
VREF+10%
+ _ + _
VREF-10%
PG_1S5
CSNS
DSCG
AVCC
PM6641
Device description
7
Device description
The PM6641 is an integrated Voltage Regulator Module designed to supply DDR2/3 memory and Chipset I/O in real estate constrained portable equipment and ultra-mobile PCs. The device consists of three buck regulators (two for Chipset Supply and one for main DDR Supply), a Low Drop-Out (LDO) Linear Regulator capable of 2 Apk (DDR Termination Voltage) and a low noise buffered reference (DDR Input Buffer Reference). It has been developed for single-series Li-Ion battery stack powered equipment, allowing an input power supply from 2.7 V up to 5.5 V. The PM6641 provides a compact solution by integrating DDR and Chipset voltage regulators on a single IC with internal power MOSFETs and requiring a minimum number of external components. All its buck regulators are based on a Current-Mode control scheme with integrated features to guarantee stability and fast load transient response. Each regulator output voltage can be adjusted or a pre-fixed output voltage can be chosen, if external components are unwanted. Each switching regulator has independent programmable soft-start, to reduce inrush current, and output soft-end, to avoid inductor and MOSFETs high peak current. Other buck regulators features include output Over-Voltage and Under-Voltage Protections, programmable current limit and output Power-Good signals. High efficiency is achieved over a wide range of load conditions by using a Pulse-Skipping technique at light load. The PM6641 can detect the AVCC pin under-voltage through the Under-Voltage Lock-Out (UVLO) block and it is able to limit its internal temperature through its auto-recovery Thermal Shutdown. The switching frequency of the buck controllers can be set in the range 500 kHz-1 MHz with an external resistor or can be set equal to 750 kHz without external components use. All buck regulators work at the same switching frequency with selectable Phase Shift. The regulators can support both electrolytic and ceramic output capacitors because no minimum output voltage ripple is required for stability purposes. The PM6641 is provided in a QFN7x7mm 48-pin lead-free package.
19/47
Device description
PM6641
7.1
Memory supply
The DDR2/3 section of PM6641 is based on the VDDQ rail, the VTT termination rail and the VTTREF reference voltage buffer. The VDDQ rail is provided by a step-down switching regulator whose output voltage, by default, is set to 1.8 V, in order to be compliant with DDR2 JEDEC specs. The output voltage can also be adjusted using an external resistor divider. This rail performs latched Output Under-Voltage and Over-Voltage and auto-recovery Current Limit, without requiring external sensing resistor. The VTT termination rail is supplied by a Low Drop-Out (LDO) Linear Regulator, able to sink and source up to 2 A peak current. This regulator follows the half of the VDDQ rail and is a replica of the VTTREF reference voltage buffer. When LDOIN is directly supplied by VDDQ, i.e. the PM6641 1S8 rail, VTT and VDDQ can perform the so called Tracking Discharge, in compliance with the JEDEC specs, as described in the following section. If higher efficiency is required, VTT can be supplied by a lower voltage rail. An output capacitor of at least 20 F is the only external component required. The VTTREF reference voltage buffer is always in tracking with the half of VDDQ and is able to sink and source up to 15mA with an accuracy of 2 % relative to VDDQ half. A 10 nF up to 100nF bypass capacitor for stability purposes is required.
7.1.1
VDDQ switching regulator
The VDDQ rail is provided by a constant frequency current-mode buck regulator, whose frequency is set by inserting an external resistor between SET_SWF pin and AGND (see Chapter 7.8: Switching frequency selection on page 29 section for details). The output voltage can easily be set to 1.8 V by connecting the feedback pin VFB_1S8 directly to the output rail, avoiding the use of external components. However, if a different output voltage is desired, the VFB_1S8 pin must be connected to the central tap of a resistor divider. The output voltage can be adjusted from 0.8V up to the input voltage value, decreased by a drop due to the high-side MOSFET on resistance. (see Chapter 7.5: Output voltage divider on page 27 section for details). The control loop needs to be compensated by inserting a resistor-capacitor series connected between the COMP_1S8 pin and ground; if electrolytic capacitor with relevant equivalent series resistance (ESR) are used, an additional capacitor between the COMP_1S8 pin and ground can be useful (see Chapter 7.3: SW regulators control loop on page 24 section for details). The classical slope compensation is internally implemented and no external components are required. The internal High-Side PMOS and Low-Side NMOS allow the regulator to source an average current of 2.8 A and a peak current of 5 A. The peak current limit protection is performed by sensing the internal high side MOSFET current and can be decreased by inserting an external resistor between CSNS pin and AGND (see Chapter 7.10: Peak current limit on page 31 section for details). This 1S8 rail is able to protect the load from Over-Voltage and Under-Voltage protection, which avoid the output to be higher than 120 % or lower than 60 % of the nominal value (see Chapter 7.11.1: Output over voltage on page 33 and Chapter 7.11.2: Output under voltage on page 33 section for details). When the EN_1S8 pin goes high the VDDQ rail is turned on and the output voltage soft-start is performed by slowly charging the rail output capacitor; this behavior is achieved because
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PM6641
Device description the loop voltage reference is increased linearly from zero up to 0.8V in a long time (up to a couple of milliseconds) (see Chapter 7.6: Outputs Soft-Start on page 28 for details). When the EN_1S8 pin goes low, the VDDQ rail output capacitor is discharged through internal discharge MOSFET and, at the end of the capacitor discharge, the low side power MOSFET is eventually closed (see Chapter 7.7: Outputs Soft-End on page 29 for details). The Power Good Signal (PG_1S8 pin) is an open drain output, shorting the output to GND in the following conditions:
When the 1.8 V rail output voltage is outside +/- 10 % range from nominal value When a protection (UV, OV, thermal) has been triggered When the regulator is in soft-start.
When VDDQ and VTT rails are enabled, PG_1S8 is left floating and, as a consequence, pulled-up by the external pull-up resistor, if both the rails are inside +/- 10 % range of nominal value. The PG_1S8 pin can sink current up to 4mA when it's asserted low.
7.1.2
VTT LDO and VTTREF buffered reference
The PM6641 provides the required DDR2/3 reference voltage on VTTREF pin. The internal buffer tracks half the voltage on VOUT_1S8 pin and has a sink and source capability up to 15mA with an accuracy of 2 % referred to the VDDQ half. Higher currents rapidly deteriorate the output accuracy. A 10 nF to 100 nF (33 nF typical) bypass capacitor to SGND is required for stability. The VTT Low-Drop-Out linear regulator has been designed to sink and source up to 2 A peak current and 1 A continuously. The VTT voltage tracks VTTREF within 35 mV. A remote voltage sensing pin (VTTFB) is provided to recovery voltage drops due to parasitic resistance. In DDR2/3 applications, the linear regulator input LDOIN is typically connected to VDDQ output; connecting LDOIN pin to a lower voltage (if available in the system) reduces the power dissipation of the LDO, but a minimum drop-out voltage must be guaranteed, depending on the maximum current expected. A minimum output capacitance of 20 uF (2x10 uF or single 22 uF ceramic capacitors) is enough to assure stability and fast load transient response. According to DDR2/3 JEDEC specifications, when the system enters the Suspend-To-RAM state (S5 high and S3 low) the LDO output is left in high-impedance while VTTREF and VDDQ are still alive. When the Suspend-To-Disk state (S3 and S5 tied to ground) is entered, all outputs are actively discharged by a tracking or a non-tracking discharge as selected through the DSCG pin (see Chapter 7.7: Outputs Soft-End on page 29 for details).
7.1.3
VTT and VTTREF Soft Start
Soft-Start on VTT and VTTREF outputs is achieved by current clamping. The LDO linear regulator is provided of a current fold-back protection: when the output voltage exits the internal 10 % VTT-Good window, the output current is clamped at 1 A. Re-entering VTTGood window releases the current limit clamping. The fold-back mechanism naturally implements a two steps soft-start charging the output capacitors with a 1 A constant current. Something similar occurs at VTTREF pin, where the output capacitor is smoothly charged at a fixed 40 mA (typ) current limit.
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Device description
PM6641
7.1.4
S3 and S5 power management pins
According to DDR2/3 memories supply requirements, the PM6641 can manage all S0 to S5 system states just connecting EN_VTT EN_1S8 pins to their respective sleep-mode signals in the notebook's motherboard: connect EN_1S8 to S5 and EN_VTT to S3. Keeping EN_VTT and EN_1S8 high, the S0 (Full-On) state is decoded and the outputs are alive. In S3 state (EN_1S8=1, EN_VTT =0), the PM6641 maintains VDDQ and VTTREF outputs active and VTT output in high-impedance as needed. In S4/S5 states (EN_1S8= EN_VTT =0) all outputs are turned off and, according to DSCG pin voltage, the proper Soft-End is performed (see Chapter 7.7: Outputs Soft-End on page 29 section for details). The following table resumes the DDR power supply states. Table 8. S3 and S5 sleep-states decoding
S3 (EN_VTT) S5 (EN_1S8) 1 0 0 1 1 0 System state S0 (Full-On) S3 (Suspend-To-RAM) VDDQ On On VTTREF On On VTT On Hi-Z
S4/S5 Off (Discharge) Off (Discharge) Off (Discharge) (Suspend-To-Disk)
7.2
Chipset supply
The chipset power supply section is based on two constant frequency current-mode buck regulators with a pre-fixed output voltage of 1.5 V and 1.05 V. These two independent rails have programmable switching frequency, set by inserting an external resistor between SET_SWF pin and AGND. The PM6641 allows also to manage the switching regulators phases for 1.5V, 1.05V and 1.8V (VDDQ) rails in order to limit the RMS input current (see Chapter 7.8: Switching frequency selection on page 29 and Chapter 7.9: Phase management on page 30 section for details). The output voltages can easily be set to the pre-fixed value by connecting the feedback pins VFB_1S5 and VFB_1S05 directly to the respective output rail, avoiding the use of external components. However, if a different output voltage is desired, the feedback pins can be independently connected to the central tap of a resistor divider. The output voltage can be adjusted from 0.8V up to the input voltage value, decreased by a drop due to the high-side MOSFET on resistance. (see Chapter 7.5: Output voltage divider on page 27 section for details). Both regulators are current-mode step-down switching regulators whose control loop needs to be compensated by inserting a resistor-capacitor series connected between the compensation pin (COMP_1S5 and COMP_1S05) and ground; if electrolytic capacitor with relevant equivalent series resistance (ESR) are used, an additional capacitor between this compensation pin and ground can be useful (see Chapter 7.3: SW regulators control loop on page 24 section for details). The classical slope compensation, which allows the peak current mode loop to avoid sub-harmonic instability with duty cycle greater than 50%, is internally implemented and no further external components are required.
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PM6641
Device description The chipset supply is able to source the following average and peak currents, , assuming 1 A peak-to-peak inductor current ripple: Table 9. Chipset supply currents
Chipset supply rail [V] 1.5 1.05 Average current [A] 1.5 2.1 Peak current [A] 3.0 4.0
The peak current and the inductor ripple must be carefully evaluated in order to choose the right current limit protection; this feature is performed by sensing the internal high side MOSFET current and can be decreased by inserting an external resistor between CSNS pin and AGND (see Chapter 7.10: Peak current limit on page 31 for details). Both rails are able to protect the load from Over-Voltage and Under-Voltage protection, which avoid the output to be higher than 120% or lower than 60% of the nominal value (see Chapter 7.11.1: Output over voltage on page 33 and Chapter 7.11.2: Output under voltage on page 33 section for details). When the EN_1S5 or EN_1S05 pin goes high the respective rail is turned on and the output voltage soft-start is performed by slowly charging the rail output capacitor; this behavior is achieved because the loop voltage reference is increased linearly from zero up to 0.8V (see Chapter 7.6: Outputs Soft-Start on page 28 section for details). When the EN_1S5 or EN_1S05 pin goes low, the respective rail output capacitor is discharged through internal discharge MOSFET and, at the end of the capacitor discharge, the low side power MOSFET is finally closed (see Chapter 7.7: Outputs Soft-End on page 29 section for details). Each rail has a dedicated pin to assert if its output voltage is not in the power good window, i.e. if the output voltage drops 10% below or rises 10% above the nominal regulated value. These Power Good Signals (PG_1S5 and PG_1S05 pins) are open drain outputs, tied to GND in the following conditions:
When the rail output voltage is outside +/- 10 % range from nominal value When a protection (UV, OV, thermal) has been triggered When the regulator is in soft-start.
The PG_1S5 and PG_1S05 pins can sink current up to 4 mA when it's asserted low.
23/47
Device description
PM6641
7.3
SW regulators control loop
The PM6641 switching regulators are buck converters employing a constant frequency, peak current mode PWM control loop, as shown in the following figure: Figure 28. SW Regulator Control Loop
Power Stage
IL
VO
RES CO
RO
a
KL
VC CRO RC CC
Signal Stage
gm gm VREF
In the current mode constant frequency loop the Power Stage is represented by a controlled current generator feeding the power stage output capacitor and load. The equivalent transfer function is: Equation 1
H(s) =
(sCORES + 1) R VO (s) = O IL (s) sC O (RES + R O ) + 1
with Co and Res being the output capacitance and its equivalent series resistance and Ro representing the output load.
24/47
PM6641
Device description
In order to obtain the typical integrative loop transfer function the signal stage must compensate for the power stage pole (due to the output capacitor and the load) and zero (above the loop bandwidth if ceramic output capacitors are selected). The signal stage transfer function is:
Equation 2
G(s) = gmK L
sC CR C + 1 C sC C sCRoR C + Ro + 1 CC
Where gM is the power stage transconductance, KL is a design parameter and is the gain due to the output resistor divider (0.8V / Vout). The external compensation network (Rc, Cc and CRO) introduces:
One zero, to compensate the power stage pole: CCR C = C O (R O + RES ) One pole in order to delete the static output voltage error; One pole, if necessary, in order to compensate the high frequency zero due to the output capacitor ESR: CRORC = C ORES
The control loop gain is obtained by multiplying G(s) by H(s):
Equation 3
GLOOP (s) = g mK L
(sC CR C + 1)
C sC C sCRoR C + Ro + 1 CC
(sC ORES + 1) R O sC O (RES + R O ) + 1
This model provides good results if the control loop cut-off frequency fCO is lower than about fsw/10.
25/47
Device description
PM6641
7.4
SW regulators pulse skipping and PWM mode
In order to enhance the light load efficiency each switching regulator enters the Pulse Skipping algorithm when the output current sourced is too low. The threshold load current which allows the regulator to enter the pulse skipping mode can be estimated with the following formula: (Vi-Vo)/(2Lfsw)*Vo/Vi
Equation 4
( VI VO ) VO Iomin ----------------------- ------( 2 L fS W ) VI
When the load current is lower than IOmin value, the switching regulator begins to skip some cycle, decreasing the effective switching frequency and, as a consequence, reducing the switching losses. This mode of operation is guaranteed by the presence of the zero crossing current comparator, the internal block which senses the inductor current and avoids this current to becoming negative, in the normal operating condition. The inductor current is allowed to become negative when the output voltage rises above the +10% power good threshold. In this condition of output soft over voltage the zero crossing current comparator is deactivated and the pulse skipping algorithm is replaced by the typical PWM one; as a consequence each switching regulator can sink up to some hundreds milliamps to decrease the output voltage to the nominal value.
Figure 29. SW regulators pulse skipping and PWM mode
Vout Vout
IL
IL
Clock
Clock
a) Pulse Skipping Mode
b) PWM Mode
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PM6641
Device description
7.5
Output voltage divider
PM6641 switching regulators are adjustable voltage converters. If the feedback pin (VFB_1S8, VFB_1S5, VFB_1S05 respectively belonging to VDDQ (1.8 V), 1.5 V, 1.05 V rail) is directly tied to the rail output capacitor the internal divider with pre-fixed output voltage value is activated and the nominal output voltages are selected. If the feedback pin is connected to the output voltage divider central tap (as depicted in Figure 30)
Figure 30. SW regulator with external divider
Vout_1Sxx R1 V F B _ 1 S xx R2
the PM6641 switching regulator automatically recognizes the external divider and the output voltage is regulated to the following value:
Equation 5
R Vout _ 1Sxx = 1 + 1 0.8V R 2
27/47
Device description
PM6641
7.6
Outputs Soft-Start
The soft start function of each switching regulator is achieved by ramping up the SS pin voltage with a constant slew rate dV/dt. When the switching section is enabled (EN high), the SS pin constant current charges the capacitor connected between SS and ground pins. The SS voltage is used as reference of the switching regulator and the output voltage of the converter follows the ramp of the SS voltage. When the SS pin voltage is higher than 0.8 V, the error amplifier will use the internal 0.8 V 1 % reference to regulate the output voltage.
Figure 31. SW regulator programmable Soft-Start
Iss SS_1Sx SW Regulator SS DO VREF
During the soft start period the current limit is set to the nominal value. The dV/dt slope is set by charging the external capacitor with a 10 A current. The capacitance values will be of the order of magnitude of 10 nF for a 1 msec soft-start duration, as pointed out by the following formula:
Equation 6
C=
I t 10A 1ms = = 12.5nF V 0. 8 V
During the soft-start the output under voltage management is not enabled, whereas the output over voltage, the current limit and the thermal overheat are always monitored. When the first switching regulator is turned on the output soft-start begins after an additional delay of about 180 s, due to PM6641 initializing and fuses reading.
28/47
PM6641
Device description
7.7
Outputs Soft-End
When the switching regulator enable pin (EN_1S8 for the VDDQ section, EN_1S5 and EN_1S05 for chipset sections) goes down or when UV or thermal protections are detected, the switching regulator output capacitor is actively discharged through a dedicated discharge MOSFET of about 25 typical resistance. The PM6641 DDR supply allows choosing between two different output discharge behaviors, involving the VDDQ (1S8) switching rail, VTT LDO termination and VTTREF reference buffered voltage: the tracking discharge and the non-tracking discharge. This selection is set by tying the Discharge pin (DSCG) to AVCC (tracking discharge enabled) or to AGND (tracking discharge disabled). When the 1.8 V rail is turned off (EN_1S8 goes low) and non-tracking discharge is active (DSCG is low), or when UV or thermal protections are detected, the VDDQ and VTT rails and the VTTREF buffer are discharged by internal discharge MOSFETs, through the VSW_1S8, VTTFB and VTTREF pins respectively. VTT termination output capacitor is discharged through 25 dedicated MOSFET whereas VTTREF output capacitor is discharged through 200 dedicated MOSFET. When the 1.8 V rail is turned off (EN_1S8 goes low) and tracking discharge is selected (DSCG is high), tracking discharge takes place:
The 1.8 V rail regulator is discharged by internal MOSFET The 0.9 V VTT LDO and VTTREF work in tracking with the half of 1.8 V rail
When the VTT LDO and VTTREF reach a voltage threshold of about 200-300 mV, the device switches to non-tracking discharge mode and the internal discharge MOSFETs are turned on.
7.8
Switching frequency selection
SET_SWF (pin 2) allows to vary the internal oscillator switching frequency, in the range of 1 MHz, by connecting this pin to AGND through a resistor between 500 kHz 70 k 140k . The following table summarizes the output resistor switching frequency correspondence:
Table 10. Typical values for switching frequency selection
RSET_SWF (k) 140 100 70 Approx. switching frequency (kHz) 500 670 1000
When SET_SWF is tied to AVCC the internal reference is chosen and each regulator performs a typical 750 kHz switching frequency.
29/47
Device description
PM6641
7.9
Phase management
When all the three switching regulators high side MOSFETs are turned on simultaneously the input root mean square (RMS) current could rise up to very high values, increasing the system losses and inducing external components overheating. It's possible to reduce the input overall RMS current by inserting one ceramic capacitor as close as possible to each switching regulator power supply input, reducing the impulsive input current path. However this synchronous mode of operation is jitter-free and noise immune. Another possible way to reduce the input RMS current is based on the phase shifting technique, which decreases the total input current by delaying the regulators turn on pulse. With three regulators turned on, the 120d eg phase shifting allows to reduce the overall input current up to 1.73 times as depicted in the following configuration, in which three independent regulators with Vout/Vin lower than 0.333 and identical output current (I) are managed with synchronous or 120 deg phase shifted turning on.
Figure 32. SW regulator phase management
IL1
IL1
IL2
+ + =
+ + =
ICIN
IL2
IL3
IL3
ICIN
Synchronous
120deg delay
Each regulator RMS input current is easily computed:
Equation 7
IL1,L 2,L 3 =
1 TSW
TSW
I
2 L1,L 2,L 3 dt
=
1 TSW
I2 TON
defining TSW the switching period, equal to 1 f SW time.
and TON the high side MOSFET on
30/47
PM6641
Device description
The synchronous mode of operation provides the following total input current:
Equation 8
ICIN,SYNC =
1 TSW
TSW
(I
L1
+ IL 2 + IL 3 ) dt =
2
1 TSW
(3I)2 TON
whereas by shifting the three regulator turn on pulses of 120 deg the resulting total input current is given by
Equation 9
ICIN,DELAY =
1 TSW
TSW
(I
L1
+ IL 2 + IL 3 ) dt =
2
1 TSW
(I
2
+ I2 + I2 TON
)
that is
3 1.73 times smaller than the one computed before.
The PM6641 SET_PH1 pin, if tied to AVCC, enables the synchronous switching regulators high side MOSFET turn on, whereas if tied to ground enables the 120 deg phase shifting.
7.10
Peak current limit
The peak current limit performed by the PM6641 switching regulators allows to monitor, cycle by cycle, the inductor current; this feature prevents IC wire bonding overheating and failure. If the current sensed on the monolithic high side MOSFET reaches the programmed current limit the regulator starts behaving like a current generator, more than a voltage regulator. Consequently, if the output load still increases the rail output capacitor discharges itself and the regulator works as current generator until the Output Under Voltage occurs and the regulator is latched off (see Chapter 7.11.2: Output under voltage on page 33 section for details). The pin 4 (CSNS) allows to select the right value for the peak current limit by inserting an external resistor (RCSNS ) between this pin and ground. CSNS forces a constant voltage on RCSNS resistor or, when tied to AVCC, enables the internal reference (equal to a 50 k external resistor). A simple equation shows how to compute the right value for RCSNS in order to decrease the peak current limit:
Equation 10
RCSNS =
VREF ICL
31/47
Device description
PM6641
where VREF = 0.9V is the constant voltage forced by CSNS pin, RCSNS [] is the resistor connected between CSNS and AGND, is the coefficient that collects the MOS current sensing scaling factor and other design parameters and ICL is the peak current limit [A].
The following table resumes values for all the switching regulators.
Table 11. Typical SW regulators values
SW regulator 1.8V 1.5V 1.05V
333x10e3 222x10e3 278x10e3
The following graph is a plot of the switching regulators peak current limit, increasing the RCSNS resistor:
Figure 33. SW regulators peak current limit
7.00 6.00 CL_1V8 5.00 Current Limit [A] 4.00 3.00 2.00 1.00 0.00 40 60 80 100 120 140 160 180 Rcsns [kOhm] CL_1V5 CL_1V05
From the previous plot and table it's clear that the three regulators peak current limits are scaled; by changing the RCSNS external resistor the three peak current limits all change.
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PM6641
Device description
7.11
Fault management
PM6641 has been conceived to constantly monitor the rails output voltage. In order to protect itself from failure and the load from damage, the device is able to:
Limit the power MOSFETs current Detect output over voltage Detect output under voltage Monitor the device temperature Detect input power supply under voltage
The current limit is an auto-recovery protection, monitoring cycle by cycle the regulators high side MOSFET current (see Chapter 7.10: Peak current limit on page 31 section for details). The output Over Voltage and Under Voltage and the input Under Voltage are latched protections, whereas the thermal shutdown is auto-recovery; all these features are described in the following sections.
7.11.1
Output over voltage
If the output voltage of a switching regulator (memory supply rail VDDQ (1.8 V), chipset supply rails 1.5 V or 1.05 V) becomes greater than 120 % of its nominal value, an over voltage (OV) protection for that rail is triggered. As a consequence the regulator stops switching, the internal low-side power MOSFET of that rail is turned on and the high-side MOSFET is turned off. The OV protection effect is the very quick discharge of the rail output capacitor. The OV condition is latched, and it can be reset only by toggling the enable pin of that rail or by turning off and on the IC power supply (AVCC pin). An OV condition for one of the outputs of the PM6641 has no effect on the operation of the other outputs (e.g., if the OV protection is triggered for the VDDQ regulator, the 1.5 V and 1.05 V regulators continue to work normally).
7.11.2
Output under voltage
If the output voltage of a switching regulator (memory supply rail VDDQ (1.8 V), chipset supply rails 1.5 V or 1.05 V) becomes lower than 60 % of its nominal value (e.g. because the rail was shorted to ground or the output load is increased dramatically), an under voltage (UV) protection for that rail is triggered. An UV condition causes the soft-end of the rail, which implies the regulator turn off and the rail discharge MOSFET turn on (see Chapter 7.7: Outputs Soft-End on page 29 section for details); the UV condition is latched, and it can be reset only by toggling the enable pin of that rail or by turning off and on the PM6641 power supply (AVCC pin). As for OV protection, each switching regulator can perform under voltage protection without affecting other regulators. The over-current feature is implemented in the PM6641 by limiting the output current of each rail (see Chapter 7.10: Peak current limit on page 31 section for details) and triggering a latched UV protection if the output voltage falls because of a load requesting more current than the limit.
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Device description
PM6641
7.11.3
Thermal shutdown
If the device temperature exceeds 150 C, a thermal protection is triggered. As a consequence, the Output Soft End takes place for all the outputs of the PM6641 (VDDQ rail (1.8 V), VTT, VTTREF, 1.5 V, 1.05 V) by closing the output discharge MOSFET (see Chapter 7.7: Outputs Soft-End on page 29 section for details) . The thermal protection condition is not latched: the device leaves this condition and reactivates itself automatically when its temperature falls below 135 C (i.e. there is a 15 C of hysteresis).
7.11.4
Input under voltage lock-out
The PM6641 AVCC pin is the device power supply input. This pin must be fed with 5 V, 10 % in order to allow the device to work properly. If this rail falls under 3.9 V typical threshold, the input under voltage is detected and the device performs the Under Voltage Lock-Out (UVLO) protection. When this event occurs, each regulator stops switching and the following actions are performed:
The memory supply rails (VDDQ, VTT and VTTREF) are discharged by closing the output discharge MOSFET (see Chapter 7.7: Outputs Soft-End on page 29 section for details); Chipset power supply output rails (1V5 and 1V05 rails) are discharged through the low side power MOSFETs; The device is turned OFF.
The PM6641 is turned on again when the AVCC pin voltage reaches the UVLO on threshold (about 4.1 V).
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PM6641
Components selection
8
Components selection
The PM6641 switching regulator sections are buck converters employing a constant frequency, current mode PWM current loop (see Chapter 7.3: SW regulators control loop on page 24 section for details). The duty-cycle of the buck converter is, in steady-state conditions, given by
Equation 11
D=
VOUT VIN
The switching frequency directly affects two parameters:
Inductor size: greater frequencies mean smaller inductances. In notebook applications, real estate solutions (i.e. low-profile power inductors) are mandatory also with high saturation and root mean square (RMS) currents. Efficiency: switching losses are proportional to the frequency. Generally, higher frequencies imply lower efficiency.
8.1
Inductor selection
Once the switching frequency has been defined, the inductance value depends on the desired inductor current ripple. Low inductance value means great ripple current that brings to poor efficiency and great output noise. On the other hand a great current ripple is desirable for fast transient response when a load step is applied. Otherwise, great inductance brings to good efficiency but the load transient response is critical, especially if VINmin - VOUT is little. The product of the output capacitor's ESR multiplied by the inductor ripple current must be taken in consideration; the PM6641 switching regulators current loop doesn't need a minimum output ripple in order to work properly, so a ceramic output capacitor can be considered a good choice. A good trade-off between the transient response time, the efficiency, the cost and the size is choosing the inductance value in order to maintain the inductor ripple current between 20 % and 50 % (usually 30 %) of the maximum output current. The maximum inductor current ripple, IL,MAX, occurs at the maximum input voltage. With these considerations, the inductance value can be calculated with the following expression:
Equation 12
L=
VIN - VOUT VOUT fsw IL VIN
where fSW is the switching frequency, VIN is the input voltage, VOUT is the output voltage and IL is the inductor current ripple.
35/47
Components selection
PM6641
Once the inductor value is determined, the inductor current ripple is then recalculated:
Equation 13
IL,MAX =
VIN,MAX - VOUT fsw L
VOUT VIN,MAX
The next step is the computation of the maximum RMS inductor current:
Equation 14
IL,RMS = (ILOAD,MAX ) 2 +
(IL,MAX ) 2 12
The inductor must have an RMS current greater than IL,RMS in order to assure thermal stability. Then the calculation of the maximum inductor peak current follows:
Equation 15
IL,PEAK = ILOAD,MAX +
IL,MAX 2
IL,PEAK is important when choosing the inductor, in term of its saturation current.
The saturation current of the inductor should be greater than the maximum between ILpeak and the programmed peak current limit, selected by an external resistor connected between CSNS pin and AGND (as described in Current Limit section).
8.2
Input capacitor selection
In a buck topology converter the current that flows through the input capacitor is pulsed and with zero average value. The RMS input current, for each switching regulator, can be calculated as follows:
Equation 16
ICinRMS = ILOAD D (1 - D) +
2
1 D (IL ) 2 12
Neglecting the second term, the equation is reduced to:
Equation 17
ICinRMS ILOAD D (1 - D)
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PM6641
Components selection
The losses due to the input capacitor are thus maximized when the duty-cycle is 0.5:
Equation 18
Ploss = ESR Cin I 2 CinRMS,MAX = ESR Cin (0.5 ILOAD,MAX )
2
The input capacitor should be selected with a RMS rated current higher than ICinRMS,MAX. Tantalum capacitors are good in term of low ESR and small size, but they occasionally can burn out if subjected to very high current during operation. Multi-Layers-Ceramic-Capacitors (MLCC) have usually a higher RMS current rating with smaller size and very low ESR. When only one common input capacitor is chosen for the application, instead of one dedicated capacitor for each regulator (close to each input power supply pins), the total input current can be quite different from the arithmetic sum of the buck regulators RMS input currents, if phase management is allowed (see Chapter 7.9: Phase management on page 30 section for details).
8.3
Output capacitor selection
Using tantalum or electrolytic capacitors, the selection is made referring to ESR and voltage rating rather than by a specific capacitance value. The output capacitor has to satisfy the output voltage ripple requirements. At a given switching frequency, small inductor values are useful to reduce the size of the choke but increase the inductor current ripple. Thus, to reduce the output voltage ripple a low ESR capacitor is required:
Equation 19
ESR
VRIPPLE,MAX IL,MAX
where VRIPPLE is the maximum tolerable ripple voltage.
The zero introduced by the output capacitor ESR must be higher than the switching frequency or must be compensated (see Chapter 7.3: SW regulators control loop on page 24 section for details):
Equation 20
1 f S W > f Z = ------------------------------------------2 E S R CO U T
In order to minimize the output voltage ripple, ceramic capacitors are suggested.
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Components selection
PM6641
If ceramic capacitors are used, the output voltage ripple due to inductor current ripple is negligible. Then the inductance could be smaller, reducing the size of the choke. In this case it is important that output capacitor can adsorb the inductor energy without generating an over-voltage condition when the system changes from a full load to a no load condition. The minimum output capacitance can be chosen by the following equation:
Equation 21
C OUT,min =
L I2 LOAD,MAX Vf 2 - Vi 2
where Vf is the output capacitor voltage after the load transient and Vi is the output capacitor voltage before the load transient.
8.4
SW regulator compensation components selection
As described in section SW Regulators Control Loop, the PM6641 switching regulators control loop is:
Equation 22
GLOOP (s) = g mK L
(sC CR C + 1)
C sC C sCRoR C + Ro + 1 CC
(sC ORES + 1) R O sC O (RES + R O ) + 1
If the output capacitor CO and its equivalent series resistance (ESR) RES provide a low frequency zero, f = 1 , the roll-off compensation pole must be added: zo 2C ORES
Equation 23
fPRO
1 2CROR C
This pole is useful if the fzo zero is greater than about fC0
. 5 However, the first assumption must relate the cross-over frequency, fCO, with the control loop gain:
Equation 24
GLOOP (j2fCO ) g mK L
2fCO C CR C R CR O R O = g mK L 2fCO C C 2fCO C O (RES + R O ) 2fCO C O (RES + R O )
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PM6641
Components selection
From the definition of cross-over frequency, the value of the compensation resistor is derived:
Equation 25
GLOOP ( j2fCO ) = 1 R C =
2fCO C O (RES + R O ) g m K L R O
A good choice for the cross-over frequency is to assign fCO equal to fSW
. 10 The fixed parameters gm = 300 s and KL = 4.4 s are design parameters, whereas the feedback divider factor () is application dependant (see Chapter 7.3: SW regulators control loop on page 24 section for details). After computing RC, the compensation capacitor can be designed in order to place the compensation zero near the power stage pole:
Equation 26
CC =
C O (R O + RES ) RC
The roll-off capacitance, as said previously, must compensate for the power stage high frequency zero, when necessary:
Equation 27
CRO =
C ORES RC
As final step, it's important to verify that the compensation zero is quite far from the crossover frequency. An empirical rule is satisfied if the following holds:
Equation 28
fZC =
f 1 CO 2C CR C 5
All these considerations are true if the cross-over frequency is quite lower than the switching frequency, and the compensation zero and the power stage pole are far enough from fCO.
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Components selection
PM6641
8.5
Layout guidelines
Each signal is referred to AGND, the analog ground. In a typical 4-layers PCB one internal layer should be dedicated to this common ground. The IC thermal pad must be connected to AGND plane through multiple VIAs, in order to remove the IC heat and to obtain the best performance. Furthermore, each switching regulator has a dedicated power ground (SGND_1Sxx); all these SGNDs must be star-connected, in a single point, with AGND. For each switching section the power componets (inductor and input/output capacitors) must be placed near the VSW_1Sxx, VIN_1Sxx and SGND_1Sxx pins and connected with large (at least 20mils or larger) and short PCB traces, in order to limit the path of the current high frequency components and, consequently, to reduce the injected noise. If the power components routing involves more than one layer, as many VIAs as possible must be inserted to reduce the series resistance and improve the global efficiency. The VTT external components (input and output capacitors) must be placed near the LDO regulator input (LDOIN) and output (VTT) pins, and must be routed with large and short traces, in order to limit the parasitic series resistance. The feedback pins (VFB_1Sxx and VTTFB) must reach the feedback points through dedicated PCB traces, typically 10mils width; larger feedback traces are not required. For reference layout, refer to PM6641 Evaluation Kit document.
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PM6641
Application examples
9
Application examples
The following application examples are typical or customized applications. Each example has been tested and evaluated and the schematic and BOM are available for reference design.
9.1
UMPC DDR2 and chipset power supply
Figure 34. System architecture for DDR2 and chipset power supply
VDDQ 1.8V @ 2.5A 3.3V VTT (LDO) 0.9V @ 2A
PM6641
1.5V @ 2.8A
1.05V @ 4A
This application is conceived for real estate constrained portable equipment with DDR2 memory. An input power voltage pre-regulated to 3.3 V or 5 V is available and the available output maximum power levels are shown in Figure 34. The switching regulator average load is estimated to be about 50 % of the maximum load; this upper limit must be respected in order to avoid dangerous stresses for internal power MOSFETs. The following table resumes these current values.
Table 12. Expected average and peak currents for DDR2 and chipset power supply
Output rail 1.8 V (VDDQ) 0.9 V (VTT) 1.5 V 1.05 V Max non continuous load [A] 2.5 2 2.8 4 Expected average load [A] 1.3 0.3 1.4 2
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1
1
VC C
R1 0603-3R 3
TP6 AGN D
C1
AVC C
0603-1u AVC C C 18 0603-33n 2 C 11 1206-22u 1 2 3 4 C 25 AVC C VI N TP10 VOU T_1S5 1 0603-100p 0603-100p 0603-100p 0603-100p C 26 C 27 C 28 SW DIP-4 8 7 6 5 SW 1 1 R 20 0603-68k R 21 0603-68k R 22 0603-68k R 23 0603-68k
1
C 16
0603-100n
TP9 VOU T_1S8
C 12 0805-10u
1
1
48 47 46 45 44 43 42 41 40 39 38 37
AVC C
C6 1206 - 100u 2839-1u5 C7 1206 - 100u
C 15 1206 - 100u L2 1 2
L1 1 PM6641_QF PN 2839-1u0 R 12 0603-47k C 23 0603-470p 2
C2 0805-10u
VI N
1 2 3 4 5 6 7 8 9 10 11 12 AGN D _1 SET_SW F VOU T_1S8 C SN S SGN D _1S8_1 SGN D _1S8_2 VSW _1S8_1 VSW _1S8_2 VI N _1S8_1 VI N _1S8_2 VF B_1S8 C OMP_1S8 U1 EN _VTT EN _1S5 EN _1S05 VI N _1S5 VSW _1S5_2 VSW _1S5_1 SGN D _1S5_2 SGN D _1S5_1 VF B_1S5 C OMP_1S5 SS_1S5 PG_1S5
VC C VT T _F B D SC G VT T R EF LD O_I N VT T VT T _GN D AVC C AGN D _2 SET _PH 1 AGN D _3 EN _1S8
C 22 0603-330p
C 19 R 13 0603-68k C 21 0603-22n 1 C 24 0603-330p 2 L3 2839-1u C4 0805-10u AVC C TP3 PG_1S5 TP2 PG_1S8 TP4 PG_1S05 VI N
0603-22n
13 14 15 16 17 18 19 20 21 22 23 24
0603-join
SS_1S8 SS_1S05 C OM P_1S05 VF B_1S05 SGN D _1S05_1 SGN D _1S05_2 VSW _1S05_1 VSW _1S05_2 VI N _1S05_1 VI N _1S05_2 PG_1S05 PG_1S8
1
1
1
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TP1 VTTR EF TP14 VTT C3 0805-10u 36 35 34 33 32 31 30 29 28 27 26 25 R 32 49 TH ER MAL
Application examples
TP5 VC C
Figure 35. Suggested schematic for DDR2 and chipset power supply
R 11 0603-100k
C 20 0603-22n
R 17 0603-68k C9 1206 - 100u C 10 1206 - 100u
The following schematic and bill of materials (BOM) are for reference design.
R 18 0603-68k
R 19 0603-68k
TP12 1 VOU T_1S05
TP13 1 1 GN D VI N TP7
The power and signal components have been selected in agreement with Chapter 8: Components selection equations.
The default switching frequency has been selected (750 kHz) and the tracking discharge has been enabled in agreement with DDR2 JEDEC specifications. No external resistor dividers are required for these output voltage levels. The allowed inductor current ripple is about 35 % of the expected peak load.
PM6641
PM6641
Application examples
Table 13. BOM suggested components for DDR2 and chipset power supply
Qty 1 4 5 1 1 1 3 2 1 4 1 1 1 8 1 2 1 1 Component C1 C2, C3, C4, C12 C6, C7, C9, C10, C15 C11 C16 C18 C19, C20, C21 C22, C24 C23 C25, C26, C27, C28 R1 R11 R12 R13, R17, R18, R19, R20, R21, R22, R23 R32 L1, L3 L2 U1 Ceramic, 50 V, C0G, 5 % Ceramic, 50 V, C0G, 5 % Ceramic, 50 V, C0G, 5 % Chip resistor, 0.1 W, 1 % Chip resistor, 0.1 W, 1 % Chip resistor, 0.1 W, 1 % Chip resistor, 0.1 W, 1 % Chip resistor, 0.1 W, 1 % SMT 11 Arms, 9.5 m SMT 9 Arms, 10.5 m IC VR - 48 PIN Description Ceramic, 10 V, X5R, 10 % Ceramic, 10 V, X5R, 10 % Ceramic, 4 V, X5R, 20 % Ceramic, 6.3 V, X5R, 10% Ceramic, 16 V, X7R, 10 % Ceramic, 25 V, X7R, 10 % Package SMD 0603 SMD 0805 SMD 1206 SMD 1206 SMD 0603 SMD 0603 SMD 0603 SMD 0603 SMD 0603 SMD 0603 SMD 0603 SMD 0603 SMD 0603 SMD 0603 SMD 0603 SMD 2827 SMD 2827 VFQFPN 7x7 744312100 /LF 744312150 /LF PM6641 GRM188R71E333KA01 GRM21BR61A106KE19 AMK316BJ107ML GRM31CR60J226KE19 Part number MFR Standard Murata Taiyo Yuden Murata Standard Murata Standard Standard Standard Standard Standard Standard Standard Standard Standard Wür th Wür th ST Value 1 uF 10 uF 100 uF 22 uF 100 nF 33 nF 22 nF 330 pF 470 pF 100 pF 3R3 100 k 47 k 68 k 0 1.0 u 1.5 u PM6641
Note:
This applicative solution has been tested and the PM6641EVAL demo board is now available for evaluation.
Please refer also to PM6641 Evaluation Kit document for test and measurement results.
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Package mechanical data
PM6641
10
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
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PM6641 Figure 36. VFQFPN-48 (7x7x1.0 mm)
Package mechanical data
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Revision history
PM6641
11
Revision history
Table 14. Document revision history
Date 16-May-2007 Revision 1 Initial release Document status promoted from preliminary data to datasheet. Updated: Table 2 on page 6, Table 3 on page 8, Table 6 on page 9, Chapter 7: Device description on page 19, Added: Chapter 9: Application examples on page 41., Chapter 8.5: Layout guidelines on page 40 Changes
16-Jan-2008
2
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PM6641
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