STP08CP05
Low voltage, low current power 8-bit shift register
Features
Low voltage power supply down to 3 V 8 constant current output channels Adjustable output current through external resistor Serial data IN/parallel data OUT 3.3 V micro driver-able Output current: 5-100 mA 30 MHz clock frequency Available in high thermal efficiency TSSOP exposed pad ESD protection 2.5 kV HBM, 200 V MM
TSSOP16 SO-16 DIP-16 TSSOP16 (Exposed pad)
Description
The STP08CP05 is a monolithic, low voltage, low current, power 8-bit shift register designed for LED panel displays. The STP08CP05 contains an 8-bit serial-in, parallel-out shift register that feeds a 8-bit D-type storage register. In the output stage, eight regulated current sources were designed to provide 5-100 mA constant current to drive the LEDs, the output current setup time is 11 ns (typ), thus improving the system performance. The STP08CP05 is backward compatible in functionality and footprint with STP8C/L596. Through an external resistor, users can adjust the STP08CP05 output current, controlling in this way the light intensity of LEDs, in addition, user can adjust LED's brightness intensity from 0 % to 100 % via OE pin. The STP08CP05 guarantees a 20 V output driving capability, allowing users to connect more LEDs in series. The high clock frequency, 30 MHz, also satisfies the system requirement of high volume data transmission. The 3.3 V of voltage supply is useful for applications that interface with any micro from 3.3 V. Compared with a standard TSSOP package, the TSSOP exposed pad increases heat dissipation capability by a 2.5 factor.
Table 1. Device summary
Order codes STP08CP05B1R STP08CP05MTR STP08CP05TTR STP08CP05XTTR Package DIP-16 SO-16 (Tape and reel) TSSOP16 (Tape and reel) TSSOP16 exposed-pad (Tape and reel) Packaging 25 parts per tube 2500 parts per reel 2500 parts per reel 2500 parts per reel
August 2008
Rev 4
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Contents
STP08CP05
Contents
1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 Pin connection and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1 3.2 3.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4 5 6 7
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Equivalent circuit and outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Truth table and timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
7.1 7.2 Truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
8 9 10 11
Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
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STP08CP05
Summary description
1
Summary description
Table 2. Typical current accuracy
Current accuracy Output voltage Between bits 1.3 V 1.5 % Between ICs 3% 20 to 100 mA Output current
1.1
Pin connection and description
Figure 1. Connections diagram
Note:
The exposed-pad is electrically not connected Table 3. Pin description
Pin N 1 2 3 4 5-12 13 14 15 16 Symbol GND SDI CLK LE OUT 0-7 OE SDO R-EXT VDD Ground terminal Serial data input terminal Clock input terminal Latch input terminal Output terminal Output enable input terminal (active low) Serial data out terminal Constant current programming 5 V supply voltage terminal Name and function
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Block diagram
STP08CP05
2
Figure 2.
Block diagram
Block diagram
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STP08CP05
Maximum rating
3
Maximum rating
Stressing the device above the rating listed in the "absolute maximum ratings" table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics sure program and other relevant quality documents.
3.1
Absolute maximum ratings
Table 4. Absolute maximum ratings
Symbol VDD VO IO IGND fC L K TOPR
T ST G
Parameter Supply voltage IGND Output voltage Output current GND terminal current Clock frequency Operating temperature range Storage temperature range
Value 0 to 7 -0.5 to 20 100 800 50 -40 to +125 -55 to +150
Unit V V mA mA MHz C C
3.2
Thermal data
Table 5. Thermal data
Symbol RthJA Parameter Thermal resistance junction-ambient DIP-16 SO-16 TSSOP-16 90 125 140 TSSOP-16 (1) (exposed pad) 37.5 Unit C/W
1. The exposed-pad should be soldered to the PBC to realize the thermal benefits
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Maximum rating
STP08CP05
3.3
Recommended operating conditions
Table 6. Recommended operating conditions
Symbol VDD VO IO IOH IOL VIH VIL twLAT twCLK t wEN Parameter Supply voltage Output voltage Output current Output current Output current Input voltage Input voltage LE pulse width CLK pulse width OE pulse width VDD = 3.0 to 5.0 V OUTn SERIAL-OUT SERIAL-OUT 0.7 VDD -0.3 20 20 200 7 4 15 Cascade operation (1) 30 5 Test conditions Min 3.0 Typ Max 5.5 20 100 +1 -1 VDD+0.3 0.3 VDD Unit V V mA mA mA V V ns ns ns ns ns ns MHz
tSETUP(D) Setup time for DATA tHOLD(D) Hold time for DATA tSETUP(L) Setup time for LATCH fCLK Clock frequency
1. In order to achieve high cascade data transfer, please consider tr/tf timings carefully.
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STP08CP05
Electrical characteristics
4
Electrical characteristics
Table 7. Electrical characteristics (VDD = 3.3 V to 5 V, T = 25 C, unless otherwise specified.)
Symbol VIH VIL IOH VOL VOH IOL1 IOL2 IOL3 IOL1 IOL2 IOL3 RSIN(up) Output current error between bit (All Output ON) Pull-up resistor Output current Parameter Input voltage high level Input voltage low level Output leakage current Output voltage (Serial-OUT) Output voltage (Serial-OUT) VOH = 20 V IOL = 1 mA IOH = -1 mA VO = 0.3 V, Rext = 3.9 k VO = 0.3 V, Rext = 970 VO = 1.3 V, Rext = 190 VO = 0.3 VREXT = 3.9 k VO = 0.3 VREXT = 970 VO = 1.3 VREXT =190 150 100 REXT = 980 OUT 0 to 7 = OFF Supply current (OFF) IDD(OFF2) IDD(ON1) Supply current (ON) IDD(ON2) Thermal Thermal protection (1) REXT = 250 OUT 0 to 7 = ON 11.7 170 13.5 C REXT = 250 OUT 0 to 7 = OFF REXT = 980 OUT 0 to 7 = ON 11.2 4.5 13.5 mA 5 VOH - VDD =- 0.4 V 4.25 19.4 97 5 20 100 5 1.5 1.2 300 200 4 5.75 20.6 103 8 2.75 2.5 600 400 5 K K % mA Test conditions Min 0.7 VDD GND 0.5 0.03 Typ Max VDD 0.3VDD 10 0.4 Unit V V A V V
RSIN(down) Pull-down resistor IDD(OFF1)
1. Guaranteed by design (not tested) The thermal protection switches OFF only the outputs
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Switching characteristics
STP08CP05
5
Switching characteristics
Table 8. Switching characteristics (VDD = 5 V, T = 25 C, unless otherwise specified.)
Symbol tPLH1 Parameter Propagation delay time, CLK-OUTn, LE = H, OE = L Propagation delay time, LE -OUTn, OE = L Propagation delay time, OE -OUTn, LE = H Propagation delay time, CLK-SDO Propagation delay time, CLK-OUTn, LE = H, OE = L Propagation delay time, LE -OUTn, OE = L Propagation delay time, OE -OUTn, LE = H Propagation delay time, CLK-SDO Output rise time 10~90% of voltage waveform Output fall time 90~10% of voltage waveform CLK rise time (1) CLK fall time (1) Test conditions VDD = 3.3 V VDD = 5 V VDD = 3.3 V VDD = 5 V VDD = 3.3 V VDD = 5 V VDD = 3.3 V VDD = 5 V VDD = 3.3 V VDD = 3.3 V VIL = GND IO = 20 mA REXT = 1 K VIH = VDD CL = 10 pF VL = 3.0 V RL = 60 VDD = 5 V VDD = 3.3 V VDD = 5 V VDD = 3.3 V VDD = 5 V VDD = 3.3 V VDD = 5 V VDD = 3.3 V VDD = 5 V VDD = 3.3 V VDD = 5 V Min Typ 35 18 48 30 55 37 21 17 11 7 24 21 20 18 24 19 26 11 5 4 Max 50 ns 28 74 ns 50 82 ns 58 28 ns 22 17 ns 11 40 ns 31 35 ns 28 32 ns 25 40 ns 17 10 ns 8 5000 5000 ns ns Unit
tPLH2
tPLH3
tPLH
tPHL1
tPHL2
tPHL3
tPHL
tO N
tOFF tr tf
1. In order to achieve high cascade data transfer, please consider tr/tf timings carefully.
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STP08CP05
Equivalent circuit and outputs
6
Equivalent circuit and outputs
Figure 3. OE terminal
Figure 4.
LE terminal
Figure 5.
CLK, SDI terminal
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Equivalent circuit and outputs Figure 6. SDO terminal
STP08CP05
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STP08CP05
Truth table and timing diagram
7
7.1
Truth table and timing diagram
Truth table
Table 9. Truth table
Clock LE H OE L SDI Dn OUT0 . . .... OUT0 . . .... OUT7 Dn . . . Dn -5 . . . Dn -7 SDO Dn -7
L
L
Dn + 1
No change
Dn -7
H
L
Dn + 2
Dn +2 . . . Dn -3 . . . Dn -5
Dn -5
X
L
Dn + 3
Dn +2 . . . Dn -3 . . . Dn -5
Dn -5
X
H
Dn + 3
OFF
Dn -5
No te :
OUT0 to OUT7 = ON when Dn = H; OUT0 to OUT7 = OFF when Dn = L.
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Truth table and timing diagram
STP08CP05
7.2
Timing diagram
Figure 7. Timing diagram
Figure 8.
Clock, serial-in, serial-out
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STP08CP05 Figure 9. Clock, serial-in, latch, enable, outputs
Truth table and timing diagram
Figure 10. Outputs
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Typical characteristics
STP08CP05
8
Typical characteristics
Figure 11. Output current-REXT resistor
TA = 25 C, Iset = 3 mA; 5 mA; 10 mA; 20 mA; 50 mA; 80 mA; Max
Table 10. Output current-REXT resistor
Output current (mA) Rext () 3 6740 5 3930 10 1913 20 963 50 386 80 241 130 124
Note:
Maximum output current capabilities setting was 130 mA applying an Rext = 124
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STP08CP05
Typical characteristics
Figure 12. ISET vs drop out voltage (VDROP)
910 810 710 Vdrop (mV) 610 510 410 310 210 110 10 0 10 20 30 40 50 60 70 80 90 100 110 Iset (mA) Vdd 5.0V Vdd 3.0V
Table 11. ISET vs drop out voltage (VDROP)
Vdd (V) 3 I set (mA) 3 5 10 20 50 80 100 5 3 5 10 20 50 80 100 Rext () 6470 3930 1910 963 386 241 192 6470 3930 1910 963 386 241 192 Vdrop min (mV) 30.6 46.5 80.9 150 392 636 846 25.6 40.8 80.1 153 379 618 825 Vdrop max (mV) 31.2 52.9 100 161 396 646 850 29 41.7 105 154 386 626 830 Vdrop AVG (mV) 30.93 48.63 82.26 157 394.3 640.3 848 26.96 41.16 89.2 154 382 621 827
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Typical characteristics Figure 13. Power dissipation vs temperature package
STP08CP05
Note:
The exposed-pad should be soldered to the PBC to realize the thermal benefits. Figure 14. Current precision between outputs vs output current
6 5.5 5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 1 10 Iset (mA) 100
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%
STP08CP05
Test circuit
9
Test circuit
Figure 15. DC characteristics
Figure 16. AC characteristics
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Test circuit
STP08CP05
Figure 17. Typical application schematic
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STP08CP05
Package mechanical data
10
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
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Package mechanical data Figure 18. DIP-16 mechanical data
STP08CP05
Plastic DIP-16 (0.25) MECHANICAL DATA
mm. DIM. MIN. a1 B b b1 D E e e3 F I L Z 3.3 1.27 8.5 2.54 17.78 7.1 5.1 0.130 0.050 0.51 0.77 0.5 0.25 20 0.335 0.100 0.700 0.280 0.201 1.65 TYP MAX. MIN. 0.020 0.030 0.020 0.010 0.787 0.065 TYP. MAX. inch
P001C
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STP08CP05 Figure 19. TSSOP16 mechanical data
Package mechanical data
TSSOP16 MECHANICAL DATA
mm. DIM. MIN. A A1 A2 b c D E E1 e K L 0 0.45 0.60 0.05 0.8 0.19 0.09 4.9 6.2 4.3 5 6.4 4.4 0.65 BSC 8 0.75 0 0.018 0.024 1 TYP MAX. 1.2 0.15 1.05 0.30 0.20 5.1 6.6 4.48 0.002 0.031 0.007 0.004 0.193 0.244 0.169 0.197 0.252 0.173 0.0256 BSC 8 0.030 0.004 0.039 MIN. TYP. MAX. 0.047 0.006 0.041 0.012 0.0079 0.201 0.260 0.176 inch
A
A2 A1 b e K c L E
D
E1
PIN 1 IDENTIFICATION
1
0080338D
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Package mechanical data Figure 20. TSSOP16 exposed pad mechanical data
STP08CP05
TSSOP16 EXPOSED PAD MECHANICAL DATA
mm. DIM. MIN. A A1 A2 b c D D1 E E1 E2 e K L 0 0.45 0.60 0.8 0.19 0.09 4.9 1.7 6.2 4.3 1.5 0.65 8 0.75 0 0.018 0.024 6.4 4.4 6.6 4.5 5 1 TYP M AX. 1.2 0.15 1.05 0.30 0.20 5.1 0.031 0.007 0.004 0.193 0.067 0.244 0.169 0.059 0.0256 8 0.030 0.252 0.173 0.260 0.177 0.197 0.004 0.039 MIN. TYP. M AX . 0.047 0.006 0.041 0.012 0.0089 0.201 inch
7419276A
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STP08CP05 Figure 21. TSSOP16 tape and reel
Package mechanical data
Tape & Reel TSSOP16 MECHANICAL DATA
mm. DIM. MIN. A C D N T Ao Bo Ko Po P 6.7 5.3 1.6 3.9 7.9 12.8 20.2 60 22.4 6.9 5.5 1.8 4.1 8.1 0.264 0.209 0.063 0.153 0.311 TYP MAX. 330 13.2 0.504 0.795 2.362 0.882 0.272 0.217 0.071 0.161 0.319 MIN. TYP. MAX. 12.99 2 0.519 inch
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Package mechanical data Figure 22. SO-16 mechanical data
STP08CP05
SO-16 MECHANICAL DATA
DIM. A a1 a2 b b1 C c1 D E e e3 F G L M S 3.8 4.6 0.5 9.8 5.8 1.27 8.89 4.0 5.3 1.27 0.62 8 (max.) 0.149 0.181 0.019 10 6.2 0.35 0.19 0.5 45 (typ.) 0.385 0.228 0.050 0.350 0.157 0.208 0.050 0.024 0.393 0.244 0.1 mm. MIN. TYP M AX. 1.75 0.25 1.64 0.46 0.25 0.013 0.007 0.019 0.004 MIN. inch TYP. M AX . 0.068 0.010 0.063 0.018 0.010
0016020D
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STP08CP05 Figure 23. SO-16 tape and reel
Package mechanical data
Tape & Reel SO-16 MECHANICAL DATA
mm. DIM. MIN. A C D N T Ao Bo Ko Po P 6.45 10.3 2.1 3.9 7.9 12.8 20.2 60 22.4 6.65 10.5 2.3 4.1 8.1 0.254 0.406 0.082 0.153 0.311 TYP MAX. 330 13.2 0.504 0.795 2.362 0.882 0.262 0.414 0.090 0.161 0.319 MIN. TYP. MAX. 12.99 2 0.519 inch
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Revision history
STP08CP05
11
Revision history
Table 12. Document revision history
Date 23-May-2007 28-Jun-2007 12-Mar-2008 07-Aug-2008 Revision 1 2 3 4 First release Updated Table 7 on page 7 Updated Table 8 on page 8 and added Figure 11 and Figure 12 on page 15 Updated Section 8: Typical characteristics on page 14 Changes
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STP08CP05
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