STV7622
192 output plasma display panel data driver
Preliminary Data
Features
s s s s
The input data bus is configured by dedicated input pins:
q q
192 high-voltage outputs Output pad placements: I-shape 90 V absolute maximum supply EMI control features: Smar tSlope ConstantSlope Spread Spectrum Jitter (SSJ) Configurable data bus: 3, 6 or 2 × 3 bits TTL and LVCMOS compatible RSDS mode Single- or dual-edge clocking mode 60 MHz clock frequency 3.3 /5 V CMOS logic compatible - 60/+24mA source/sink output current capability BCD Process Packaging according to customer request: wafer, die, bumped die/wafer, TCP or COF
BS1 and BS2: bus width select (3, 6, 2 × 3 bits or RSDS mode) DIR input: shift register loading direction
The STV7622 output stage integrates several ST patented functions aimed at reducing EMI without compromising addressing speed or performance of the PDP modules. These functions mainly consist of:
q q q
s
Smar tSlope: controls the output falling edge speed /shape ConstantSlope: controls the output rising edge speed Spread Spectrum Jitter (SSJ): controls the spread of the output rising edge
s s
s s
The STV7622 is powered by a separate 70V supply for the high-voltage outputs and a 5V supply for the logic. All command input levels are 5V CMOS as well as 3.3V compatible. Figure 1. Block diagram
BS1 BS2 DIR CLK1 CLK2 VDD VSSLOG DB1 32-bit Shift register Shift register direction 3/6/2x3-bit & RSDS selection 32-bit Shift register 32-bit Shift register 32-bit Shift register 32-bit Shift register 32-bit Shift register TEST1 TEST2 VREF
10nF Q192
Description
The STV7622 is a data driver for Plasma Display Panels (PDP) designed in the ST's proprietary BCD high-voltage technology. It controls up to 192 outputs via an input data bus (3, 6 or 2 × 3-bits wide) operating at up to 60MHz. This large number of outputs reduces the number of connections between the controller board and the data driver ICs. The STV7622 contains a new logic input stage that minimizes EMI resulting from the transmission of high speed TTL or LVCMOS data and clock signals. This new input stage is RSDS compliant. It enables increasing the operating frequency without compromising noise immunity.
DB2 DB3 DB4 DB5 DB6
Data decoding
/STB1 /STB2
Q1 Q2 Q3 Q4
Latch
V CC /BLK POC RS 1 RS 2 F S1 F S2 VPP
Output control / EMI control
Output buffer stage
VSSP VSSSUB
OUT1
OUT2
OUT3 . . .
.... OUT192
May 2007
Rev 1
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www.st.com 32
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Contents
STV7622
Contents
1 2 3 4 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Output stage description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5. 1 5. 2 5. 3 5. 4 5. 5 5. 6 Data input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 x 64-bit data bus, standard transmission (BS1 = H, BS2 = L) . . . . . . . . . 8 6 x 32-bit data bus, standard transmission (BS1 = L, BS2 = L) . . . . . . . . . 8 2 x 3 x 32-bit data bus, standard transmission (BS1 = H, BS2 = H) . . . . . 9 Differential transmission mode: RSDS (BS1 = L, BS2 = H) . . . . . . . . . . . 10 Power output block and EMI control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6 7 8 9 10 11 12 13 14
Truth tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 AC timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 AC timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Pad dimensions and positions (in m) . . . . . . . . . . . . . . . . . . . . . . . . . 22 Tested wafer disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
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STV7622
Block diagram
1
Figure 2.
Block diagram
STV7622 block diagram
BS1 BS2
DIR
CLK1
CLK2
VDD VSSLOG
DB1 Shift register direction 3/6/2x3-bit & RSDS selection DB2 DB3 DB4 DB5 DB6
32-bit Shift register 32-bit Shift register 32-bit Shift register 32-bit Shift register 32-bit Shift register 32-bit Shift register TEST1 TEST2 VREF
10nF Q192
Data decoding
/STB1 /STB2
Q1 Q2 Q3 Q4
Latch
VCC /BLK POC RS1 RS2 FS1 FS2 VPP
Output control / EMI control
Output buffer stage
VSSP VSSSUB
OUT1
OUT2
OUT3 . . .
.... OUT192
3/32
Pin description
STV7622
2
Table 1.
Pin description
Pin description
Function Supply Supply Supply Ground Ground Ground Outputs Inputs Input Input Input Inputs Inputs Inputs Inputs Inputs Test pin Test pin Input Description DC high-voltage supply of power outputs Analog 5V supply Digital 5V supply Ground for power outputs Substrate ground Ground for 5V logic Power outputs Shift register inputs Blanking input Power output control input Selection of shift register direction Shift register configuration pins (3/6/2 × 3-bits and RSDS selection) Clock for data shift register Latch of data to power outputs Output rise time selection pins Output "slow-slope" fall time selection pins Must be grounded Must be grounded Filter for internal reference - must be connected to ground via a 10nF capacitor
Pin name VPP VCC VDD VSSP VSSSUB VSSLOG OUT1 to OUT192 DB1to DB6 /BLK POC DIR BS1 and BS2 CLK1 and CLK2 /STB1 and /STB2 RS1 and RS2 FS1 and FS2 TEST1 TEST2 VREF
Note:
Inputs /BLK, /STB1 and /STB2 are active Low.
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STV7622
Output stage description
3
Figure 3.
Output stage description
Output stage description
VCC VPP
Output stage
Output 1
Rise time RS1/RS2
T3
to 192
Totem pole
VCC
Fall time FS1/FS2
T1 OUTn
Rising edge control Falling edge control
Delay
T2
T4
Output control
VSSP
5/32
Pinout description
STV7622
4
Figure 4.
Pinout description
Pinout diagram
OUT19 2 OUT19 1 OUT19 0 OUT18 9 OUT18 8 OUT18 7 OUT18 6 OUT18 5 OUT18 4 OUT18 3 OUT18 2 OUT18 1 OUT18 0
VSSP1 VSSP2 VSSP3 VPP 1 VPP 2 VPP 3 DUMMY VSS LOG 1 VSS SUB 1 VDD1 VCC1
OUT12 OUT11 OUT10 OUT9 OUT8 OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUT1 VSSP4 VSSP5
Y
VSSP6 VPP4 VPP5
0/0
X
VPP6 DUMMY VSSLOG 2 VSSSUB 2 VDD2 VCC2 DUMMY
In the pinout diagram of Figure 4 above:
q q q
VDD1 to VDD8 are internally connected. It is not necessary to connect them together on the tape carrier package (TCP) - the same applies to VCC1 and VCC2. VSSLOG1 to VSSLOG2 are internally connected. It is not necessary to connect them together on the TCP - the same for VSSSUB1 and VSSSUB2. VSSLOG1 to VSSLOG7 are not internally connected to VSSSUB1 and VSSSUB2. We recommend shorting them together very close to the die, either on the TCP or at the TCP connector. VDD1 to VDD8 are not internally connected to VCC1 and VCC2. For good test coverage, they must not be shorted together on the TCP. In the application, VDD1 to VDD8, VCC1 and VCC2 must be connected together at the TCP connector level. TEST1 and TEST2 are used to test the device. For good test coverage, they must not be shorted together on the TCP. In the application, TEST1 and TEST2 must be grounded at the TCP connector level. VREF must be connected to ground via a 10nF filter capacitor.
q
q
q
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DB6 DB5 DB4 DB3 DB2 DB1 /STB2 /STB1 CLK 2 CLK 1 VDD3 /B LK VSSLOG 3 POC VDD4 DUMMY DUMMY VREF DUMMY VSSLOG 4 RS1 VDD5 RS2 VSSLOG 5 FS2 VDD6 FS1 VSSLOG 6 DIR VDD7 BS 1 VSSLOG 7 BS 2 VDD8 TEST1 TEST2 DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY
STV7622
Circuit description
5
Circuit description
The STV7622 includes all the logic and power circuits necessary to drive the column electrodes of a Plasma Display Panel (PDP). A low-voltage logic block manages data information, and a high-voltage block converts the low-voltage information stored in the logic block into high-voltage signals applied to the display electrodes.
5.1
Data input block
The Data Bus is TTL- and LVCMOS-compatible and can also operate in an RSDS (Reduced Swing Differential Signaling) mode. The maximum clock frequency is 60MHz. The data input block consists of several shift registers operating in parallel to load the binary values of the digital video. The number of cells in each shift register is defined by the BS pin as described below in Table 2. Table 2. BS1/BS2 truth table
BS1 L H L H BS2 L L H H Shift register configuration 6 × 32 bits 3 × 64 bits RSDS mode 2 × 3 × 32 bits (96 + 96)
For the 3 × 64 bit configuration, only pins DB1, DB2 and DB3 of the input data bus are used, while for the 6 × 32 and 2 × 3 × 32 bit configurations all 6 bits of the input data bus input, pins DB1 to DB6, are used. The DIR input pin is used to select the shift register loading direction. Data is shifted for each low-to-high transition of the clock signal (CLK1). The maximum frequency of the clock is 60MHz, which is equivalent to a 360MHz serial shift register for a 6 × 32-bit arrangement. When the /STB signal goes from high-to-low, data is transferred from the shift register to the latch and to the power output stages. All output data is stored and held in the latch stage when the latch input is pulled back High. The core of the STV7622 is powered by 5V. All logic inputs can be driven either by 5V or 3.3V CMOS logic. The tables in the following sections describe the position of the first data sampled by the first rising edge of the CLK1 clock.
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Circuit description
STV7622
5.2
3 x 64-bit data bus, standard transmission (BS1 = H, BS2 = L)
The data bus is in 3-bit mode (DB1 to DB3 active) for BS1 = H and BS2 = L. Data on DB1 is sampled by the first clock pulse and shifted from position 1 to position 190 after 64 clock pulses. The data is then applied to output 190, on the high-to-low transition of /STB.
Table 3.
BS1 BS2
3 x 64-bit data bus transmission
Clock pulse number DIR Input Position DB1 DB2 DB3 DB1 DB2 DB3 OUT OUT OUT OUT OUT OUT 01 01 02 03 190 191 192 02 04 05 06 187 188 189 03 07 08 09 184 185 186 ... 62 184 185 186 07 08 09 63 187 188 189 04 05 06 64 190 191 192 01 02 03 Left / Right shift Comment
H
L
L
H
L
H
Right / Left shift
5.3
6 x 32-bit data bus, standard transmission (BS1 = L, BS2 = L)
The data bus is in 6-bit mode (DB1 to DB6 active) for BS1 = L and BS2 = L. Table 4 below describes how data is shifted in the register.
Table 4.
BS1 BS2
6 x 32-bit data bus transmission
Position DIR Input Clock pulse number DB1 DB2 DB3 DB4 DB5 DB6 DB1 DB2 DB3 DB4 DB5 DB6 OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT 01 02 03 04 05 06 187 188 189 190 191 192 07 08 09 10 11 12 181 182 183 184 185 186 13 14 15 16 17 18 175 176 177 178 179 180 175 176 177 178 179 180 13 14 15 16 17 18 181 182 183 184 185 186 07 08 09 10 11 12 187 188 189 190 191 192 01 02 03 04 05 06 01 02 03
...
30
31
32 Comment
L
L
L
Left/Right shift
L
L
H
Right/Left shift
8/32
STV7622
Circuit description
5.4
2 x 3 x 32-bit data bus, standard transmission (BS1 = H, BS2 = H)
The data bus is in 2 × 3-bit mode (DB1 to DB6 active) for BS1 = H and BS2 = H. Table 5 below describes how data is shifted in the register.
Table 5.
BS1 BS2
2 x 3 x 32-bit data bus transmission
Clock pulse number DIR Input Position DB1 DB2 DB3 DB4 DB5 DB6 DB1 DB2 DB3 DB4 DB5 DB6 OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT 01 01 02 03 97 98 99 94 95 96 190 191 192 02 04 05 06 100 101 102 91 92 93 187 188 189 03 07 08 09 103 104 105 88 89 90 184 185 186 Comment
...
30 88 89 90 184 185 186 07 08 09 103 104 105
31 91 92 93 187 188 189 04 05 06 100 101 102
32 94 95 96 190 191 192 01 02 03 97 98 99
H
H
L
Left/Right shift
H
H
H
Right/Left shift
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Circuit description
STV7622
5.5
Differential transmission mode: RSDS (BS1 = L, BS2 = H)
In differential transmission mode, data is transmitted on two wires, one line transmits the data value, the other the inverted data. The logic level of the data is determined by the difference between data and inverted data. Two DB inputs are needed for the transmission of 1 data value. The sampling clocks, CLK1 and CLK2, as well as strobes STB1/ and STB2 are also transmitted differentially. Data is sampled on the rising and falling edges of the clock.
Table 6.
BS2 B12
2 x 3 x 32-bit data bus transmission - differential mode
DIR Input Position DB1 DB2 01 01 OUT 02 03 190 OUT 191 192 CLK1 clock pulse number 01 04 05 06 187 188 189 02 07 08 09 184 185 186 Comment 31 184 185 186 07 08 09 32 187 188 189 04 05 06 32 190 191 192 01 02 03 Right /Left shift Left /Right shift
...
H
L
L
DB3 DB4 DB5 DB6 DB1 DB2
H
L
H
DB3 DB4 DB5 DB6
In differential transmission operating mode, the biasing of the data input bus must be carefully arranged to reduce static power consumption. In stand-by and non-active modes, DB1, DB3, DB5, CLK1 and /STB1 should be set High to reduce bias current in the differential input buffers. For a High level, all differential pairs should be configured with DB1, DB3, DB5, CLK1 and /STB1 High and with DB2, DB4, DB6, CLK2 and /STB2 Low. When operating in differential transmission mode, a 100 ohm (1%) resistor termination must be connected between:
q q q q q
DB1 and DB2 DB3 and DB4 DB5 and DB6 CLK1 and CLK2 STB1 and STB2
with each resistor placed as close as possible to the STV7622 itself.
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STV7622 Figure 5. Differential input buffer - waveform timing
Circuit description
DB1-3-5 100 Differential input buffer
VID
DB2-4-6 VIA VIB
(=DB1- 3- 5)
V0
VIA VIB
1.4V
1.0V
0.4V
VID
0
0 -0.4V
tPHLD
90%
tPLHD
90% 50% 50% 10%
OUTn
10%
tFD
STV7622 TCP
CLK1-CLK2 S TB1-S TB2 DB1-DB2 DB3-DB4 DB5-DB6 DB1-DB2
tRD
STV7622 TCP
CLK1-CLK2
STV7622 TCP
Data driver board
CLK1-CLK2
DB3-DB4
DB5-DB6
DB1-DB2
DB1-DB2
DB3-DB4
DB5-DB6
STLVD31
STLVD31
STLVD31
Display controller
Video board
DB1-DB2
11/32
Circuit description
STV7622
5.6
Power output block and EMI control
The high-voltage output stage has a totem pole structure (see Figure 3). The capacitive load is charged to Vpp by the high-side N-channel transistor, T1, and discharged to ground by the low-side N-channel transistor, T2. The status of the power outputs can also be controlled by the configuration pins, POC and /BLK, which can set the power outputs either all High or all Low. Several functions, patented by STMicroelectronics, are implemented in the STV7622 to reduce EMI: SmartSlope: The falling edge of the output pulse consist of 2 slopes (Figure 6 below): a smooth slope followed by a steeper one (typically 4 times faster) The duration of the first slope is set by two logic inputs, FS1 and FS2, according to the table in Figure 6. Figure 6. Output falling edge
tF-SLOW 90%
FS2 0 0 1 1 FS1 0 1 0 1 tF-SLOW 10ns 50ns 100ns 200ns
10% tF-OUT
ConstantSlope: The duration of the output rising edge (Figure 7) is kept constant independent of the value of the capacitive load connected to the output. This solution minimizes the peak current in the power outputs as well as any oscillation phenomenon in the power supplies. In addition, it reduces high-frequency components of the EMI spectrum by suppressing very rapid rising edge transitions on the power outputs. The total duration of the rising edge (tR-OUT) is set by another pair of logic inputs, RS1 and RS2, according to the table in Figure 7 below. Figure 7. Output rising edge
RS2= 0
RS2
RS1
tR-OUT
90%
RS 1 1=
0 0 1 1
0 1 0 1
120ns 230ns 400ns 560ns
1 2= RS
10% tR-OUT
12/32
RS1= 0
STV7622
Circuit description Spread Spectrum: To avoid having too large of a current in the driver during the rising edge of the power outputs, all outputs are not triggered at the same time. Instead, the STV7622 inserts a small delay between the rising edge of two consecutive outputs. This delay depends on picture or image content (see Figure 8). For a dark picture, we have tSSJ-MIN = 1 to 2ns (typ.) between output 1 and any output X, while for a white picture, we have tSSJ-MAX = 100ns (typ.). The SSJ function spreads the discharge current in the scan lines and, therefore, reduces EMI by "spreading" the energy spectrum. Figure 8. Spread spectrum filter
OUT-1 OUT-x
OUT-1 OUT-x
tSSJ-MIN Case #1: Dark picture
tSSJ-MAX Case #2: White picture
13/32
Truth tables
STV7622
6
Table 7.
Truth tables
Shift register truth table
Input pins BS2 L L L L BS1 L L L L DIR L L H H H or L H or L CLK1 CLK2(1) N.C. N.C. N.C. N.C. Shift register function Q output Left / Right shift DB1,2, ... input pins, 6 × 32-bit mode 6 Steady Right / Left shift DB1, 2, ... input pins, 6 × 32-bit mode 6 Steady
L L L L
H H H H
L L H H H or L H or L
N.C. N.C. N.C. N.C.
Left / Right shift DB1,2, 3 input pins, 3 × 64-bit mode Steady Right / Left shift DB1, 2, 3 input pins, 3 × 64-bit mode Steady
H H H H
L L L L
L L H H H or L L or H H or L L or H
Left / Right shift DB1, 2, ... input pins, RSDS mode 6 Steady Right / Left shift DB1, 2, ... input pins, RSDS mode 6 Steady
H H H H
H H H H
L L H H H or L H or L
N.C. N.C. N.C. N.C.
Left / Right shift, DB1,2, ...6 input pins, 2 × 3 × 32-bit mode Steady Left / Right shift, DB1,2, ... input pins, 6 2 × 3 × 32-bit mode Steady
1. CLK2 is not used in LVCMOS operating mode and can be left "open" or "floating".
14/32
STV7622 Table 8.
Qn(1) X X
Truth tables Truth table for power outputs
/STB1 X X /STB2 (2) X X BS1 X X BS2 X X /BLK L H POC X L Driver output all L all H Note Comments Output at Low level Output at High level
X X X X
H H H H
X L X X
L L H H
L H L H
H H H H
H H H H
Qn Qn Qn Qn
(3) (4) (5) (6)
Data latched Data latched Data latched (RSDS) Data latched
L H L H L H L H
L L L L L L L L
X X H H X X X X
L L L L H H H H
L L H H L L H H
H H H H H H H H
H H H H H H H H
L H L H L H L H
(3) (3) (4) (4) (5) (5) (6) (6)
Data copied Data copied Data copied (RSDS) Data copied (RSDS) Data copied Data copied Data copied Data copied
1. Qn is the state of the shift register output (Figure 2). "X" means either High or Low (H or L). 2. /STB2 is not used in LVCMOS operating mode and can be left "open" or "floating". 3. Qn + 1 = DB1, Qn + 2 = DB2, Qn + 3 = DB3, Qn + 4 = DB4, Qn + 5 = DB5, Qn + 6 = DB6; n = {0, 6, 12, 18, ...186}. 4. RSDS mode: Qn + 1 = DB1, Qn + 1 = DB2, Qn + 2 = DB3, Qn + 2 = DB4, Qn + 3 = DB5, Qn + 3 = DB6; n = {0, 6, 12, 18, ...186}. 5. Qn + 1 = DB1, Qn + 2 = DB2, Qn + 3 = DB3; n = {0, 3, 6, 9, ...186, 189}. 6. Qn + 1 = DB1, Qn + 2 = DB2, Qn + 3 = DB3, Qn + 97 = DB4, Qn + 98 = DB5, Qn + 99 = DB6; n = {0, 3, 6, 9, ...186, 189}.
15/32
Absolute maximum ratings
STV7622
7
Table 9.
Symbol Vdd Vcc Vpp Vin Ipout Idout Vout VESD Tjmax Tstg
Absolute maximum ratings
Absolute maximum ratings
Parameter Digital supply range Analog supply range Driver supply range Logic input voltage range Driver output current x
(1), (2), (3)
Value -0.3, +7 -0.3, +7 -0.3, +90 -0.3, Vcc+0.3 - 70/+35 -200 / +300 -0.3, +90 2 100 -50, +150
Units V V V V mA mA V KV C C
Diode output current(1), (2), (3) Output power voltage range ESD susceptibility, Human Body Model (100pF discharged through 1.5Kohms), on all except the VCC pins(4) Maximum junction temperature Storage temperature range
1. Measurements done on one single output, x. The other outputs are either not used or are connected to output x. Assumes junction temperature remains less than Tjmax during measurement. 2. All transient current measurements are made under conditions close to those encountered in a typical application (that is, with duration of any output current spike always less than 300 ns). 3. These parameters are measured during STMicroelectronics' internal qualification which includes temperature characterization on standard as well as corner batches of the process. These parameters are not tested in production. 4. VCC pins withstand 1.3 KV.
16/32
STV7622
Electrical characteristics
8
Electrical characteristics
VCC = VDD = 5V, VPP = 70V, VSSP = VSSLOG = VSSSUB = 0V, TAMB = 25 , C fCLK = 50 MHz, unless otherwise specified.
Table 10.
Symbol Supply Vdd Idd Id d l Idd Vcc Icc_1
Electrical characteristics
Parameter Min. Typ. Max. Units
Digital supply voltage Digital supply current
(1)
4.50 20MHz) (2) 250 4.50 -
5
5.5 10
V A mA A V mA
Digital Dynamic Supply Current (CLK1 freq = Digital Supply Current @ VIH = 2.0V Analog supply voltage
15 500 5 1.1
20 900 5.5 2
Analog supply current in standard transmission mode Analog supply current in RSDS mode (that is, with BS1 = BS2 = L) and with DB1, DB3, DB5, CLK1 and /STB1 less than DB2, DB4, DB6, CLK2 and /STB2, respectively DC power output supply voltage Power output supply current (steady outputs) @ VCC = 0V Power output supply current (steady outputs) @ VCC = 5 V and RS1 = RS2 = L
Icc_2
-
5
10
mA
Vpp Ipph -1 Ip p h - 2
15 300 450
80 20 600
V A A
OUT1 to OUT192 Vpouth Vpoutl Vdouth Vdoutl Power output high level (voltage drop versus Vpp) @ Ipouth = -20mA and Vpp = 70V Power output low level @ Ipoutl = +20mA Output upper diode voltage drop @ Idouth = +30mA (see Figure 9) Output lower diode voltage drop @ Idoutl = -30mA (see Figure 9) 2 3 -2 3.5 6 1 -1 5 10 2 V V V V
Standard Mode, TTL/LVCMOS inputs: CLK1, DIR, /STB1, POC, /BLK, BS1, BS2 and DB1 to DB6 VI H VI L II H II L High level input voltage Low level input voltage High level input current (VIH 2.0V) Low level input current (VIL = 0V) 2 .0 0.8 5 5 V V A A
17/32
Electrical characteristics Table 10.
Symbol
STV7622
Electrical characteristics (continued)
Parameter Min. Typ. Max. Units
RSDS Mode, inputs: CLK1, CLK2, /STB1, /STB2 and DB1 to DB6 Vid Vi c Cin Magnitude of differential input voltage Common mode input range Input capacitance (3) 100 0.5 Vid 400 1.2 600 2. 4 - 0.5 Vid 15 mV V pF
1. For 5V CMOS input logic levels (0 or 5V) 2. All input data is switched at 10MHz rate. 3. Same for TTL and RSDS modes. This parameter is measured during qualification by ST Microelectronics which includes temperature characterization on standard as well as corner batches of the process. This parameter is not tested in production.
Figure 9.
Output test configuration
VPP VPP
ON
Vdouth
OFF
Idouth (*)
Idoutl (**)
OFF
OUTn
+
ON
OUTn Vdoutl
-
VSSP/VSSSUB (*) Output sinking current is considered as positive.
VSSP/VSSSUB (**) Output sourcing current is considered as negative.
18/32
STV7622
AC timing requirements
9
AC timing requirements
VCC = VDD = 4.5V to 5.5V, Tamb = -20 to +85C, C input signal edge maximum rise and fall times (tr, tf) = 3ns.
Table 11.
Symbol tCLK tWHCLK tWLCLK tSDAT tHDAT tHSTB t ST B t SST B
AC timing requirements
Parameter Data clock period Duration of clock pulse at high level Duration of clock pulse at low level Input data set-up time before low-to-high clock transition Input data hold-time after low-to-high clock transition Strobe hold-time after low-to-high clock transition Duration of strobe Low level Strobe set-up time before low-to-high clock transition Min. 16.7 8 .8 8 .8 5 5 5 10 5 Typ. Max. Units ns ns ns ns ns ns ns ns
19/32
AC timing characteristics
STV7622
10
AC timing characteristics
VCC = VDD = 5V, VPP = 70V, VSSP = VSSLOG = VSSSUB = 0V, Tamb = 25 , C Fclk= 60MHz, VILmax = 0.2 × VCC, VIHmin = 0.8 × VCC.
Table 12.
Symbol
AC timing characteristics
Parameter Delay of power output change after CLK1/CLK2 transition Min Typ Max Units
tPHL1 tPLH1
- high to low - low to high Delay of power output change after /STB1/STB2 transition - high to low - low to high Delay of power output change after /BLK transition
-
35 30
100 100
ns ns
tPHL2 tPLH2
-
95 95
ns ns
tPHL3 tPLH3 tR-OUT tR-OUT tR-OUT tR-OUT tF-OUT tF-SLOW tF-SLOW tF-SLOW tF-SLOW
- high to low - low to high Power output rise time(1) (RS = "L" and RS2 = "L") Power output rise time(1) (RS = "H" and RS2 = "L") Power output rise time(1) (RS= "L" and RS2 = "H") Power output rise time(1) (RS = "H" and RS2 = "H") Power output fall time(2) Soft slope duration(3) (FS1 = "L" and FS2 = "L") Soft slope duration(3) (FS1 = "H" and FS2 = "L") Soft slope duration(3) (FS1 = "L" and FS2 = "H") Soft slope duration(3) (FS1 = "H" and FS2 = "H")
90 180 320 470 50 8 40 80 160
25 20 120 230 400 560 10 50 100 200
90 90 150 280 480 670 200 12 60 120 240
ns ns ns ns ns ns ns ns ns ns ns
1. tR-OUT is set externally by inputs RS1 and RS2. 2. Measurement made on one of the 192 power outputs with FS1 = "H" and FS2 = "L". Load capacitor CL = 50pF, all other power outputs Low. 3. tF-SLOW is set externally by inputs FS1 and FS2.
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STV7622 Figure 10. AC characteristic waveforms
AC timing characteristics
Standard mode
CLK
tCLK tW HCLK
50%
tW LCLK
50% 50%
tSDAT DB (input) t ST B /STB
50% 50% 50%
tHDAT
50%
tHSTB
50%
tSSTB t PH L 2 OUT(n) tPLH2
90% 10%
tPHL1
90% 10%
tPLH 1
/BLK
50%
50%
tPHL3
90%
tPLH 3
90% 10% 10%
OU T n
(See sections on output falling/rising edge)
tF-OUT
t R -O U T
Differential mode
tW HCLK CLK1
50%
tCLK tW LCLK
50% 50%
CLK2 tSDAT DB1-3-5 (input)
50% 50%
tHDAT
DB2-4-6 (input) t ST B /STB1
50% 50% 50%
tHSTB
/STB2
tSSTB
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Pad dimensions and positions (in m)
STV7622
11
Pad dimensions and positions (in m)
The reference (x=0, y=0) is the centre of the die. Output pad pitch is 76.5m. Pad placement coordinate values correspond to the center of each bump pad center. Pad size is specified for bumping. Table 13. Pad placement and bump pad dimensions (in microns)
Pad placements X TOP SIDE from left to right OUT192 OUT191 OUT190 OUT189 OUT188 OUT187 OUT186 OUT185 OUT184 OUT183 OUT182 OUT181 OUT180 OUT179 OUT178 OUT177 OUT176 OUT175 OUT174 OUT173 OUT172 OUT171 OUT170 OUT169 OUT168 OUT167 OUT166 -7303.1 -7226.6 -7150.1 -7073.6 -6997.1 -6920.6 -6844.1 -6767.6 -6691.1 -6614.6 -6538.1 -6461.6 -6385.1 -6308.6 -6232.1 -6155.6 -6079.1 -6002.6 -5926.1 -5849.6 -5773.1 -5696.6 -5620.1 -5543.6 -5467.1 -5390.6 -5314.1 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 Y Bump dimensions X Y
Lead pad name
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STV7622 Table 13.
Pad dimensions and positions (in m) Pad placement and bump pad dimensions (in microns) (continued)
Pad placements X OUT165 OUT164 OUT163 OUT162 OUT161 OUT160 OUT159 OUT158 OUT157 OUT156 OUT155 OUT154 OUT153 OUT152 OUT151 OUT150 OUT149 OUT148 OUT147 OUT146 OUT145 OUT144 OUT143 OUT142 OUT141 OUT140 OUT139 OUT138 OUT137 OUT136 OUT135 OUT134 OUT133 -5237.6 -5161.1 -5084.6 -5008.1 -4931.6 -4855.1 -4778.6 -4702.1 -4625.6 -4549.1 -4472.6 -4396.1 -4319.6 -4243.1 -4166.6 -4090.1 -4013.6 -3937.1 -3860.6 -3784.1 -3707.6 -3631.1 -3554.6 -3478.1 -3401.6 -3325.1 -3248.6 -3172.1 -3095.6 -3019.1 -2942.6 -2866.1 -2789.6 Y 624.2 624.2 624.21 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 Bump dimensions X 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 Y 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6
Lead pad name
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Pad dimensions and positions (in m) Table 13.
STV7622
Pad placement and bump pad dimensions (in microns) (continued)
Pad placements X OUT132 OUT131 OUT130 OUT129 OUT128 OUT127 OUT126 OUT125 OUT124 OUT123 OUT122 OUT121 OUT120 OUT119 OUT118 OUT117 OUT116 OUT115 OUT114 OUT113 OUT112 OUT111 OUT110 OUT109 OUT108 OUT107 OUT106 OUT105 OUT104 OUT103 OUT102 OUT101 OUT100 -2713.1 -2636.6 -2560.1 -2483.6 -2407.1 -2330.6 -2254.1 -2177.6 -2101.1 -2024.6 -1948.1 -1871.6 -1795.1 -1718.6 -1642.1 -1565.6 -1489.1 -1412.6 -1336.1 -1259.6 -1183.1 -1106.6 -1030.1 -953.6 -877.1 -800.6 -724.1 -647.6 -571.1 -494.6 -418.1 -341.6 -265.1 Y 624.2 624.2 624.2 624.2 624.2 624.2 624.215 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 Bump dimensions X 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 Y 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6
Lead pad name
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STV7622 Table 13.
Pad dimensions and positions (in m) Pad placement and bump pad dimensions (in microns) (continued)
Pad placements X OUT99 OUT98 OUT97 OUT96 OUT95 OUT94 OUT93 OUT92 OUT91 OUT90 OUT89 OUT88 OUT87 OUT86 OUT85 OUT84 OUT83 OUT82 OUT81 OUT80 OUT79 OUT78 OUT77 OUT76 OUT75 OUT74 OUT73 OUT72 OUT71 OUT70 OUT69 OUT68 OUT67 -188.6 -112.1 -35.6 40.9 117.4 193.9 270.4 346.9 423.4 499.9 576.4 652.9 729.4 805.9 882.4 958.9 1035.4 1111.9 1188.4 1264.9 1341.4 1417.9 1494.4 1570.9 1647.4 1723.9 1800.4 1876.9 1953.4 2029.9 2106.4 2182.9 2259.4 Y 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 Bump dimensions X 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 Y 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6
Lead pad name
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Pad dimensions and positions (in m) Table 13.
STV7622
Pad placement and bump pad dimensions (in microns) (continued)
Pad placements X OUT66 OUT65 OUT64 OUT63 OUT62 OUT61 OUT60 OUT59 OUT58 OUT57 OUT56 OUT55 OUT54 OUT53 OUT52 OUT51 OUT50 OUT49 OUT48 OUT47 OUT46 OUT45 OUT44 OUT43 OUT42 OUT41 OUT40 OUT39 OUT38 OUT37 OUT36 OUT35 OUT34 2335.8 2412.3 2488.9 2565.4 2641.9 2718.4 2794.9 2871.4 2947.9 3024.4 3100.9 3177.4 3253.9 3330.4 3406.9 3483.4 3559.9 3636.4 3712.9 3789.4 3865.9 3942.4 4018.9 4095.4 4171.9 4248.4 4324.9 4401.4 4477.9 4554.4 4630.9 4707.4 4783.9 Y 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 Bump dimensions X 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 Y 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6
Lead pad name
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STV7622 Table 13.
Pad dimensions and positions (in m) Pad placement and bump pad dimensions (in microns) (continued)
Pad placements X OUT33 OUT32 OUT31 OUT30 OUT29 OUT28 OUT27 OUT26 OUT25 OUT24 OUT23 OUT22 OUT21 OUT20 OUT19 OUT18 OUT17 OUT16 OUT15 OUT14 OUT13 OUT12 OUT11 OUT10 OUT9 OUT8 OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUT1 4860.4 4936.9 5013.4 5089.9 5166.4 5242.9 5319.4 5395.9 5472.4 5548.9 5625.4 5701.9 5778.4 5854.9 5931.4 6007.9 6084.4 6160.9 6237.4 6313.9 6390.4 6466.9 6543.4 6619.9 6696.4 6772.9 6849.4 6925.9 7002.4 7078.9 7155.4 7231.9 7308.4 Y 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 624.2 Bump dimensions X 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 Y 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6
Lead pad name
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Pad dimensions and positions (in m) Table 13.
STV7622
Pad placement and bump pad dimensions (in microns) (continued)
Pad placements X Y Bump dimensions X Y
Lead pad name
RIGHT SIDE from top to bottom VSSP4 VSSP5 VSSP6 VPP4 VPP5 VPP6 DUMMY VSSLOG2 VSSSUB2 VDD2 VCC2 DUMMY BOTTOM SIDE from right to left DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY TEST2 TEST1 VDD8 BS2 VSSLOG7 BS1 VDD7 DIR VSSLOG6 FS1 VDD6 6838.2 6749.7 6673.1 6486.3 6409.8 6333.3 6256.8 6103.6 5928.9 5617.8 4783.9 4634.4 4466.3 4325.9 4095.4 3949.6 3709.5 3560.2 3327.0 -622.5 -622.5 -622.5 -622.5 -622.5 -622.5 -622.5 -622.5 -622.5 -622.5 -622.5 -622.5 -622.5 -622.5 -622.5 -622.5 -622.5 -622.5 -622.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 7461.3 7473.2 7473.2 7473.2 7473.2 7473.2 7473.2 7473.2 7473.2 7473.2 7473.2 7461.3 635.2 560.3 485.4 260.1 185.2 110.3 35.5 -39.4 -114.3 -189.2 -555.2 -633.5 65.6 65.6 65.6 65.6 65.6 65.6 65.6 65.6 65.6 65.6 65.6 65.6 4 3 .5 4 3 .5 4 3 .5 4 3 .5 4 3 .5 4 3 .5 4 3 .5 4 3 .5 4 3 .5 4 3 .5 4 3 .5 4 3 .5
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STV7622 Table 13.
Pad dimensions and positions (in m) Pad placement and bump pad dimensions (in microns) (continued)
Pad placements X FS2 VSSLOG5 RS2 VDD5 RS1 VSSLOG4 DUMMY VREF DUMMY DUMMY VDD4 POC VSSLOG3 BLK/ VDD3 CLK1 CLK2 STB1/ STB2/ DB1 DB2 DB3 DB4 DB5 DB6 3178.1 2944.5 2798.8 2629.4 2486.6 2314.1 648.6 117.6 -271.1 -424.1 -572.067 -870.5 -1110.0 -1458.1 -1722.0 -1958.7 -2567.3 -3018.9 -3561.8 -4021.4 -4632.8 -5015.9 -5840.8 -6114.5 -7094.6 Y -622.5 -622.5 -622.5 -622.5 -622.5 -622.5 -622.5 -622.5 -622.5 -622.5 -622.5 -622.5 -622.5 -622.5 -622.5 -622.5 -622.5 -622.5 -622.5 -622.5 -622.5 -622.5 -622.5 -622.5 -622.5 Bump dimensions X 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 43.5 Y 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6 6 5 .6
Lead pad name
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Pad dimensions and positions (in m) Table 13.
STV7622
Pad placement and bump pad dimensions (in microns) (continued)
Pad placements X Y Bump dimensions X Y
Lead pad name
LEFT SIDE from bottom to top VCC1 VDD1 VSSSUB1 VSSLOG1 DUMMY VPP3 VPP2 VPP1 VSSP3 VSSP2 VSSP1 -7474.9 -7474.9 -7474.9 -7474.9 -7474.9 -7474.9 -7474.9 -7474.9 -7474.9 -7474.9 -7462.9 -555.2 -189.2 -114.3 -39.4 35.5 110.3 185.2 260.1 485.5 560.3 635.2 65.6 65.6 65.6 65.6 65.6 65.6 65.6 65.6 65.6 65.6 65.6 4 3 .5 4 3 .5 4 3 .5 4 3 .5 4 3 .5 4 3 .5 4 3 .5 4 3 .5 4 3 .5 4 3 .5 4 3 .5
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STV7622
Tested wafer disclaimer
12
Tested wafer disclaimer
All wafers are tested and guaranteed to comply with this specification until the wafer sawing stage, for a period of ninety (90) days from the delivery date. Please remember that it is the customer's responsibility to test and qualify their application using the STMicroelectronics die. STMicroelectronics is ready to support customers when qualifying the product.
13
Ordering information
Table 14. Order codes
Part number STV7622/BMP Description Tested and usawn bump wafer (u = die)
14
Revision history
Table 15.
Date 29-May-2007
Document revision history
Revision 1 Initial release Changes
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STV7622
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