L6743 L6743Q
High current MOSFET driver
Features
Dual MOSFET driver for synchronous rectified converters High driving current for fast external MOSFET switching Integrated bootstrap diode High frequency operation Enable pin Adaptive dead-time management Flexible gate-drive: 5 V to 12 V compatible High-impedance (HiZ) management for output stage shutdown Preliminary OV protection SO-8 and DFN10 3x3 packages
SO-8
DFN10 3x3
Combined with ST PWM controllers, the driver allows implementing complete voltage regulator solutions for modern high-current CPUs and DCDC conversion in general. L6743, L6743Q embeds high-current drivers for both high-side and low-side MOSFETS. The device accepts flexible power supply (5 V to 12 V) to optimize the gate-drive voltage for High-Side and Low-Side maximizing the System Efficiency. The Bootstrap diode is embedded saving the use of external diodes. Anti shoot-through management avoids high-side and low-side MOSFET to conduct simultaneously and, combined with Adaptive Dead-Time control, minimizes the LS body diode conduction time. L6743, L6743Q embeds Preliminary OV Protection: after Vcc overcomes the UVLO and while the device is in HiZ, the LS MOSFET is turned ON to protect the load in case the output voltage overcomes a warning threshold protecting the output against HS failures. The driver is available is SO-8 and DFN10 3x3 packages
Applications
High current VRM / VRD for desktop / server / workstation CPUs High current and high efficiency DC / DC converters
Description
L6743, L6743Q is a flexible, high-frequency dualdriver specifically designed to drive N-channel MOSFETs connected in synchronous-rectified buck topology.
Table 1.
Device summary
Order code L6743 L6743TR L6743Q L6743QTR Package SO-8 SO-8 DFN10 DFN10 Packaging Tube Tape and reel Tube Tape and reel
June 2008
Rev 2
1/17
www.st.com 1
Contents
L6743, L6743Q
Contents
1 Typical application circuit and block diagram . . . . . . . . . . . . . . . . . . . . 3
1.1 1.2 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Pins description and connection diagrams . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 4
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4.1 4.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
5
Device description and operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5.1 5.2 5.3 5.4 5.5 High-impedance (HiZ) management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Preliminar y OV protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Internal BOOT diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6 7
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
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L6743, L6743Q
Typical application circuit and block diagram
1
1.1
Typical application circuit and block diagram
Application circuit
Figure 1. Typical application circuit
VCC = 5V to 12V CDEC VCC BOOT CHF PWM Input CBULK
VIN = 5V to 12V
L6743
PWM
UGATE
HS L Vout
EN Input
EN
PHASE
GND NC*
L6743 Reference Schematic
LGATE NC*
LS
COUT
1.2
Block diagram
Figure 2. Block diagram
VCC EN
ADAPTIVE ANTI CROSS CONDUCTION 15k GND HS
BOOT UGATE PHASE
VCC
L6743
PWM
CONTROL LOGIC & PROTECTIONS PWM
LS
LGATE
GND
3/17
Pin description and connection diagrams
L6743, L6743Q
2
Pin description and connection diagrams
Figure 3. Pin connection (top view)
1 2 3 4 8
BOOT PWM EN VCC
L6743
7 6 5
UGATE PHASE GND LGATE
BOOT PWM EN VCC VCC
1 2 3 4 5
10 9
L6743Q
8 7 6
UGATE PHASE GND GND LGATE
2.1
Table 2.
Pin n
Pin description
Pin description
Name Function High-side driver supply. This pin supplies the high-side floating driver. Connect through a RBOOT - CBOOT capacitor to the PHASE pin. Internally connected to the cathode of the integrated bootstrap diode. See Section 5.3 for guidance in designing the capacitor value. Control input for the driver, 5 V compatible. This pin controls the state of the driver and which external MOSFET have to be turned-ON according to EN status. If left floating and in conjunction with EN asserted, it causes the driver to enter the high-impedance (HiZ) state which causes all MOSFETs to be OFF. See Section 5.1 for details about HiZ. Enable input for the driver. Internally pulled low by 15 k. Pull high to enable the driver according to the PWM status. If pulled low will cause the drive to enter HiZ state with all MOSFET OFF regardless of the PWM status. See Section 5.1 for details about HiZ. Device and LS driver power supply. Connect to any voltage between 5 V and 12 V. Bypass with low-ESR MLCC capacitor to GND. Low-side driver output. Connect directly to the low-side MOSFET gate. A small series resistor can be useful to reduce dissipated power especially in high frequency applications. All internal references, logic and drivers are referenced to this pin. Connect to the PCB ground plane. High-side driver return path. Connect to the high-side MOSFET source. This pin is also monitored for the adaptive dead-time management and Pre-OV Protection. High-side driver output. Connect to high-side MOSFET gate. Thermal pad connects the Silicon substrate and makes good thermal contact with the PCB. Connect to the PGND plane. (DFN10 only)
DFN10
SO-8
1
1
BOOT
2
2
PWM
3
3
EN
4, 5
4
VCC
6
5
LGATE
7, 8
6
GND
9
7
PHASE
10 PAD
8 -
UGATE TH. PAD
4/17
L6743, L6743Q
Thermal data
3
Thermal data
Table 3.
Symbol
Thermal data
Value Parameter SO8 DFN10 45 5 150 0 to 150 0 to 125 1.15 2.25 C/W C/W C C C W Thermal resistance junction to ambient (Device soldered on 2s2p, 67 mm x 69 mm board) Thermal resistance junction to case Maximum junction temperature Storage temperature range Junction temperature range Maximum power dissipation at 25C (Device soldered on 2s2p PC board) Unit
RthJA RthJC TMAX TSTG TJ PTOT
85 -
4
4.1
Electrical specifications
Absolute maximum ratings
Table 4.
Symbol VCC,VPVCC VBOOT, VUGATE VPHASE VLGATE VPWM, VEN VCC,VPVCC to GND to GND to PHASE to GND to GND to GND to GND
Absolute maximum ratings
Parameter Value -0.3 to 15 41 15 -8 to 26 -0.3 to VCC + 0.3 -0.3 to 7 -0.3 to 15 Unit V V V V V V
5/17
Electrical specifications
L6743, L6743Q
4.2
Table 5.
Symbol
Electrical characteristics
Electrical characteristics (VCC = 12 V15 %, TJ = 0 C to 70 C unless otherwise specified).
Parameter Test conditions Min. Typ. Max. Unit
Supply current and power-ON ICC IBOOT UVLOVCC VCC supply current BOOT supply current VCC turn-ON VCC turn-OFF UGATE and LGATE = OPEN BOOT = 12 V UGATE = OPEN; PHASE to GND; BOOT = 12 V VCC rising VCC falling 3.5 5 2 4.1 mA mA V V
PWM and EN input PWM tHiZ Input high - VPWM_IH Input low - VPWM_IL HiZ hold-off time Input high - VEN_IH EN Input low - VEN_IH Input resistance Gate drivers RHIHS IUGATE RLOHS RHILS ILGATE RLOLS Protections VPRE_OV Pre-OV threshold PHASE rising 1.8 V HS source resistance HS source current (1) HS sink resistance LS source resistance LS source current (1) LS sink resistance BOOT - PHASE = 12 V; 100 mA BOOT - PHASE = 12 V; CUGATE to PHASE = 3.3 nF BOOT - PHASE = 12 V; 100 mA 100 mA CLGATE to GND = 5.6 nF 100 mA 2.3 2 2 1.3 3 1 1.5 2.5 1.8 2.8 A A EN rising EN falling to GND 15 2 0.8 PWM rising PWM falling 150 2 0.8 V V ns V V k
1. Parameter(s) guaranteed by designed, not fully tested in production
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L6743, L6743Q
Device description and operation
5
Device description and operation
L6743, L6743Q provides high-current driving control for both high-side and low-side N-channel MOSFETS connected as step-down DC-DC Converter driven by an external PWM signal. The integrated high-current drivers allow using different types of power MOSFETs (also multiple MOS to reduce the equivalent RDS(on)), maintaining fast switching transition. The driver for the high-side MOSFET use BOOT pin for supply and PHASE pin for return. The driver for the low-side MOSFET use the VCC pin for supply and PGND pin for return. The driver embodies a anti-shoot-through and adaptive dead-time control to minimize LowSide body diode conduction time maintaining good efficiency saving the use of Schottky diodes: when the high-side MOSFET turns off, the voltage on its source begins to fall; when the voltage reaches about 2 V, the low-side MOSFET gate drive voltage is suddenly applied. When the low-side MOSFET turns off, the voltage at LGATE pin is sensed. When it drops below about 1 V, the high-side MOSFET gate drive voltage is suddenly applied. If the current flowing in the inductor is negative, the source of highside MOSFET will never drop. To allow the low-side MOSFET to turn-on even in this case, a watchdog controller is enabled: if the source of the high-side MOSFET doesn't drop, the low-side MOSFET is switched on so allowing the negative current of the inductor to recirculate. This mechanism allows the system to regulate even if the current is negative. Before VCC to overcome the UVLO threshold, L6743, L6743Q keeps firmly-OFF both highside and low-side MOSFETS then, after the UVLO has been crossed, the EN and PWM inputs take the control over driver's operations. EN pin enables the driver: if low will keep all MOSFET OFF (HiZ) regardless of the status of PWM. When EN is high, the PWM input takes the control: if left floating, the internal resistor divider sets the HiZ state: both MOSFETS are kept in the OFF state until PWM transition. After UVLO crossing and while in HiZ, the preliminary-OV protection is activated: if the voltage senses through the PHASE pin overcomes about 1.8 V, the low-side MOSFET is latched ON in order to protect the load from dangerous over-voltage. The driver status is reset from a PWM transition. Driver power supply as well as power conversion input are flexible: 5 V and 12 V can be chosen for high-side and low-side MOSFET voltage drive. Figure 4. Timing diagram (EN = High)
HiZ Window PWM HiZ Window
HS Gate
HiZ HiZ tprop_ L
LS Gate
tdead_LH tdead_HL tprop_H
tprop_L
thold-off
thold-off
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Device description and operation
L6743, L6743Q
5.1
High-impedance (HiZ) management
The driver is able to manage high-impedance state by keeping all MOSFETs in off state in two different ways.
If the EN signal is pulled low, the device will keep all MOSFETs OFF careless of the PWM status. When EN is asserted, if the PWM signal remains in the HiZ window for a time longer than the hold-off time, the device detects the HiZ condition so turning off all the MOSFETs. The HiZ window is defined as the PWM voltage range comprised between VPWM_IL and VPWM_IH. The device exits from the HiZ state only after a PWM transition to logic zero (VPWM < V PWM_IL) . See Figure 4 for details about HiZ timings.
The implementation of the high-impedance state allows the controller that will be connected to the driver to manage high-impedance state of its output, avoiding to produce negative undershoot on the regulated voltage during the shut-down stage. Furthermore, different power management states may be managed such as pre-bias start-up.
5.2
Preliminary OV protection
After VCC has overcome its UVLO threshold and while in HiZ, L6743, L6743Q activates the Preliminary-OV protection. The intent of this protection is to protect the load especially from high-side MOSFET failures during the system start-up. In fact, VRM, and more in general PWM controllers, have a 12 V bus compatible turn-on threshold and results to be non-operative if VCC is below that turnon thresholds (that results being in the range of about 10 V). In case of a high-side MOSFET failure, the controller won't recognize the over voltage until VCC = ~10 V (unless other special features are implemented): but in that case the output voltage is already at the same voltage (~10 V) and the load (CPU in most cases) already burnt. L6743, L6743Q by-pass the PWM controller by latching on the low-side MOSFET in case the PHASE pin voltage overcome 2 V during the HiZ state. When the PWM input exits form the HiZ window, the protection is reset and the control of the output voltage is transferred to the controller connected to the PWM input. Since the driver has its own UVLO threshold, a simple way to provide protection to the output in all conditions when the device is OFF consists in supplying the controller through the 5 VSB bus: 5 VSB is always present before any other voltage and, in case of High-Side short, the low-side MOSFET is driven with 5 V assuring a reliable protection of the load. Preliminary OV is active after UVLO and while the driver is in HiZ state and it is disabled after the first PWM transition. The controller will have to manage its output voltage from that time on.
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L6743, L6743Q
Device description and operation
5.3
Internal BOOT diode
L6743, L6743Q embeds a boot diode to supply the high-side driver saving the use of an external component. Simply connecting an external capacitor between BOOT and PHASE complete the high-side supply connections. To prevent bootstrap capacitor to extra-charge as a consequence of large negative spikes, an external series resistance RBOOT (in the range of few ohms) may be required in series to BOOT pin. Bootstrap capacitor needs to be designed in order to show a negligible discharge due to the high-side MOSFET turn-on. In fact it must give a stable voltage supply to the high-side driver during the MOSFET turn-on also minimizing the power dissipated by the embedded Boot Diode. Figure 5 gives some guidelines on how to select the capacitance value for the bootstrap according to the desired discharge and depending on the selected MOSFET. Figure 5. Bootstrap capacitance design
5.4
Power dissipation
L6743, L6743Q embeds high current drivers for both high-side and low-side MOSFETs: it is then important to consider the power that the device is going to dissipate in driving them in order to avoid overcoming the maximum junction operative temperature. Two main terms contribute in the device power dissipation: bias power and drivers' power.
Device power (PDC) depends on the static consumption of the device through the supply pins and it is simply quantifiable as follow:
PD C = VC C IC C + VP V C C IP V C C
Drivers' power is the power needed by the driver to continuously switch ON and OFF the external MOSFETs; it is a function of the switching frequency and total gate charge of the selected MOSFETs. It can be quantified considering that the total power PSW dissipated to switch the MOSFETs dissipated by three main factors: external gate resistance (when present), intrinsic MOSFET resistance and intrinsic driver resistance. This last term is the important one to be determined to calculate the device power dissipation. The total power dissipated to switch the MOSFETs results:
PS W = FS W ( QG H S P V C C + QG L S V C C )
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Device description and operation
L6743, L6743Q
When designing an application based on L6743, L6743Q it is recommended to take into consideration the effect of external gate resistors on the power dissipated by the driver. External gate resistors helps the device to dissipate the switching power since the same power PSW will be shared between the internal driver impedance and the external resistor resulting in a general cooling of the device. Referring to Figure 6, classical MOSFET driver can be represented by a push-pull output stage with two different MOSFETs: P-MOSFET to drive the external gate high and NMOSFET to drive the external gate low (with their own RDS(on): Rhi_HS, Rlo_HS, Rhi_LS, Rlo_LS). The external power MOSFET can be represented in this case as a capacitance (CG_HS, CG_LS) that stores the gate-charge (QG_HS, QG_LS) required by the external power MOSFET to reach the driving voltage (PVCC for HS and VCC for LS). This capacitance is charged and discharged at the driver switching frequency FSW. The total power Psw is dissipated among the resistive components distributed along the driving path. According to the external gate resistance and the power-MOSFET intrinsic gate resistance, the driver dissipates only a portion of Psw as follow:
R oH RH 1 2 -- --P S W H S = -- C G H S P V C C F s w -----------------------------h-i-----S------------------------ + -----------------------------l--------S------------------------ R 2 + R G a t e H S + R i H S R l o H S + R G a t e H S + R i H S hiHS Rl o L S Rh i L S 1 2 P S W L S = -- C G L S V C C F s w ------------------------------------------------------------- + ------------------------------------------------------------- R 2 + R G a t e L S + R i L S R l o L S + R G a t e L S + R i L S hiLS
The total power dissipated from the driver can then be determined as follow:
P = PD C + PS W H S + PS W L S
Figure 6.
Equivalent circuit for MOSFET drive
VCC
VCC
RhiHS RhiLS
BOOT
RGATELS LGATE
RILS
RGATEHS HGATE
RIHS
CGLS
RloHS
RloLS
CGHS
GND LS DRIVER
LS MOSFET
PHASE HS DRIVER
HS MOSFET
10/17
L6743, L6743Q
Device description and operation
5.5
Layout guidelines
L6743, L6743Q provides driving capability to implement high-current step-down DC-DC converters. The first priority when placing components for these applications has to be reserved to the power section, minimizing the length of each connection and loop as much as possible. To minimize noise and voltage spikes (also EMI and losses) power connections must be a part of a power plane and anyway realized by wide and thick copper traces: loop must be anyway minimized. The critical components, such as the power MOSFETs, must be close one to the other. However, some space between the power MOSFET is still required to assure good thermal cooling and airflow. Traces between the driver and the MOSFETS should be short and wide to minimize the inductance of the trace so minimizing ringing in the driving signals. Moreover, VIAs count needs to be minimized to reduce the related parasitic effect. The use of multi-layer printed circuit board is recommended. Small signal components and connections to critical nodes of the application as well as bypass capacitors for the device supply are also important. Locate the bypass capacitor (VCC, PVCC and BOOT capacitors) close to the device with the shortest possible loop and use wide copper traces to minimize parasitic inductance. Systems that do not use Schottky diodes in parallel to the Low-Side MOSFET might show big negative spikes on the phase pin. This spike can be limited as well as the positive spike but has an additional consequence: it causes the bootstrap capacitor to be over-charged. This extra-charge can cause, in the worst case condition of maximum input voltage and during particular transients, that boot-to-phase voltage overcomes the abs.max.ratings also causing device failures. It is then suggested in this cases to limit this extra-charge by adding a small resistor RBOOT in series to the boot capacitor. The use of RBOOT also contributes in the limitation of the spike present on the BOOT pin. For heat dissipation, place copper area under the IC. This copper area may be connected with internal copper layers through several VIAs to improve the thermal conductivity. The combination of copper pad, copper plane and VIAs under the driver allows the device to reach its best thermal performances. Figure 7. Driver turn-on and turn-off paths
VCC
VCC CGD RGATE LGATE CBOOT CGS CDS RINT
BOOT CGD RGATE HGATE CBOOT CGS CDS RINT
RBOOT
RBOOT
LS DRIVER
GND
LS MOSFET
HS DRIVER
PHASE
HS MOSFET
11/17
Device description and operation
L6743, L6743Q
Figure 8.
External components placement example
Rboot
Cboot
Rboot
Cboot
BOOT PWM EN VCC
1 2 3 4
8 7
L6743
6 5
UGATE PHASE GND LGATE
BOOT PWM EN VCC VCC
1 2 3
10 9 8
L6743Q 7 4
5 6
UGATE PHASE GND GND LGATE
12/17
L6743, L6743Q
Package mechanical data
6
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com
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Package mechanical data
L6743, L6743Q
Table 6.
Dim.
SO-8 mechanical data
mm Min Typ Max 1.75 0.25 1.65 0.51 0.25 5.00 4.00 1.27 5.80 0.25 0.40 6.20 0.50 1.27 228.3 9.8 15.7 Mi n 53.1 3.9 43.3 13.0 7.5 189.0 149.6 50.0 244.1 19.7 50.0 mils Typ Ma x 68.9 9.8 65.0 20.1 9.8 196.9 157.5
A A1 A2 B C
D
1.35 0.10 1.10 0.33 0.19 4.80 3.80
(1)
E e H h L k ddd
0 (min.), 8 (max.) 0.10 3.9
1. Dimensions D does not include mold flash, protru-sions or gate burrs. Mold flash, potrusions or gate burrs shall not exceed 0.15mm (.006inch) in total (both side).
Figure 9.
Package dimensions
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L6743, L6743Q
Package mechanical data
Table 7.
Dim.
DFN10 mechanical data
mm Min Typ 0.90 0.02 0.70 0.20 0.18 0.23 3.00 2.21 2.26 3.00 1.49 1.64 0.50 0.3 0.4 0.75 0.25 0.5 11.8 1.74 58.7 2.31 87.0 0.30 7.1 Max 1.00 0.05 Min 31.5 mils Typ 35.4 0.8 27.6 7.9 9.1 118.1 89.0 118.1 64.6 19.7 15.7 29.5 9.8 19.7 68.5 90.9 11.8 Max 39.4 2.0
A A1 A2 A3 b D D2 E E2 e L M m
0.80
Figure 10. Package dimensions
m
M
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Revision history
L6743, L6743Q
7
Revision history
Table 8.
Date 20-Aug-2007 05-Jun-2008
Document revision history
Revision 1 2 Initial release Updated: Table 6 on page 15 Changes
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L6743, L6743Q
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