ESDALC6V1-1BT2
Single line low capacitance TransilTM for ESD protection
Features
1 line low capacitance TRANSIL diode Very thin package: 0.4 mm max. Bidirectional ESD protection Breakdown Voltage VBR = 6.1 V min. Low diode capacitance (22 pF typ. at 0V) Low leakage current: 100 nA max. @ 3V Very small PCB area: 0.6 mm2 Leadfree package Figure 1. Thin SOD882 Functional diagram
Benefits
High ESD protection level High integration Suitable for high density boards
I/O1
Complies with the following standards
IEC 61000-4-2 level 4 15 kV (air discharge) 8 kV (contact discharge) MIL STD 883G - Method 3015-7: class 3B Human body model
I/O2
Applications
Where transient overvoltage protection in ESD sensitive equipment is required, such as:
Description
The ESDALC6V1-1BT2 is a bidirectional single line TVS diode designed to protect the datalines or other I/O ports against ESD transients. The device is ideal for applications where both reduced line capacitance and board space saving are required.
Computers Printers Communication systems Cellular phone handsets and accessories Video equipment
TM: Transil is a trademark of STMicroelectronics
September 2007
Rev 1
1/10
www.st.com
Characteristics
ESDALC6V1-1BT2
1
Characteristics
Table 1.
Symbol VPP(1) PPP(1) IPP Tj Tstg TL TOP
Absolute maximum ratings (Tamb = 25 C)
Parameter Peak pulse voltage (IEC 61000-4-2 contact discharge) Peak pulse power dissipation (8/20 s) Repetitive peak pulse current (8/20 s) Junction temperature Storage temperature range Maximum lead temperature for soldering during 10 s Operating temperature range Tj initial = Tamb Value 30 100 9 125 - 55 to + 150 260 - 40 to + 125 Unit kV W A C C C C
1. For a surge greater than the maximum values, the diode will fail in short-circuit.
Table 2.
Symbol VRM VBR VCL IRM IPP VF
Electrical characteristics
Parameter Stand-of voltage Breakdown voltage Clamping voltage Leakage current @ VRM Peak pulse current Forward voltage drop VBR @ IR IRM @ VRM max. mA 1 nA 100 V 3 Rd typ. 0.65 T max. 10-4/C 2.5 C@ 0 V Bias typ. pF 22
VBR VRM IR IRM IRM IR VRM VBR V I
Part number
min. V
max. V 8.0
ESDALC6V1-1BT2
6.1
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Characteristics
Figure 2.
Relative variation of peak pulse power versus initial junction temperature
Figure 3.
Peak pulse power versus exponential pulse duration
PPP[Tj initial] / PPP[Tj initial=25C)
1.1 1.0 0.9 0.8 0.7 0.6 100 0.5 0.4 0.3 0.2 0.1 0.0 0 25 50 75 100 125 150 1000
PPP(W)
Tj initial=25C
Tj(C)
10 1
tp(s)
10 100
Figure 4.
Clamping voltage versus peak pulse current (typical values)
Figure 5.
Junction capacitance versus reverse voltage applied (typical values)
IPP(A)
100.0
Tj initial=25C
C(pF)
25
F=1MHz VOSC=30mVRMS Tj=25C
20 10.0 15
10 1.0 5
VCL(V)
0.1 0 5 10 15 20 25 30 35 40 0 0 1 2
VLINE(V)
3 4 5
Figure 6.
Relative variation of leakage current versus junction temperature (typical values)
Figure 7.
ESD response to IEC 61000-4-2 (+15 kV air discharge) on each channel
IR[Tj] / IR[Tj=25C]
100
VR=3V
10
Tj(C)
1 25 50 75 100 125 150
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Ordering information scheme
ESDALC6V1-1BT2
Figure 8.
ESD response to IEC 61000-4-2 (-15 kV air discharge) on each channel
Figure 9.
S21 attenuation measurement result
0.00
- 10.00
- 20.00
- 30.00
- 40.00 100.0k
1.0M
10.0M
f/Hz
100.0M
1.0G
2
Ordering information scheme
Figure 10. Ordering information
ESDA LC 6V1 - 1 B T2
ESD Array Low Capacitance Breakdown Voltage 6V1 = 6.1 Volts min Number of lines Directional B = Bi-directional Package T2 = Thin SOD882
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Package information
3
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Table 3. Thin SOD882 dimensions
D
INDEX AREA (D/2 x E/2)
Dimensions Ref.
E
Millimeters Min. Typ. Max. 0.40 0.05 0.25 0.25 1.00 0.60 0.65 0.45 0.45 0.50 0.50 0.55 0.55 0.30 0.30 Min. 0.012 0.000
Inches Typ. Max. 0.016 0.002
A A1
A b1
INDEX AREA (D/2 x E/2)
0.30 0.00 0.20 0.20
A1
b1 b2 D E
0.008 0.010 0.012 0.008 0.010 0.012 0.039 0.024 0.026 0.018 0.020 0.022 0.018 0.020 0.022
b2
L1
OPTIONAL PIN # 1 ID
L2
e L1 L2
e
Note:
Product marking may be rotated by 90 for assembly plant differentiation. In no case should this product marking be used to orient the component for its placement on a PCB. Only pin 1 mark is to be used for this purpose. Figure 11. Footprint (dimensions in mm) Figure 12. Marking
0.55 0.55
0.50
Pin1
L
Pin 2
0.40
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Package information Figure 13. Tape and reel specifications
ES DALC6V1-1BT2
2.0 0.05
4.0 0.1
Ø 1.55 0.05
1.75 0.1
1.15 0.05
L L
3.5 - 0.05
0.47 0.05
All dimensions in mm
8.0 0.3
0.70 0.05
User direction of unreeling
L
L
L
2.0 0.1
L
L
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Recommendation on PCB assembly
4
4.1
Recommendation on PCB assembly
Stencil opening design
1. General recommendation on stencil opening design a) Stencil opening dimensions: L (Length), W (Width), T (Thickness).
Figure 14. Stencil opening dimensions
L
T
W
b)
General design rule Stencil thickness (T) = 75 ~ 125 m W Aspect Ratio = ---- 1.5 T L×W Aspect Area = --------------------------- 0.66 2T( L + W)
2.
Reference design a) b) Stencil opening thickness: 100 m Stencil opening for leads: Opening to footprint ratio - between 60% and 65%.
Figure 15. Recommended stencil windows position
Package footprint
Lead footprint on PCB Lead footprint on PCB
Stencil window position
0.39 mm
Stencil window position
0.45 mm 0.05 mm 0.05 mm
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Recommendation on PCB assembly
ES DALC6V1-1BT2
4.2
Placement
1. 2. 3. 4. Manual positioning is not recommended. It is recommended to use the lead recognition capabilities of the placement system, not the outline centering Standard tolerance of 0.05 mm is recommended. 3.5 N placement force is recommended. Too much placement force can lead to squeezed out solder paste and cause solder joints to short. Too low placement force can lead to insufficient contact between package and solder paste that could cause open solder joints or badly centered packages. To improve the package placement accuracy, a bottom side optical control should be performed with a high resolution tool. For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is recommended during solder paste printing, pick and place and reflow soldering by using optimized tools.
5. 6.
4.3
PCB design preference
1. 2. To control the solder paste amount, the closed via is recommended instead of open vias. The position of tracks and open vias in the solder area should be well balanced. The symmetrical layout is recommended, in case any tilt phenomena caused by asymmetrical solder paste amount due to the solder flow away.
4.4
Reflow profile
Figure 16. ST ECOPACK recommended soldering reflow profile for PCB mounting
Temperature (C)
260C max 255C 220C 180C 125 C
2C/s recommended 2C/s recommended 6C/s max 6C/s max
3C/s max 3C/s max
0 0 1 2 3 4 5
10-30 sec 90 to 150 sec 90 sec max
6
7
Time (min)
Note:
Minimize air convection currents in the reflow oven to avoid component movement.
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Ordering information
5
Ordering information
Table 4. Ordering information
Marking L(1) Package Thin SOD882 Weight 0.76 mg Base qty 3000 Delivery mode Tape and reel
Order code ESDALC6V1-1BT2
1. The marking can be rotated by 90 to differentiate assembly location
6
Revision history
Table 5.
Date 13-Sep-2007
Revision history
Revision 1 Initial release. Changes
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