STA330
2.0 digital audio processor with FFX digital modulator and analog and digital inputs
Features
! ! ! ! ! ! ! !
Up to 96 dB dynamic range Sample rates from 8 kHz to 192 kHz FFX (digital modulation) class-D driver Digital supply voltage from 1.5 V to 3.6 V Analog supply voltage from 1.5 V to 3.6 V 18-bit audio processing and class-D FFX digital modulator 100-dB SNR analog to digital converter Digital volume control: +36 dB to -105 dB in 0.5 dB steps Software volume update Individual channel and master gain/attenuation Automatic invalid-input detect mute Device summary
Order code Package VFQFPN52 VFQFPN52 Tube Tape and reel Packaging
VFQFPN52
! !
2-channel serial input/output data interface Digitally controlled pop-free operation
! !
Table 1.
STA330 STA33013TR
December 2007
Rev 1
1/55
www.st.com 1
Contents
STA330
Contents
1 2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Connection diagrams and pin descriptions . . . . . . . . . . . . . . . . . . . . . . 5
2.1 2.2 Connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1 3.2 3.3 3.4 Maximum and recommended operating conditions . . . . . . . . . . . . . . . . . . 8 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Lock time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 ADC performance values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4 5
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Digital processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1 5.2 5.3 Signal processing flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 I2C interface disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Volume control and gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6
PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.1 6.2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Configuration examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7
Analog-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.1.1 7.1.2 7.1.3 Digital anti-aliasing filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 21 High-pass filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Programmable gain amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.2 7.3
Application scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Configuration examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8
Serial digital audio interface (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8.1 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
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STA330
Contents
8.2 8.3 8.4
Master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Serial formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8.4.1 8.4.2 8.4.3 8.4.4 DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 I2S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 PCM/IF (non-delayed mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 PCM/IF (delayed mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.5
SAI pass-through . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
9
I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9.1 9.2 9.3 9.4 9.5 9.6 Data transition and change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Star t condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
9.6.1 9.6.2 Byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Multi-byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
9.7
Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
9.7.1 9.7.2 9.7.3 9.7.4 Current address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Current address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Random address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Random address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
10.1 10.2 Summar y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 General registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
11 12 13
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Trademarks and other acknowledgements . . . . . . . . . . . . . . . . . . . . . . 53 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
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Introduction
STA330
1
Introduction
The STA330 is a digital stereo audio processor with analog and digital input. It includes an audio DSP and FFX, a ST proprietary high-efficiency class-D driver. In conjunction with a power device, the STA330 provides high-quality digital amplification. The STA330 contains an on-chip volume/gain control. The PWM amplifier achieves greater than 90% efficiency for longer battery life for portable systems. The STA330 I2CDIS pin disables the audio DSP functions to provide a direct conversion of the input signal into output power (the I2C interface is disabled). This conversion is done without the microcontroller. The STA330 is designed for low-power operation with extremely low-current consumption in standby mode. It is available in the package VFQFPN52, a very thin (1.2 mm thick) package that can be used for small portable applications. Figure 1. Block diagram
BICLKI BICLKO/PWM1A LRCLKI LRCLKO/PWM1B SDATAI SDATAO/PWM2A
RST_N STBY MUTE POWERFAULT/ EAPD
GNDIO
GND33
VDDIO
VCC33
GND2
GND1
Serial digital audio interface PWM driver Digital volume MUX ADC M UX FFX modulator PWM driver PWM out I/F OUT2 A OUT2 B OUT1 A OUT1 B MUX
VBIAS INL VHI VCM VLO INR PGA ADC OSC
TM
PLL
Divider
Control interface
MCLK33 SELCLK33
FILT VDDPLL GNDPLL CLKOUT/ PWM2B
XTI
4/55
I2CDIS
AVCC AGND
XTO
SDA
SCL
VCC2
VCC1
GND
VDD
STA330
Connection diagrams and pin descriptions
2
2.1
Connection diagrams and pin descriptions
Connection diagram
Figure 2. Pin out (package underside view)
27
39
26
40
VFQFPN52 Exposed pad down
14
Exposed pad, EP
52
13
1
5/55
Connection diagrams and pin descriptions
STA330
2.2
Pin description
Table 2.
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Pin list
Name STBY INL INR VBIAS AVDD VHI VLO AGND VCM RST_N CLKOUT GND1 VDD1 MUTE VCC1A OUT1A GND1A GND1B OUT1B VCC1B VCC2B OUT2B GND2B GND2A OUT2A VCC2A GND33 GNDIO1 VDDIO1 VCC33 Type Digital input Analog input Analog input/output Analog input/output Supply Analog input Analog input Ground Analog input/output Digital input Digital output Ground Supply Digital input Supply PWM output Ground Ground PWM output Supply Supply PWM output Ground Ground PWM output Supply Ground Ground Supply Supply Description Standby (active high) ADC left channel line input or microphone input ADC right channel line input ADC microphone bias voltage ADC analog supply ADC high reference voltage ADC low reference voltage ADC analog ground ADC Common mode voltage Reset (active low) Buffered clock output Digital ground Digital supply Mute (active high) Channel 1 PWM A power supply Channel 1 PWM A output Channel 1 PWM A power ground Channel 1 PWM B power ground Channel 1 PWM B output Channel 1 PWM B power supply Channel 2 PWM B power supply Channel 2 PWM B output Channel 2 PWM B power ground Channel 2 PWM A power ground Channel 2 PWM A output Channel 2 PWM A power supply Pre-driver ground I/O ring ground I/O ring supply Pre-driver supply
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STA330 Table 2.
Pin # 31 32 33 34 35
Connection diagrams and pin descriptions Pin list (continued)
Name POWERFAULT/ EAPD TM I2CDIS SCL SDA Type Digital output Digital input Digital input Digital input Digital input/output Digital input Description Power fault signal (active high) / External audio power-down signal Test mode (active high) I2C disable pin (active high) I2C serial clock I2C serial data Master clock input selector: SELCLK33 = 1 -> MCLK33 selected SELCLK33 = 0 -> XTI selected Master clock input 3.3-V capable XTI: crystal input or master clock input 3.3-V capable Crystal input or master clock input Crystal output PLL loop filter terminal PLL analog ground PLL analog supply Digital ground Digital supply Input serial audio interface data Output serial audio interface data Input serial audio interface L/R-clock Output serial audio interface L/R-clock (volume UP when I2CDIS=1) I/O ring ground I/O ring supply Input serial audio interface bit-clock Output serial audio interface bit-clock (volume DOWN when I2CDIS=1) Exposed pad ground
36
SELCLK33
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
MCLK33 XTI XTO FILT GNDPLL VDDPLL GND2 VDD2 SDATAI SDATAO LRCLKI LRCLKO GNDIO2 VDDIO2 BICLKI BICLKO EP
Digital input Digital input Digital output Analog input/output Ground Supply Ground Supply Digital input Digital output Digital input/output Digital input/output Ground Supply Digital input/output Digital input/output Ground
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Electrical specifications
ST A 3 3 0
3
3.1
Electrical specifications
Maximum and recommended operating conditions
Table 3 gives the maximum ratings and Table 4 the recommended operating conditions. Table 3. Absolute maximum ratings
Description Digital supply voltage ADC supply voltage PLL analog supply voltage Power stage supply voltage Pre-driver supply Digital I/O supply Voltage range digital in Voltage range analog in Voltage on output pins Storage temperature Ambient operating temperature -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -40 -20 Mi n Max +4.0 +4.0 +4.0 +4.0 +4.0 +4.0 Unit V V V V V V
Symbol VDD/VDD1/VDD2 AVDD VDDPLL VCC1A/1B/2A/2B VCC33 VDDIO VDI VAI Vo TSTG TAMB
VDDIO +0.3 V AVDD +0.3 V
VDDIO +0.3 V 150 85
oC oC
Note:
All grounds must be within 0.3 V of each other. Table 4. Recommended operating conditions
Parameter Digital supply voltage ADC supply voltage PLL analog supply voltage Power stage supply voltage Pre-driver supply voltage Channel 1 and 2 power ground, pre-driver ground Ambient operating temperature 0 Mi n 1.55 1.8 1.55 1.8 1.8 Typ 1.8 3.3 1.8 3.3 3.3 0 25 70 Max 3.6 3.6 3.6 3.6 3.6 Unit V V V V V V
o
Symbol VDD/VDD1/VDD2 AVDD VDDPLL VCC1A/1B/2A/2B VCC33 GND1, GND2, GND33 TAMB
C
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STA330
Electrical specifications
3.2
Electrical characteristics
Table 5 lists the device electrical characteristics under the conditions nominal supply voltage (see Table 4), LRCLKI frequency (fS) = 48 kHz, input frequency = 1 kHz, and Rload = 32 , unless otherwise specified.
Table 5.
Symbol IstbyL IddL Tds Tdd Tr Tf DNR SNR
Electrical characteristics
Parameter Logic power supply current at standby Logic power supply current at operating Low current dead time (static) High current dead time (dynamic) Rise time Fall time Dynamic range A-weighted Signal-to-noise ratio (A-weighted) Speaker mode Speaker mode 0 dBFS input, 8 speaker -6 dBFS input, 8 speaker Test conditions Min Typ 1.3 15 1 2.5 3 3 96 92 0.1 0.05 0.1 0.05 Max Unit A mA ns ns ns ns dB dB % % % %
THDN
Total harmonic distortion
0 dBFS input, 32 headphone -6 dBFS input, 32 headphone
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Electrical specifications
ST A 3 3 0
3.3
Lock time
Table 6 gives the typical lock time of the PLL using the suggested loop filter on page 18, a 1.8-V supply and 30o C junction temperature. Table 6. PLL lock time
Parameter Lock time 200 s Value
3.4
ADC performance values
Table 7. Programmable gain performance
Parameter Dynamic range, 1 kHz, 3.3-V supply Dynamic range, 1 kHz, 1.8-V supply Dynamic range, 1 kHz, 3.3-V supply A-weighted Dynamic range, 1 kHz, 1.8-V supply A-weighted SNDR 1 kHz, 3.3 V supply SNDR 1 kHz, 1.8 V supply SNDR 1 kHz, 3.3 V supply A-weighted SNDR 1 kHz, 1.8 V supply A-weighted THD 1 kHz, -1 dB input, 1.8-V supply THD 1 kHz, -1 dB input, 3.3-V supply Deviation from linear phase Pass band Pass band ripple Stop band Stop band attenuation Group delay, 8 kHz Group delay, 48 kHz Cross talk, 1.8 V Cross talk, 3.3 V 92 84 75 85 92 84 Min Typ Max Unit dB dB dB dB dB dB dB dB dB dB kHz dB kHz dB ms ms dB dB
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STA330
Appl ic at ions
4
Applications
Figure 3 to Figure 6 below show the circuit diagrams of a typical application with the STA510F. Figure 3. STA330 codec block
PWM output selection
Figure 4.
STA510F power stage block
IC401 IC - STA510F
Binary, Ternary
11/55
Applications Figure 5. Connector and power supply block
STA330
Figure 6.
Direct control and settings block
Table 8.
Components for setting up application
Controller No Yes Yes No Yes No Yes Yes No Yes No Yes No Yes STA510F: PWM2B STA510F: PWM1A Less Comments EAPD (Less mode) POWERFAULT -> EAPD (P mode) STA510F: PWM1B
Component R413 R28 R12 R21 R11 R18 R17
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STA330 Table 8. Components for setting up application (continued)
Controller No Yes No 2-3 2-3 2-3 2-3 (L) No Yes No 1-2 1-2 2-3 1-2 (H) Volume up (Less mode) Volume down (Less mode) 3.3-V supply I2CDIS STA510F: PWM2A Less Comments
Appl ic at ions
Component R25 R16 R22 J7 J6 J5 J4
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Digital processing
STA330
5
Digital processing
The STA330 processor block is a digital block providing two channels of audio processing and channel-mapping capability.
5.1
Signal processing flow
I2S or stereo ADC data can be selected. The I2S frequency range is from 8 kHz to 192 kHz. ADC sampling frequency can be selected from 8 kHz to 48 kHz.
5.2
I2C interface disabled
When pin I2CDIS = 1, the SDA, SCL, LRCLKO and BICLKO pins can be pulled high or low to change certain parameters of operation.
"
SDA = 0: FFX input comes from ADC SDA = 1: FFX input comes from digital audio interface SCL = 0: binary output mode (binary soft start/stop enabled) SCL = 1: phase shift output mode LRCLKO = 0: no volume change LRCLKO = 1: volume up BICLKO = 0: no volume change BICLKO = 1: volume down
"
"
"
At power-up, the master volume is set to -60 dB. When holding pin LRCLKO = 1 and pin BICLKO = 1 simultaneously, the master volume is set to 0 dB. A high pulse on pin LRCLKO causes a master volume change of +0.5 dB and a high pulse on pin BICLKO causes a master volume change of -0.5 dB.
14/55
STA330
Digital processing
5.3
Volume control and gain
The volume control structure of the STA330 consists of individual volume registers for each channel and a master volume register that provides an offset to each channel's volume setting. The individual channel volumes are adjustable in 0.5 dB steps from +36 dB to -91.5 dB. As an example, if register LVOL = 0x00 or +36 dB and register MVOL = 0x18 or -12 dB, then the total gain for the left channel is +24 dB. When the mute bit is set to 1, all channels are muted. The volume control provides a soft mute with the volume ramping down to mute in 4096 samples from the maximum volume setting at the internal processing rate (approximately 48 kHz). Table 9. Master volume offset as a function of register MVOL
MVOL[7:0] 0x00 0x01 0x02 ... 0x78 ... 0xFE 0xFF 0 dB -0.5 dB -1dB ... -60 dB ... -105 dB Hard master mute Volume offset from channel value
Table 10.
Channel volume as a function of registers LVOL and RVOL
Volume +36 dB +35.5 dB +35 dB ... +0.5 dB 0 dB -0.5 dB ... ... -91.5 dB
LVOL/RVOL[7:0] 0x00 0x01 0x02 ... 0x47 0x48 0x49 ... ... 0xFF
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PLL
STA330
6
PLL
Figure 7 shows the main components of the PLL. Figure 7. PLL block diagram
INFIN CLKIN IDF FILT INFIN Buffer INFOUT REFOUT FBCLK VCO LF Charge pump and loop filter VCONT Input frequency divider FBCLK Lock detect
LOCKP
Phase / frequency divider (PFD)
Loop frequency divider
F VCO
STR B STR B _ BYPASS FRAC_CTRL Fractional controller
Output frequency divider
PHI
DITH ER_DISABLE FRAC_INPUT
NDIV
16/55
STA330
PLL
6.1
Functional description
Phase/frequency detector
The phase/frequency detector (PFD) compares the phase difference between the corresponding rising edges of INFIN and FBCLK, (clock output from the loop frequency divider) by generating voltage pulses with widths proportional to the input phase error.
Charge pump and loop filter
This block converts the voltage pulses from the phase/frequency detector to current pulses which charge the loop filter and generate the control voltage for the voltage-controlled oscillator. The loop filter is placed external to the PLL on pin FILT.
Voltage controlled oscillator
The voltage controlled oscillator (VCO) is the oscillator inside the PLL. It produces a frequency output (FVCO) proportional to the input control voltage.
Input frequency divider
This frequency divider divides the PLL input clock CLKIN by a factor called the input division factor (IDF) to generate the PFD input frequency INFIN.
Loop frequency divider
This frequency divider is present within the PLL for dividing FVCO by a factor called the loop division factor (LDF). The output of this block is the FBCLK.
Output frequency divider
The PLL output PHI is generated by dividing the FVCO by the output division factor (ODF). The divider that divides the FVCO to generate the clock to the core is called the output frequency divider. In the STA330, the ODF is fixed to be divisible by 2 and cannot be configured.
Lock-detect circuit
The output of this block (the LOCKP signal) is asserted high when the PLL enters the state of COARSE LOCK in which the output frequency is within 10% (approximately) of the desired frequency. The LOCKP signal is refreshed every 32 cycles of the INFIN. The generated value is based on the result of comparing the number of FBCLK cycles in a window of 14 INFIN cycles. The different cases generated after comparison are as follows.
"
If LOCKP is already at 0, then in the next refresh cycle LOCKP goes to 1 if the number of FBCLK cycles in the 14-cycle INFIN window is 13, 14, or 15. Otherwise LOCKP stays at 0. If LOCKP is already at 1, then in the next refresh cycle LOCKP goes to 0 if the number of FBCLK cycles in the 25-cycle INFIN window is less than 11 or higher than 17, otherwise LOCKP stays at 1. If LOCKP is already at 1 and CLKIN is lost (no longer present on the input pin), LOCKP stays at 1. In this case, the PLL is unlocked.
"
"
17/55
PLL
STA330
PLL filter
Figure 8 shows the PLL filter scheme. Recommended values are R1 = 12.5 k, C1 = 250 pF, and C2 = 82 pF. Figure 8. PLL filter scheme
Vc
R1 C2 C1
Ground
Table 6 on page 10 gives a typical lock time value for the PLL.
6.2
Configuration examples
The STA330 PLL can be configured in two ways:
" "
default startup configuration direct PLL programming
The default startup configuration reads the device defaults. With this configuration, it is not necessary to program the PLL dividers directly as some presets are used. In this mode, the oversampling ratio between pins XTI (or MCLK33) and LRCLKI is fixed to 256. The direct PLL programming bypasses the automatic presets allowing direct programming of the PLL dividers. The output PLL frequency can be determined as following: Output division factor: ODF = 2 Relation between input and output clock frequency: FINFIN = FXTI / IDF If register bit PLLCFG0.FRAC_CTRL = 1 FVCO = FINFIN * (LDF + FRACT / 216 + 1 / 217) FPHI = FVCO / ODF When register bit PLLCFG0.DITHER_DISABLE[1] = 1, the 1 / 217 factor is not in the multiplication. It is recommended to keep register bit PLLCFG0.DITHER_DISABLE[1] = 0, otherwise there can be spurious signals in the output clock spectrum.
18/55
STA330 If register bit PLLCFG0.FRAC_CTRL = 0, then: FVCO = FINFIN * LDF FPHI = FVCO / ODF In the above equations: FRACT = Decimal equivalent of register bit PLLCFG1.FRAC_INPUT[15:0] IDF = Input division factor (refer to previous formulas) LDF = Loop division factor (refer to previous formulas) ODF = Output division factor = 2 FINFIN = INFIN frequency FXTI = XTI frequency FVCO = VCO frequency FPHI = Frequency of the PLL output clock When selecting the value of IDF, LDF and FRACT make sure the following limits are maintained: 2.048 MHz < FXTI < 49.152 MHz 2.048 MHz < FINFIN < 16.384 MHz 65.536 MHz < FVCO < 98.304 MHz
PLL
There are also some additional constraints on IDF and LDF. IDF should be greater than 0, LDF should be greater than 5 if FRAC_CTRL = 0 and greater than 8 if FRAC_CTRL = 1. When automatic settings are not used, the PLL must be configured to generate an internal frequency of N * fS, where fS is the LRCLKI pin frequency. Values of N are given in Table 11. Table 11. Oversampling table
fS ( k H z ) 8 11.025 12 16 22.05 24 32 44.1 48 64 88.2 96 128 176.4 192 4096 4096 4096 2048 2048 2048 1024 1024 1024 512 512 512 256 256 256 N 32.768 45.1584 49.152 32.768 45.1584 49.152 32.768 45.1584 49.152 32.768 45.1584 49.152 32.768 45.1584 49.152 FPHI (MHz)
19/55
PLL
STA330 In the following examples floor means rounded towards zero and round means rounded to nearest integer.
Example 1
FXTI = 13 MHz fS = 44.1 kHz IDF should be equal to 3 otherwise LDF become less than 8 (FRAC_CTRL must be 1): LDF = floor(45.1584 / (13 / IDF)) = 10 FRACT = round([(45.1584 / (13 / IDF)) - floor(45.1584 / (13 / IDF))] * 216) = 27602 Using the above configuration, the system clock is 45.15841675 MHz, the approximate static error is 16 Hz (that is, 0.5 ppm).
Example 2
FXTI = 19.2 MHz fS = 48 kHz IDF should be equal to 4 otherwise LDF become less than 8 (FRAC_CTRL must be 1): LDF = floor(49.152 / (19.2 / IDF)) = 10 FRACT = round([(49.152 / (19.2 / IDF)) - floor(49.152 / (19.2 / IDF))] * 216) = 15728 Using the above configuration, the system clock is 49.151953125 MHz, the approximate static error is 47 Hz (that is, 1 ppm).
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STA330
Analog-digital converter (ADC)
7
7.1
Analog-digital converter (ADC)
Functional description
The STA330 analog input is provided through a low-power, low-voltage, stereo, audio-ADC front end designed for audio applications. It includes a programmable gain amplifier, antialiasing filter, a low-noise microphone biasing circuit, a third-order, MASH2-1, delta-sigma modulator, a digital decimating filter and a first-order DC-removal filter. This device is fabricated using a 0.18 m CMOS process, where high-speed precision analog circuits are combined with high-density logic circuits. The ADC works in a microphone-input (mic-in) mode and in a line-input mode. If the line-input mode is selected, the ADC is configured in stereo and all conversion channels are active. If the microphone-input mode is selected, the ADC is configured in mono. The mono channel is routed through the left conversion path, and the right conversion path is kept in power-down mode to minimize power consumption. A programmable gain amplifier (PGA) is available in mic-in mode, giving the possibility to amplify the signal from 0 to +42 dB in steps of 6 dB.
7.1.1
Digital anti-aliasing filter characteristics
The digital filter characteristics are shown in Table 12. Table 12. Digital filter characteristics
Parameter Pass band Pass band ripple: Fs mode Fs_by_2 mode Fs_by_4 mode Stop band attenuation: Fs mode Fs_by_2 mode Fs_by_4 mode Group delay: Fs mode Fs_by_2 mode Fs_by_4 mode 0.4535 * fS 0.08 dB at 44.1 kHz 0.08 dB at 22.05 kHz 0.08 dB at 11.025 kHz 45 dB at 44.1 kHz 45 dB at 22.05 kHz 45 dB at 11.025 kHz 0.4 ms at 32 kHz 0.7 ms at 16 kHz 1.4 ms at 8 kHz Typical
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Analog-digital converter (ADC)
STA330
7.1.2
High-pass filter characteristics
Table 13. High-pass filter characteristics
Parameter Frequency response: -3 dB -0.08 dB Phase deviation at 20 Hz Pass-band ripple Typical
7 Hz 50 Hz 19.35 0.08 dB
7.1.3
Programmable gain amplifier
The programmable gain amplifier (PGA) is available in mic-in mode only. It is possible to amplify the input signal from 0 to 42 db in steps of 6 db. The setting is done through bits PGA of register ADCCFG on page 47. See Table 7 on page 10 for performance values.
7.2
Application scheme
Figure 9 shows the filter circuit. Figure 9. Block diagram
C9 AC coupled DC coupled C0 AC coupled DC coupled 3-V, 3-A supply VSSA R1 VHI VSSA C6 VLO VCM C7 R1 = 500 C8 = 10 F C9, C0 = 1 F (low ESR) The 3-V, 3-A supply must be low-noise and separate from the other supplies C5 AGND The VSSA plane must be a different plane to the other ground planes AVDD INR C5 = 1 F C6, C7 = 10 F (low ESR and ESL capacitors are recommended) INL
VBIAS C8
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STA330
Analog-digital converter (ADC)
7.3
Configuration examples
The ADC sampling frequency can be selected from three values:
" " "
normal (from 32 kHz to 48 kHz) low (from 16 kHz to 24 kHz) very-low (from 8 kHz to 12 kHz).
The setting is done through bits ADC_FS_RANGE in register MISC on page 48. For all other settings, register ADCCFG on page 47 is used.
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Serial digital audio interface (SAI)
ST A 3 3 0
8
8.1
Serial digital audio interface (SAI)
Specifications
The serial-to-parallel interface and the parallel-to-serial interface can have different sampling rates. The following terms are used in this section:
"
BICLK active edge: Pins SDATAI, SDATAO, LRCLKI, LRCLKO always change synchronously with BITCLK active edges. The active edge can be configured to a rising or falling edge via register programming. BICLK strobe edge: Pins SDATAI, SDATAO, LRCLKI, LRCLKO should be stable near BICLK strobe edges, the slave device is able to use strobe edges to latch serial data internally.
"
8.2
Master mode
In this mode pins BICLKI/BICLKO and pins LRCLKI/LRCLKO are configured as outputs. Figure 10. Master mode
BICLKI/ BICLKO tDL
LRCLKI/ LRCLKO
tDDA SDATAO
SDATAI tDST tDHT
Table 14.
Symbol tDL tDDA tDST tDHT
Master mode
Parameter LRCLKI/LRCLKO propagation delay from BICLK active edge SDATAI propagation delay from BICLKI/O active edge Sdatao setup time to BICLKI/O strobing edge Sdatao hold time from BICLKI/O strobing edge Min 0 0 10 10 Typ Max 10 15 Unit ns ns ns ns
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STA330
Serial digital audio interface (SAI)
8.3
Slave mode
In this mode, pins BICLKI/O and pins LRCLKI/O are configured as inputs. Figure 11. Slave mode
tBCH BICLKI/ BICLKO tBCY LRCLKI/ LRCLKO tDS SDATAO tDH SDATAI tDD tLRH tLRSU tBCL
Table 15.
Symbol tBCY tBCH tBCL tLRSU tLRH tDS tDH tDD
Slave mode
Parameter BICLK cycle time BICLK pulse width high BICLK pulse width low LRCLKI/LRCLKO setup time to BICLK strobing edge LRCLKI/LRCLKO hold time to BICLK strobing edge SDATAO setup time to BICLK strobing edge SDATAO hold time to BICLK strobing edge SDATAI propagation delay from BICLK active edge Min 50 20 20 10 10 10 10 0 10 Typ Max Unit ns ns ns ns ns ns ns ns
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Serial digital audio interface (SAI)
ST A 3 3 0
8.4
Serial formats
Different audio formats are supported in both master and slave modes. Clock and data configurations can be customized to match most of the serial audio protocols available on the market. Data length can be customized for 8-, 16-, 24- and 32-bit. Figure 12. Right justified
LRCLKI/ LRCLKO
BICLKI/ BICLKO
SDATAI/ SDATAO
123
n-1 n
123
n-1 n
Figure 13. Left justified
LRCLKI/ LRCLKO
BICLKI/ BICLKO
SDATAI/ SDATAO
123
n-1 n
123
n -1 n
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STA330
Serial digital audio interface (SAI)
8.4.1
DSP
Figure 14. DSP
LRCLKI/ LRCLKO
BICLKI/ BICLKO Left SDATAI/ SDATAO
123
Right n -1 n 1 2 3 n-1 n
8.4.2
I2S
Figure 15. I2S
LRCLKI/ LRCLKO
BICLKI/ BICLKO
SDATAI/ SDATAO
123
n-1 n
123
n-1 n
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Serial digital audio interface (SAI)
ST A 3 3 0
8.4.3
PCM/IF (non-delayed mode)
" "
MSB first 16-bit data
Figure 16. PCM/IF (non-delayed mode)
Any width LRCLKI/ LRCLKO
BICLKI/ BICLKO
SDATAI/ SDATAO
123
n-1 n
8.4.4
PCM/IF (delayed mode)
" "
MSB first 16-bit data
Figure 17. PCM/IF (delayed mode)
LRCLKI/ LRCLKO
BICLKI/ BICLKO
SDATAI/ SDATAO
123
n-1 n
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STA330
Serial digital audio interface (SAI)
8.5
SAI pass-through
A configuration is available which allows the SAI input signal to be passed straight to the digital output. The STA330 is able to translate the incoming serial audio interface signal from SAI-in to a different output format on SAI-out. So the SAI pass-through enables devices to be cascaded, even devices with slightly different protocols. The pass-through is set by programming register PWMINT1 on page 49 with the value 0x00 and register PWMINT2 with the value 0x01. SAI-in protocol is set up with registers S2PCFG0 on page 39 and S2PCFG1 and SAI-out protocol with P2SCFG0 on page 41 and P2SCFG1. Input and output data sampling frequencies must be the same.
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I2C interface
STA330
9
I2C interface
This section describes the communication protocol of the I2C interface.
9.1
Data transition and change
Data changes on the SDA line must only occur when the SCL clock is low. SDA transition while the clock is high is used to identify a start or stop condition.
9.2
Start condition
A start condition is identified by a high to low transition of the data bus SDA signal while the clock signal SCL is stable in the high state. A start condition must precede any command for data transfer.
9.3
Stop condition
A stop condition is identified by low to high transition of the data bus SDA signal while the clock signal SCL is stable in the high state. A stop condition terminates communication between the STA330 and the master bus.
9.4
Data input
During data input, the STA330 samples the SDA signal on the rising edge of clock SCL. For correct device operation the SDA signal must be stable during the rising edge of the clock and the data can change only when the SCL line is low.
9.5
Device addressing
To start communication between the master and the STA330, the master must initiate with a start condition. Following this, the master sends onto the SDA line 8 bits (MSB first) corresponding to the device select address and read or write mode. The 7 most significant bits are the device address identifiers, corresponding to the I2C bus definition. In the STA330, the I2C interface has the device address 0x34. The 8th bit (LSB) identifies read or write operation (R/W), this bit is set to 1 in read mode and 0 in write mode. After a start condition, the STA330 identifies on the bus the device address and if a match is found, it acknowledges the identification on SDA bus during the 9th bit time. The byte following the device identification byte is the internal space address.
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STA330
I2C interface
9.6
Write operation
Following the start condition the master sends a device select code with the R/W bit set to 0. The STA330 acknowledges this and the writes to the byte of the internal address. After receiving the internal byte address, the STA330 responds with an acknowledgement.
9.6.1
Byte write
In the byte-write mode the master sends one data byte. This is acknowledged by the STA330. The master then terminates the transfer by generating a stop condition.
9.6.2
Multi-byte write
The multi-byte write modes can start from any internal address. The master generates a stop condition which terminates the transfer.
9.7
9.7.1
Read operation
Current address byte read
Following the start condition the master sends a device select code with the R/W bit set to 1. The STA330 acknowledges this and then responds by sending one byte of data. The master then terminates the transfer by generating a stop condition.
9.7.2
Current address multi-byte read
The multi-byte read modes can start from any internal address. Sequential data bytes are read from sequential addresses within the STA330. The master acknowledges each data byte read and then generates a stop condition terminating the transfer.
9.7.3
Random address byte read
Following the start condition the master sends a device select code with the R/W bit set to 0. The STA330 acknowledges this and then the master writes the internal address byte. After receiving the internal byte address, the STA330 again responds with an acknowledgement. The master then initiates another start condition and sends the device select code with the R/W bit set to 1. The STA330 acknowledges this and then responds by sending one byte of data. The master then terminates the transfer by generating a stop condition.
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I2C interface
STA330
9.7.4
Random address multi-byte read
The multi-byte read modes could start from any internal address. Sequential data bytes are read from sequential addresses within the STA330. The master acknowledges each data byte read and then generates a stop condition terminating the transfer.
Figure 18. I2C write operations
ACK Byte Write ACK ACK
Star t
Dev address
R/W ACK
Sub address ACK
Data in ACK
Stop ACK Stop
Multibyte Write Star t
Dev address
R/W
Sub address
Data in
Data in
Figure 19. I2C read operations
ACK Current address read Star t No ACK
Dev address
R/W ACK
Data
Stop ACK ACK No ACK
Random address read Star t
Dev address
R/W
Sub address
Star t
Dev address
R/W
Data
Stop
ACK Sequential current read Star t
ACK
ACK
No ACK
Dev address
R/W=High
Data
Data
Data
Stop
ACK Sequential random read Star t
ACK
ACK
ACK
Dev address
R/W
Sub address
Star t
Dev address
R/W ACK
Data No ACK
Data
Data
Stop
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STA330
Registers
10
10.1
Table 16.
Address
Registers
Summary
Register summary
Name Bit 7 MUTE L1_R2 Bi t 6 POW_STBY MUTE_ON_ INVALID Bit 5 SO FT_ VOL_ON Bit 4 BIN_SOFT START Bi t 3 Bi t 2 Bit 1 Bit 0
0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x0A 0x0B 0x0C 0x0D 0x14 0x15 0x16 0x17 0x18 0x19 0x1E 0x1F 0x20 0x21 0x22 0x23 0x28 0x29
FFXCFG0 FFXCFG1 MVOL LVOL RVOL TTF0 TTF1 TTP0 TTP1 S2PCFG0 S2PCFG1 P2SCFG0 P2SCFG1 PLLCFG0 PLLCFG1 PLLCFG2 PLLCFG3 PLLPFE PLLST ADCCFG CKOCFG MISC PADST0 PADST1 FFXST BISTRUN BISTST0
TIM_SOFT_VOL[3:0] PWM_SHIFT[1:0]
PWM_MODE[1:0]
SET_VOL_MASTER[7:0] SET_VOL_LEFT[7:0] SET_VOL_RIGHT[7:0] TIM_TS_FAULT[15:8] TIM_TS_FAULT[7:0] TIM_TS_POWUP[15:8] TIM_TS_POWUP[7:0] BICLK_ STRB LRCLK_ LEFT SHARE_ BILR MSB_FIRST DATA_FORMAT[2:0] MAP_L[1:0] DATA_FORMAT[2:0] MAP_L[1:0] IDF[3:0] MASTER_ MODE MAP_R[1:0] MASTER_ MODE MAP_R[1:0]
PDATA_LENGTH[1:0] BICLK_ STRB LRCLK_ LEFT
BICLK_OS[1:0] SDATAO_ ACT MSB_FIRST
PDATA_LENGTH[1:0] PLL_DIRECT _PROG FRAC_ CTR L
BICLK_OS[1:0] DITHER_DISABLE[1:0]
FRAC_INPUT[15:8] FRAC_INPUT[7:0] STRB PLL_ BYP_ UNL PLL_ UNLOC K STRB _BYPASS BICLK2PLL PLL_ PWDN PFE1A NDIV[5:0] PFE1B PFE2A PFE2B RESET_ FAULT
PLL_ PLL_ PWD_STATE BYP_STATE PGA[2:0] INSEL STBY BYPASS_ CALIB CLKENBL
CLKOUT_ DIS OSC_DIS
CLKOUT_SEL[1:0] P2P_FS_RANGE[2:0] ADC_FS_RANGE[1:0] Reserved Reserved INVALID_ INP_FBK Reserved Reserved MUTE_ INT_FBK BINSS_FBK P2P_ IN_ ADC CORE_ CLKENBL
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Registers Table 16.
Address
STA330 Register summary (continued)
Name Bit 7 Bi t 6 Bit 5 Bit 4 Reserved Reserved PWM_INT[15:8] PWM_INT[7:0] POWER DOWN POW_ TRISTATE POW_ FAULT1A POW_ FAULT1B POW_ FAULT2A POW_ FAULT2B Bi t 3 Bi t 2 Bit 1 Bit 0
0x2A 0x2B 0x2D 0x2E 0x32
BISTST1 BISTST2 PWMINT1 PWMINT2 POWST
10.2
FFXCFG0
Bit 7 MU TE
General registers
FFX configuration register 0
B it 6 POW_STBY Bit 5 SOFT_VOL_ON Bit 4 BIN_ SOFTSTART B it 3 B it 2 Bit 1 B it 0 TIM_SOFT_VOL[3:0]
Address: Type: Buffer: Reset: Description:
0x00 R/W No 0x75
7 MUTE: 0: default 6 POW_STBY: 0: FFX bridge is in power-up mode 1: FFX bridge is in standby mode (default) 5 SOFT_VOL_ON: 0: smooth transition not active 1: smooth transition when changing volume control (default) 4 BIN_SOFTSTART: Reserved (default is 1) 3:0 TIM_SOFT_VOL: volume control time step for any 0.5 dB volume change Time is 2TIM_SOFT_VOL * 20.83 s Default is 666.66 s
1: FFX output is zero
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STA330
Registers
FFXCFG1
Bit 7 L1_R2 B it 6 MUTE_ON_ INVALID Bit 5
Configuration register 1
Bit 4 B it 3 B it 2 Bit 1 B it 0 PWM_MODE[1:0] PWM_SHIFT[1:0]
Address: Type: Buffer: Reset: Description:
0x01 R/W No 0xF8
7 L1_R2: channel mapping: 0: right channel is mapped to output channel 1 and left channel is mapped to output channel 2 1: left channel is mapped to output channel 1 and right channel is mapped to output channel 2 (default) 6 MUTE_ON_ INVALID: mutes PWM outputs if invalid digital data is received: 0: outputs are not muted 1: outputs are muted (default) 5:4 PWM_MODE[1:0]: 00: binary (output B is opposite of output A) 01: binary headphones (output B is 50% duty cycle) 10: ternary 11: phase shift (default) 3:2 PWM_SHIFT[1:0]: 10: default PWM period-shift between channels 1 and 2 Value is N * 90 Default is 180 1:0 Reserved (default is 0)
MVOL
Bit 7 B it 6 Bit 5
Master volume control
Bit 4 B it 3 B it 2 Bit 1 B it 0 SET_VOL_MASTER[7:0]
Address: Type: Buffer: Reset: Description:
0x02 R/W No 0x00
7:0 SET_VOL_MASTER[7:0]: master volume control: From 0 dB to -127.5 dB in 0.5 dB steps
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Registers
STA330
LVOL
Bit 7 B it 6 Bit 5
Left channel volume control
Bit 4 B it 3 B it 2 Bit 1 B it 0 SET_VOL_LEFT[7:0]
Address: Type: Buffer: Reset: Description:
0x03 R/W No 0x48
7:0 SET_VOL_LEFT[7:0]: left channel volume control: Left channel volume control (from +36 dB to -91.5 dB in 0.5 dB steps) Default value (0x48) corresponds to 0 dB
RVOL
Bit 7 B it 6 Bit 5
Right channel volume control
Bit 4 B it 3 B it 2 Bit 1 B it 0 SET_VOL_RIGHT[7:0]
Address: Type: Buffer: Reset: Description:
0x04 R/W No 0x48
7:0 SET_VOL_RIGHT[7:0]: right channel volume control: Right channel volume control (from +36 dB to -91.5 dB in 0.5 dB steps) Default value (0x48) corresponds to 0 dB
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STA330
Registers
TTF0
Bit 7 B it 6 Bit 5
Tri-state time-after-fault register 0
Bit 4 B it 3 B it 2 Bit 1 B it 0 TIM_TS_FAULT[15:8]
Address: Type: Buffer: Reset: Description:
0x05 R/W No 0x00
7:0 MSBs of TIM_TS_FAULT[15:0]: See TTF1 on page 37.
TTF1
Bit 7 B it 6 Bit 5
Tri-state time-after-fault register 1
Bit 4 B it 3 B it 2 Bit 1 B it 0 TIM_TS_FAULT(7:0)
Address: Type: Buffer: Reset: Description:
0x06 R/W No 0x02
7:0 LSBs of TIM_TS_FAULT[15:0]: time in which power is held in tri-state mode after a fault signal: Time is TIM_TS_FAULT * 83.33 s. Default value (0x0002) corresponds to 166.66 s tri-state time after fault
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Registers
STA330
TTP0
Bit 7 B it 6 Bit 5
Tri-state time-after-power-up register 0
Bit 4 B it 3 B it 2 Bit 1 B it 0 TIM_TS_POWUP[15:8]
Address: Type: Buffer: Reset: Description:
0x07 R/W No 0x00
7:0 MSBs of TIM_TS_POWUP[15:0]: See register TTP1.
TTP1
Bit 7 B it 6 Bit 5
Tri-state time-after-power-up register 1
Bit 4 B it 3 B it 2 Bit 1 B it 0 TIM_TS_POWUP[7:0]
Address: Type: Buffer: Reset: Description:
0x08 R/W No 0x02
7:0 LSBs of TIM_TS_POWUP[15:0]: time in which power is held in tri-state mode after a power-up signal: Time is TIM_TS_POWUP * 83.33 s Default value(0x0002) corresponds to 166.66 s tri-state time after power-up
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STA330
Registers
S2PCFG0
Bit 7 BICLK_STRB B it 6 LRCLK_LEFT Bit 5 SHARE_BILR
Serial-to-parallel audio interface config register 0
Bit 4 MSB_FIRST B it 3 B it 2 DATA_FORMAT[2:0] Bit 1 B it 0 MASTER_ MODE
Address: Type: Buffer: Reset: Description:
0x0A R/W No 0xD2
7 BICLK_STRB: 0: bit clock strobe edge is falling edge, bit clock active edge is rising edge 1: bit clock strobe edge is rising edge, bit clock active edge is falling edge (default) 6 LRCLK_LEFT: 0: left/right clock is low for left channel, high for right channel 1: left/right clock is high for left channel, low for right channel (default) 5 SHARE_BILR: 0: default 1: left/right clock and bit clock are shared between serial-parallel interface and parallel-toserial interface, BICLKI and LRCLKI are used 4 MSB_FIRST: 0: LSB first 1: MSB first (default)
3:1 DATA_FORMAT[2:0]: serial interface protocol format: 000: left Justified 001: I2S (default) 010: right justified 100: PCM no delay 101: PCM delay 111: DSP 0 MASTER_MODE: 0: default 1: serial interface is in master mode
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Registers
STA330
S2PCFG1
Bit 7 B it 6 Bit 5 PDATA_LENGTH[1:0]
Serial-to-parallel audio interface config register 1
Bit 4 B it 3 MAP_L[1:0] B it 2 Bit 1 MAP_R[1:0] B it 0 BICLK_OS[1:0]
Address: Type: Buffer: Reset: Description:
0x0B R/W No 0x91
7:6 PDATA_LENGTH[1:0]: serial-to-parallel interface data length: 10: 24 bits (default) Length is (N+1) * 8 bit 5:4 BICLK_OS[1:0]: bit clock oversampling: 01:64 * fs (default) Value is (N+1) * 32 * fs (where fs = sampling frequency) 3:2 MAP_L[1:0]: left data-mapping slot: 00: slot0 (default) Value is nth slot 1:0 MAP_R[1:0]: right data-mapping slot: 01: slot1 (default) Value is nth slot
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STA330
Registers
P2SCFG0
Bit 7 BICLK_ STRB B it 6 LRCLK_LEFT Bit 5 SDATAO_ACT
Parallel-to-serial audio interface configuration register 0
Bit 4 MSB_FIRST B it 3 B it 2 DATA_FORMAT[2:0] Bit 1 B it 0 MASTER_ MODE
Address: Type: Buffer: Reset: Description:
0x0C R/W No 0xD3
7 BICLK_STRB: defines the bit clock edges: 0: strobe is falling edge, active edge is rising 1: strobe is rising edge, active edge is falling (default) 6 LRCLK_LEFT: defines the channel for the LR clock: 0: clock is low for left channel, high for right channel 1: clock is high for left channel, low for right channel (default) 5 SDATAO_ ACT: sets the behavior of pin SDATAO: 0: output is tri-stated when no data is sent (default) 1: output is never in tri-state (it is 0 when no data is sent) 4 MSB_FIRST: data alignment in the protocol for SDATAI and SDATAO: 0: LSB is the first bit 1: MSB is the first bit (default) 3:1 DATA_FORMAT[2:0]: serial interface protocol format: 000: left justified 001: I2S (default) 010: right justified 100: PCM no delay 101: PCM delay 110: Reserved 111: DSP 0 MASTER_ MODE: selects serial interface master/slave mode: 0: slave 1: master (default)
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Registers
STA330
P2SCFG1
Bit 7 B it 6 Bit 5 PDATA_LENGTH[1:0]
Parallel-to-serial audio interface config register 1
Bit 4 B it 3 MAP_L[1:0] B it 2 Bit 1 MAP_R[1:0] B it 0 BICLK_OS[1:0]
Address: Type: Buffer: Reset: Description:
0x0D R/W No 0x91
7:6 PDATA_LENGTH[1:0]: serial-to-parallel interface data length: 10: 24 bits (default) Length is (PDATA_LENGTH + 1) * 8 bit 5:4 BICLK_OS[1:0]: bit clock oversampling: 01: 64 * fs (default) Value is (BICLK_OS+1) * 32 * fs 3:2 MAP_L[1:0]: left data-mapping slot: 00: slot0 (default) Value is nth slot 1:0 MAP_R[1:0]: right channel data-mapping slot: 01: slot1 (default) Value is nth slot
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STA330
Registers
PLLCFG0
Bit 7 PLL_DIRECT_ PROG B it 6 FRAC_CTRL Bit 5
PLL configuration register 0
Bit 4 B it 3 B it 2 IDF[3:0] Bit 1 B it 0 DITHER_DISABLE[1:0]
Address: Type: Buffer: Reset: Description:
0x14 R/W No 0x00
7 PLL_DIRECT_PROG: PLL programming: 0: default 1: PLL is programmed according to the PLLCFG register settings 6 FRAC_CTRL: 0: default 1: PLL fractional-frequency synthesis is enabled 5:4 DITHER_DISABLE[1:0]: 00: default MSB = 1: disables rectangular PDF dither input to SDM LSB = 1: disables triangular PDF dither input to SDM 3:0 IDF[3:0]: PLL input division factor: 0000: IDF = 1 (default) 0010: IDF = 2 1111: IDF = 15 0001: IDF = 1 ...
PLLCFG1
Bit 7 B it 6 Bit 5
PLL configuration register 1
Bit 4 B it 3 B it 2 Bit 1 B it 0 FRAC_INPUT[15:8]
Address: Type: Buffer: Reset: Description:
0x15 R/W No 0x00
7:0 FRAC_INPUT[15:8]: 16 bits are used to set the fractional part of PLL multiplication factor
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Registers
STA330
PLLCFG2
Bit 7 B it 6 Bit 5
PLL configuration register 2
Bit 4 B it 3 B it 2 Bit 1 B it 0 FRAC_INPUT[7:0]
Address: Type: Buffer: Reset: Description:
0x16 R/W No 0x00
7:0 FRAC_INPUT[7:0]: 16 bits are used to set the fractional part of PLL multiplication factor
PLLCFG3
Bit 7 STRB B it 6 STRB_BYPASS Bit 5
PLL configuration register 3
Bit 4 B it 3 NDIV[5:0] B it 2 Bit 1 B it 0
Address: Type: Buffer: Reset: Description:
0x17 R/W No 0x00
7 STRB: asynchronous strobe input to the fractional controller: 0: default 6 STRB_BYPASS: standby bypass: 0: STRB signal is not bypassed (default) 1: STRB signal is bypassed
5:0 NDIV[5:0]: PLL multiplication factor (integral part) named as loop division factor: 00 00XX: LDF = NA 00 0100: LDF = NA 00 0101: LDF = 5 ... 11 0111: LDF = 55 11 1XXX: LDF = NA
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STA330
Registers
PLLPFE
Bit 7 PLL_BYP_UNL B it 6 BICLK2PLL Bit 5 PLL_PWDN
PLL/POP-free configuration register
Bit 4 PFE1A B it 3 PFE1B B it 2 PFE2A Bit 1 PFE2B B it 0 RESET_FAULT
Address: Type: Buffer: Reset: Description:
0x18 R/W No 0x00
7 PLL_BYP_UNL: PLL bypass: 0: PLL is not bypassed (default) 6 BICLK2PLL: 0: default 5 PLL_PWDN: 0: default
1: PLL is bypassed when not locked 1: BICLKI is input to PLL 1: PLL is put in power-down mode
4 PFE1A: 0: default 1: pop-free resistances are connected to output 1A 3 PFE1B: 0: default 1: pop-free resistances are connected to output 1B 2 PFE2A: 0: default 1: pop-free resistances are connected to output 2A 1 PFE2B: 0: default 1: pop-free resistances are connected to output 2B 0 RESET_FAULT: 0: default 1: fault signal in the I2C register POWST is reset
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Registers
STA330
PLLST
Bit 7 PLL_UNLOCK B it 6 PLL_ PWD_ STATE Bit 5 PLL_ BYP_ STATE
PLL status register (RO)
Bit 4 B it 3 B it 2 Bit 1 B it 0
Address: Type: Buffer: Reset: Description:
0x19 RO No Undefined
7 PLL_UNLOCK: PLL unlock state: 0: PLL is not in unlock state 6 PLL_PWD_ STATE: PLL power-down state: 0: PLL is not in power-down state 5 PLL_BYP_STATE: PLL bypass state: 0: PLL is not in bypass state 4:0 Reserved
1: PLL is in unlock state 1: PLL is in power-down state 1: PLL is in bypass state
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STA330
Registers
ADCCFG
Bit 7 B it 6 PGA[2:0] Bit 5
ADC configuration register
Bit 4 INSEL B it 3 STBY B it 2 BYPASS_CALIB Bit 1 CLKENBL B it 0
Address: Type: Buffer: Reset: Description:
0x1E RO No Undefined
7:5 PGA[2:0]: gain selection bits for the ADC programmable gain amplifier: 000: default Values are from 0 to 42 dB in 6 dB steps 4 INSEL: 0: line input selected (default) 1: microphone input selected (INL is the input) 3 STBY: ADC standby mode: 0: ADC in power-up mode (default) 1: ADC in standby mode
2 BYPASS_CALIB: 0: ADC DC-removal block not bypassed (default) 1: ADC DC-removal block bypassed 1 CLKENBL: Clock enable: 0: system clock not enabled 1: system clock available at ADC input (default) 0 Reserved
CKOCFG
Bit 7 CLKOUT_DIS B it 6 Bit 5 CLKOUT_SEL[1:0]
Clock-out configuration register
Bit 4 B it 3 B it 2 Bit 1 B it 0
Address: Type: Buffer: Reset: Description:
0x1F R/W No Undefined
7 CLKOUT_DIS: CLKOUT PAD disabled 0: default
1: disabled
6:5 CLKOUT_SEL[1:0]: 00: default The CLKOUT output frequency is the PLL output frequency divided by 2CLKOUT_SEL. 4:0 Reserved
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Registers
STA330
MISC
Bit 7 OSC_DIS B it 6 Bit 5
Miscellaneous configuration register
Bit 4 B it 3 B it 2 Bit 1 P2P_IN_ADC B it 0 CORE_ CLKENBL P2P_FS_RANGE[2:0] ADC_FS_RANGE[1:0]
Address: Type: Buffer: Reset: Description:
0x20 R/W No 0x21
7 OSC_DIS: enable/disable crystal oscillator: 0: default
1: disabled
6:4 P2P_FS_RANGE[2:0]: FFX audio frequency range: 000: very low (fs = 8 to 12 kHz) 001: low (fs = 16 to 24 kHz) 010: normal (fs = 32 to 48 kHz) (default) 011: high (fs = 64 to 96 kHz) 1X: very high (fs = 128 to 192 kHz) 3:2 ADC_FS_RANGE[2:0]: ADC audio frequency range: 00: normal (fs = 32 to 48 kHz) (default) 01: low (fs = 16 to 24 kHz) 1X: very low (fs = 8 to 12 kHz) 1 P2P_IN_ADC: FFX input: 0: FFX input is from serial-to-parallel audio interface (default) 1: FFX input is from ADC 0 CORE_CLKENBL: availability of system clock: 0: FFX system clock disabled 1: FFX system clock enabled (default)
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STA330
Registers
FFXST
Bit 7 B it 6 Bit 5
FFX status register
Bit 4 B it 3 B it 2 INVALID_ INP_ FBK Bit 1 MUTE_INT_FBK B it 0
Address: Type: Buffer: Reset: Description:
0x23 RO No Undefined
7:3 Reserved 2 INVALID_INP_FBK: invalid input status: 1: invalid input sent to FFX 1 MUTE_INT_FBK: FFX mute status 1: FFX is in mute state 0 Reserved
PWMINT1
Bit 7 B it 6 Bit 5
PWM driver configuration register 1
Bit 4 B it 3 B it 2 Bit 1 B it 0 PWM_INT1[7:0]
Address: Type: Buffer: Reset: Description:
0x2D R/W No 0x00
7:0 PWM_INT1[7:0]: see Section 8.5: SAI pass-through on page 29
PWMINT2
Bit 7 B it 6 Bit 5
PWM driver configuration register 2
Bit 4 B it 3 B it 2 Bit 1 B it 0 PWM_INT2[7:0]
Address: Type: Buffer: Reset: Description:
0x2E R/W No 0x00
7:0 PWM_INT2[7:0]: see Section 8.5: SAI pass-through on page 29
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Registers
STA330
POWST
Bit 7 POW_ POWERDOWN B it 6 POW_ TRISTATE Bit 5 POW_FAULT1A
Power bridge status register
Bit 4 POW_FAULT1B B it 3 POW_FAULT2A B it 2 POW_FAULT2B Bit 1 B it 0
Address: Type: Buffer: Reset: Description:
0x32 RO No Undefined
7 POW_POWERDOWN: power-down bridge: 0: not in power-down state 6 POW_TRISTATE: 1: power bridge is in tri-state 5 POW_FAULT1A: 1: power bridge 1A is in fault state 4 POW_FAULT1B: 1: power bridge 1B is in fault state 3 POW_FAULT2A: 1: power bridge 2A is in fault state 2 POW_FAULT2B: 1: power bridge 2B is in fault state 1:0 Reserved
1: power-down state
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STA330
Package information
11
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These package have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Table 17 gives the package dimensions for the parameters shown in Figure 20: VFQFPN52 outline below. Figure 20. VFQFPN52 outline
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Package information Table 17. VFQFPN52 dimensions
Dimensions in mm Reference Min A A1 A2 A3 b D D2 E E2 e L ddd 0.180 7.875 2.750 7.875 2.750 0.450 0.350 0.800 Typical 0.900 0.020 0.650 0.250 0.230 8.000 5.700 8.000 5.700 0.500 0.550 0.300 8.125 6.250 8.125 6.250 0.550 0.750 0.080 0.007 0.310 0.108 0.310 0.108 0.018 0.014 Max 1.000 0.050 1.000 Min 0.031 Typical 0.035 0.001 0.026 0.010 0.009 0.315 0.224 0.315 0.224 0.020 0.022
STA330
Dimensions in inches Max 0.039 0.002 0.039
0.012 0.320 0.246 0.320 0.246 0.022 0.030 0.003
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STA330
Trademarks and other acknowledgements
12
Trademarks and other acknowledgements
FFX is a STMicroelectronics proprietary digital modulation technology. ECOPACK is a registered trademark of STMicroelectronics.
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Revision history
STA330
13
Revision history
Table 18.
Date 12-Dec-2007
Document revision history
Revision 1 Initial release Changes
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STA330
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