M48Z58 M48Z58Y
5V, 64Kbit (8Kbit x 8) ZEROPOWER SRAM
Features
Integrated, ultra low power SRAM, power-fail control circuit, and battery READ cycle time equals WRITE cycle time Automatic power-fail chip deselect and WRITE protection WRITE protect voltages: (VPFD = Power-fail deselect voltage) M48Z58: VCC = 4.75 to 5.5V 4.5V VPFD 4.75V M48Z58Y: VCC = 4.5 to 5.5V 4.2V VPFD 4.5V Self-contained battery in the CAPHATTM DIP package Packaging includes a 28-lead SOIC and SNAPHAT top (to be ordered separately) SOIC package provides direct connection for a SNAPHAT top which contains the battery Pin and function compatible with JEDEC standard 8Kbit x 8 SRAMs RoHS compliant Lead-free second level interconnect
28 1 28 1
PCDIP28 (PC) Battery CAPHAT
SNAPHAT (SH) battery
SOH28 (MH)
November 2007
Rev 8
1/23
www.st.com 1
Contents
M48Z58, M48Z58Y
Contents
1 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 2.2 2.3 2.4 Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 VCC noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . 12
3 4 5 6 7
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2/23
M48Z58, M48Z58Y
List of tables
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Read mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Write mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Power down/up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 PMDIP28 28-pin plastic DIP, battery CAPHATTM, pack. mech. data. . . . . . . . . . . . . . . . 17 SOH28 28-lead plastic small outline, battery SNAPHAT, pack. mech. data . . . . . . . . . . 18 SH 4-pin SNAPHAT housing for 48mAh battery, package mechanical data . . . . . . . . . . 19 SH 4-pin SNAPHAT housing for 120mAh battery, pack. mech. data . . . . . . . . . . . . . . . 20 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 SNAPHAT battery table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3/23
List of figures
M48Z58, M48Z58Y
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 DIP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 SOIC connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Read mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Write enable controlled, write mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Chip enable controlled, write mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 PCDIP28 28-pin plastic DIP, battery CAPHATTM, package outline . . . . . . . . . . . . . . . . . 17 SOH28 28-lead plastic small outline, battery SNAPHAT, package outline . . . . . . . . . . . 18 SH 4-pin SNAPHAT housing for 48mAh battery, package outline. . . . . . . . . . . . . . . . . . 19 SH 4-pin SNAPHAT housing for 120mAh battery, package outline . . . . . . . . . . . . . . . . . 20
4/23
M48Z58, M48Z58Y
Description
1
Description
The M48Z58/Y ZEROPOWER RAM is an 8Kbit x 8 non-volatile static RAM that integrates power-fail deselect circuitry and battery control logic on a single die. The monolithic chip is available in two special packages to provide a highly integrated battery backed-up memory solution. The M48Z58/Y is a non-volatile pin and function equivalent to any JEDEC standard 8K x 8 SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets, providing the non-volatility of PROMs without any requirement for special WRITE timing or limitations on the number of WRITEs that can be performed. The 28-pin, 600mil DIP CAPHATTM houses the M48Z58/Y silicon with a long life lithium button cell in a single package. The 28-pin, 330mil SOIC provides sockets with gold plated contacts at both ends for direct connection to a separate SNAPHAT housing containing the battery. The unique design allows the SNAPHAT battery package to be mounted on top of the SOIC package after the completion of the surface mount process. Insertion of the SNAPHAT housing after reflow prevents potential battery damage due to the high temperatures required for device surfacemounting. The SNAPHAT housing is keyed to prevent reverse insertion. The SOIC and battery packages are shipped separately in plastic anti-static tubes or in Tape & Reel form. For the 28-lead SOIC, the battery package (e.g., SNAPHAT) part number is "M4Z28BR00SH1" (see Table 16 on page 21). Figure 1. Logic diagram
VCC
13 A0-A12
8 DQ0-DQ7
W E G
M48Z58 M48Z58Y
VSS
AI01176B
5/23
Description Table 1. Signal names
A0-A12 DQ0-DQ7 E G W VCC VSS NC Address inputs Data inputs / outputs Chip enable input Output enable input WRITE enable input Supply voltage Ground Not connected internally
M48Z58, M48Z58Y
Figure 2.
DIP connections
NC A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 6 7 M48Z58 8 M48Z58Y 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC W NC A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3
AI01177B
Figure 3.
SOIC connections
NC A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 6 7 M48Z58Y 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC W NC A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3
AI01178B
6/23
M48Z58, M48Z58Y Figure 4. Block diagram
Description
A0-A12
LITHIUM CELL VOLTAGE SENSE AND SWITCHING CIRCUITRY
POWER
8K x 8 SRAM ARRAY
DQ0-DQ7
VPFD
E W G
VCC
VSS
AI01394
7/23
Operating modes
M48Z58, M48Z58Y
2
Operating modes
The M48Z58/Y also has its own Power-fail Detect circuit. The control circuitry constantly monitors the single 5V supply for an out of tolerance condition. When VCC is out of tolerance, the circuit write protects the SRAM, providing a high degree of data security in the midst of unpredictable system operation brought on by low VCC. As VCC falls below battery switchover voltage (VSO), the control circuitry connects the battery which maintains data until valid power returns. Table 2.
Mode Deselect WRITE READ READ Deselect Deselect VSO to VPFD (min)(1) 4.75 to 5.5V or 4.5 to 5.5V
Operating modes
VCC E VIH VIL VIL VIL X X G X X VIL VIH X X W X VIL VIH VIH X X DQ0-DQ7 High Z DIN DOUT High Z High Z High Z Power Standby Active Active Active CMOS standby Batter y back-up mode
VSO(1)(1)
1. See Table 10 on page 16 for details.
Note:
X = VIH or VIL; VSO = Battery Back-up Switchover Voltage.
2.1
Read mode
The M48Z58/Y is in the READ Mode whenever W (WRITE Enable) is high, E (Chip Enable) is low. Thus, the unique address specified by the 13 Address Inputs defines which one of the 8,192 bytes of data is to be accessed. Valid data will be available at the Data I/O pins within Address Access time (tAVQV) after the last address input signal is stable, providing that the E and G access times are also satisfied. If the E and G access times are not met, valid data will be available after the latter of the Chip Enable Access time (tELQV) or Output Enable Access time (tGLQV). The state of the eight three-state Data I/O signals is controlled by E and G. If the outputs are activated before tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If the Address Inputs are changed while E and G remain active, output data will remain valid for Output Data Hold time (tAXQX) but will go indeterminate until the next Address Access.
8/23
M48Z58, M48Z58Y Figure 5. Read mode AC waveforms
tAVAV A0-A12 tAVQV tELQV E tELQX tGLQV G tGLQX DQ0-DQ7 VALID tGHQZ VALID
Operating modes
tAXQX tEHQZ
AI01385
Note: Table 3.
Symbol tAVAV tAVQV tELQV tGLQV tELQX(2) tGLQX(2) tEHQZ(2) tGHQZ(2) tAXQX
WRITE Enable (W) = High. Read mode AC characteristics
Parameter(1) Min READ cycle time Address valid to output valid Chip enable low to output valid Output enable low to output valid Chip enable low to output transition Output enable low to output transition Chip enable high to output Hi-Z Output enable high to output Hi-Z Address transition to output transition 10 5 5 25 25 70 70 70 35 M48Z58/Y Unit Max ns ns ns ns ns ns ns ns ns
1. Valid for ambient operating temperature: TA = 0 to 70C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted). 2. CL = 5pF (see Figure 9 on page 14).
2.2
Write mode
The M48Z58/Y is in the WRITE Mode whenever W and E are low. The start of a WRITE is referenced from the latter occurring falling edge of W or E. A WRITE is terminated by the earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W must return high for a minimum of tEHAX from Chip Enable or tWHAX from WRITE Enable prior to the initiation of another READ or WRITE cycle. Data-in must be valid tDVWH prior to the end of WRITE and remain valid for tWHDX afterward. G should be kept high during WRITE cycles to avoid bus contention; although, if the output bus has been activated by a low on E and G, a low on W will disable the outputs tWLQZ after W falls.
9/23
Operating modes Figure 6. Write enable controlled, write mode AC waveforms
tAVAV A0-A12 VALID tAVWH tAVEL E tWLWH tAVWL W tWLQZ tWHDX DQ0-DQ7 DATA INPUT tDVWH
M48Z58, M48Z58Y
tWHAX
tWHQX
AI01386
Figure 7.
Chip enable controlled, write mode AC waveforms
tAVAV A0-A12 VALID tAVEH tAVEL E tAVWL W tEHDX DQ0-DQ7 DATA INPUT tDVEH
AI01387B
tELEH
tEHAX
10/23
M48Z58, M48Z58Y Table 4.
Symbol tAVAV tAVWL tAVEL tWLWH t ELEH tWHAX tEHAX tDVWH tDVEH tWHDX tEHDX tWLQZ(2)(3) tAVWH tAVEH tWHQX(2)(3) WRITE cycle time Address valid to WRITE enable low Address valid to chip enable low WRITE enable pulse width Chip enable low to chip enable high WRITE enable high to address transition Chip enable high to address transition Input valid to WRITE enable high Input valid to chip enable high WRITE enable high to input transition Chip enable high to input transition WRITE enable low to output Hi-Z Address valid to WRITE enable high Address valid to chip enable high WRITE enable high to output transition 60 60 5
Operating modes Write mode AC characteristics
Parameter(1) M48Z58/Y Unit Min 70 0 0 50 55 0 0 30 30 5 5 25 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
1. Valid for ambient operating temperature: TA = 0 to 70C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted). 2. CL = 5pF (see Figure 9 on page 14). 3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
2.3
Data retention mode
With valid VCC applied, the M48Z58/Y operates as a conventional BYTEWIDETM static RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write protecting itself when VCC falls within the VPFD (max), VPFD (min) window. All outputs become high impedance, and all inputs are treated as "Don't care."
Note:
A power failure during a WRITE cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the RAM's content. At voltages below VPFD (min), the user can be assured the memory will be in a write protected state, provided the VCC fall time is not less than tF. The M48Z58/Y may respond to transient noise spikes on VCC that reach into the deselect window during the time the device is sampling VCC. Therefore, decoupling of the power supply lines is recommended. When VCC drops below VSO, the control circuit switches power to the internal battery which preserves data. The internal button cell will maintain data in the M48Z58/Y for an accumulated period of at least 10 years when VCC is less than VSO. As system power returns and VCC rises above VSO, the battery is disconnected, and the power supply is switched to external VCC. Normal RAM operation can resume trec after VCC exceeds VPFD (max). For more information on Battery Storage Life refer to the Application Note AN1012.
11/23
Operating modes
M48Z58, M48Z58Y
2.4
VCC noise and negative going transients
ICC transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if capacitors are used to store energy which stabilizes the VCC bus. The energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1F (see Figure 8) is recommended in order to provide the needed filtering. In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on VCC that drive it to values below VSS by as much as one volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, ST recommends connecting a schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). (Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is recommended for surface mount). Figure 8. Supply voltage protection
VCC VCC
0.1F
DEVICE
VSS
AI02169
12/23
M48Z58, M48Z58Y
Maximum rating
3
Maximum rating
Stressing the device above the rating listed in the "Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Table 5.
Symbol TA TSTG TSLD(1)(2) VIO VCC IO PD
Absolute maximum ratings
Parameter Ambient operating temperature SNAPHAT Storage temperature (VCC off, oscillator off) Lead solder temperature for 10 seconds Input or output voltages Supply voltage Output current Power dissipation
Value 0 to 70 top 40 to 85 40 to 85 55 to 125 260 0.3 to 7.0 0.3 to 7.0 20 1
Unit C C C C C V V mA W
CAPHAT DIP SOIC
1. For DIP package: Soldering temperature not to exceed 260C for 10 seconds (total thermal budget not to exceed 150C for longer than 30 seconds). 2. For SO package, Lead-free (Pb-free) lead finish: Reflow at peak temperature of 260C (total thermal budget not to exceed 245C for greater than 30 seconds).
Caution: Caution:
Negative undershoots below 0.3V are not allowed on any pin while in the battery back-up mode. Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
13/23
DC and AC parameters
M48Z58, M48Z58Y
4
DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the Measurement Conditions listed in Table 6: Operating and AC measurement conditions. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 6. Operating and AC measurement conditions
Parameter Supply voltage (VCC) Ambient operating temperature (TA) Load capacitance (CL) Input rise and fall times Input pulse voltages Input and output timing ref. voltages M48Z58 4.75 to 5.5V 0 to 70 100 5 0 to 3 1.5 M48Z58Y 4.5 to 5.5 0 to 70 100 5 0 to 3 1.5 Unit V C pF ns V V
Note:
Output Hi-Z is defined as the point where data is no longer driven. Figure 9. AC measurement load circuit
5V
1.9k DEVICE UNDER TEST 1k
OUT
CL = 100pF or 5pF
CL includes JIG capacitance
AI01030
Table 7.
Symbol CIN CIO
(3)
Capacitance
Parameter(1)(2) Input capacitance Input / output capacitance Min Ma x 10 10 Unit pF pF
1. Effective capacitance measured with power supply at 5V. Sampled only, not 100% tested. 2. At 25C, f = 1MHz. 3. Outputs deselected.
14/23
M48Z58, M48Z58Y Table 8.
Symbol ILI ILO(2) ICC ICC1 ICC2 VIL VIH VOL VOH
DC and AC parameters
DC characteristics
Parameter Input leakage current Output leakage current Supply current Supply current (standby) TTL Supply current (standby) CMOS Input low voltage Input high voltage Output low voltage Output high voltage IOL = 2.1mA IOH = 1mA 2.4 Test condition(1) 0V VIN VCC 0V VOUT VCC Outputs open E = VIH E = VCC 0.2V 0.3 2.2 Min Max 1 1 50 3 3 0.8 VCC + 0.3 0.4 Unit A A mA mA mA V V V V
1. Valid for ambient operating temperature: TA = 0 to 70C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted). 2. Outputs deselected.
Figure 10. Power down/up mode AC waveforms
VCC VPFD (max) VPFD (min) VSO tF tFB tPD INPUTS
RECOGNIZED
tR tRB tDR DON'T CARE trec
RECOGNIZED
HIGH-Z OUTPUTS VALID
(PER CONTROL INPUT)
VALID
(PER CONTROL INPUT)
AI01168C
Table 9.
Symbol tPD tF
(2) (3)
Power down/up AC characteristics
Parameter(1) E or W at VIH before power down VPFD (max) to VPFD (min) VCC fall time VPFD (min) to VSS VCC fall time VPFD (min) to VPFD (max) VCC rise time VSS to VPFD (min) VCC rise time VPFD (max) to inputs recognized Min 0 300 10 10 1 40 200 M ax Unit s s s s s ms
tFB
tR tRB trec
1. Valid for ambient operating temperature: TA = 0 to 70C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted). 2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200s after VCC passes VPFD (min). 3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
15/23
DC and AC parameters Table 10.
Symbol VPFD VSO tDR(3)
M48Z58, M48Z58Y Power down/up trip points DC characteristics
Parameter(1)(2) Min M48Z58 M48Z58Y 4.5 4.2 Typ 4.6 4.35 3.0 10 Max 4.75 4.5 Unit V V V YEARS
Power-fail deselect voltage
Battery back-up switchover voltage Expected data retention time
1. All voltages referenced to VSS. 2. Valid for ambient operating temperature: TA = 0 to 70C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted). 3. At 25C, VCC = 0V.
16/23
M48Z58, M48Z58Y
Package mechanical data
5
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 11. PCDIP28 28-pin plastic DIP, battery CAPHATTM, package outline
A2
A
A1 B1 B e3 D
N
L eA
C
e1
E
1 PCDIP
Note:
Drawing is not to scale. Table 11.
Symbol Typ A A1 A2 B B1 C D E e1 e3 eA L N Min 8.89 0.38 8.38 0.38 1.14 0.20 39.37 17.83 2.29 29.72 15.24 3.05 28 Max 9.65 0.76 8.89 0.53 1.78 0.31 39.88 18.34 2.79 36.32 16.00 3.81 Typ Min 0.350 0.015 0.330 0.015 0.045 0.008 1.550 0.702 0.090 1.170 0.600 0.120 28 Max 0.380 0.030 0.350 0.021 0.070 0.012 1.570 0.722 0.110 1.430 0.630 0.150
PMDIP28 28-pin plastic DIP, battery CAPHATTM, pack. mech. data
mm inches
17/23
Package mechanical data
M48Z58, M48Z58Y
Figure 12. SOH28 28-lead plastic small outline, battery SNAPHAT, package outline
A2 B e
A C eB CP
D
N
E
H A1 L
1 SOH-A
Note:
Drawing is not to scale. Table 12. SOH28 28-lead plastic small outline, battery SNAPHAT, pack. mech. data
mm Symbol Typ A A1 A2 B C D E e eB H L a N CP 1.27 0.05 2.34 0.36 0.15 17.71 8.23 3.20 11.51 0.41 0 28 0.10 Min Max 3.05 0.36 2.69 0.51 0.32 18.49 8.89 3.61 12.70 1.27 8 0.050 0.002 0.092 0.014 0.006 0.697 0.324 0.126 0.453 0.016 0 28 0.004 Typ Min Max 0.120 0.014 0.106 0.020 0.012 0.728 0.350 0.142 0.500 0.050 8 inches
18/23
M48Z58, M48Z58Y
Package mechanical data
Figure 13. SH 4-pin SNAPHAT housing for 48mAh battery, package outline
A1
A2 A A3
eA D
B eB
L
E
SHZP-A
Note:
Drawing is not to scale. Table 13.
Symbol Typ A A1 A2 A3 B D E eA eB L 0.46 21.21 14.22 15.55 3.20 2.03 6.73 6.48 Min Max 9.78 7.24 6.99 0.38 0.56 21.84 14.99 15.95 3.61 2.29 0.018 0.835 0.560 0.612 0.126 0.080 0.265 0.255 Typ Min Max 0.385 0.285 0.275 0.015 0.022 0.860 0.590 0.628 0.142 0.090
SH 4-pin SNAPHAT housing for 48mAh battery, package mechanical data
mm inches
19/23
Package mechanical data
M48Z58, M48Z58Y
Figure 14. SH 4-pin SNAPHAT housing for 120mAh battery, package outline
A1
A2 A A3
eA D
B eB
L
E
SHZP-A
Note:
Drawing is not to scale. Table 14.
Symb Typ A A1 A2 A3 B D E eA eB L 0.46 21.21 17.27 15.55 3.20 2.03 8.00 7.24 Min Max 10.54 8.51 8.00 0.38 0.56 21.84 18.03 15.95 3.61 2.29 0.018 0.835 0.680 0.612 0.126 0.080 0.315 0.285 Typ Min Max 0.415 0.335 0.315 0.015 0.022 0.860 0.710 0.628 0.142 0.090
SH 4-pin SNAPHAT housing for 120mAh battery, pack. mech. data
mm inches
20/23
M48Z58, M48Z58Y
Part numbering
6
Part numbering
Table 15.
Example: Device type M48Z Supply voltage and write protect voltage 58(1) = VCC = 4.75 to 5.5V; VPFD = 4.5 to 4.75V 58Y = VCC = 4.5 to 5.5V; VPFD = 4.2 to 4.5V Speed 70 = 70ns (for M48Z58/Y) Package PC = PCDIP28 MH(2) = SOH28 Temperature range 1 = 0 to 70C Shipping method For SOH28: E = ECOPACK package, tubes F = ECOPACK package, tape & reel For PCDIP28: blank = ECOPACK package, tubes
1. The M48Z58 part is offered with the PCDIP28 (ie., CAPHATTM) package only. 2. The SOIC package (SOH28) requires the SNAPHAT battery package which is ordered separately under the part number "M4Zxx-BR00SH1" in plastic tubes (see Table 16).
Ordering information scheme
M48Z 58Y 70 MH 1 E
Caution:
Do not place the SNAPHAT battery package "M4Zxx-BR00SH1" in conductive foam as it will drain the lithium button-cell battery. For other options, or for more information on any aspect of this device, please contact the ST sales office nearest you. Table 16. SNAPHAT battery table
Description Lithium Battery (48mAh) SNAPHAT Lithium Battery (120mAh) SNAPHAT Package SH SH
Part number M4Z28-BR00SH1 M4Z32-BR00SH1
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Revision history
M48Z58, M48Z58Y
7
Revision history
Table 17.
Date March 1999 10-Feb-2000 22-Feb-2000 14-Sep-2001 29-May-2002 16-Sep-2002 02-Apr-2003 23-Mar-2004 23-Nov-2004 09-Jun-2005 14-Dec-2005 06-Nov-2007
Document revision history
Revision 1.0 1.1 1.2 2.0 2.1 2.2 3.0 4.0 5.0 6.0 7.0 8.0 First issue 2-socket SOH and 2-pin SH packages removed Data retention mode paragraph changed Reformatted; added temperature information (Table 7, 8, 3, 4, 9, 10) Modify reflow time and temperature footnotes (Table 5) Remove footnote from ordering information (Table 15) v2.2 template applied; test condition updated (Table 10) Reformatted; updated lead-free information (Table 5, 15) Remove references to industrial temperature grade (Table 3, 4, 5, 6, 8, 9, 10, 15) Removal of SNAPHAT, industrial temperature sales types (Table 3, 4, 5, 6, 7, 8, 10, 15) Updated Lead-free text (Table 15) Reformatted; added lead-free second level interconnect information to cover page and Section 5: Package mechanical data; updated Table 5, 15, 16. Changes
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M48Z58, M48Z58Y
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