M48T201Y M48T201V
5.0 or 3.3 V TIMEKEEPER supervisor
Features
Converts low power SRAM into NVRAMs Year 2000 compliant Battery low flag Integrated real time clock, power-fail control circuit, battery and crystal Watchdog timer Choice of write protect voltages (VPFD = power-fail deselect voltage): M48T201Y: VCC = 4.5 to 5.5 V 4.1V VPFD 4.5 V M48T201V: VCC = 3.0 to 3.6 V 2.7 V VPFD 3.0 V Microprocessor power-on reset (valid even during battery back-up mode.) Programmable alarm output active in the battery backed-up mode Packaging includes a 44-lead SOIC and SNAPHAT top (to be ordered separately) SOIC package provides direct connection for a SNAPHAT top which contains the battery and crystal RoHS compliant Lead-free second level interconnect
44 1
SNAPHAT (SH) crystal/battery
SOH44 (MH) 44-pin SOIC
April 2008
Rev 6
1/35
www.st.com 1
Contents
M48T201Y, M48T201V
Contents
1 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 2.2 2.3 2.4 Address decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3
Clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 TIMEKEEPER registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Reading the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Setting the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Stopping and starting the oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Setting the alarm clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Square wave output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Reset inputs (RSTIN1 & RSTIN2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Calibrating the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Battery low warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Initial power-on defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 VCC noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . 25
4 5 6 7 8
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2/35
M48T201Y, M48T201V
List of tables
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Read mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Write mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 TIMEKEEPER register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Alarm repeat modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Square wave output frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Reset AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Default values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 DC and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Power down/up mode AC characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 SOH44 44-lead plastic small outline, SNAPHAT, pack. mech. . . . . . . . . . . . . . . . . . . . . 30 SH 4-pin SNAPHAT housing for 48 mAh battery & crystal, pack. mech. data. . . . . . . . . 31 SH 4-pin SNAPHAT housing for 120 mAh battery & crystal, pack. mech. data. . . . . . . . 32 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 SNAPHAT battery table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
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List of figures
M48T201Y, M48T201V
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 SOIC connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 GCON timing when switching between RTC and external SRAM . . . . . . . . . . . . . . . . . . . . 10 Read cycle timing: RTC and external RAM control signals . . . . . . . . . . . . . . . . . . . . . . . . 11 Write cycle timing: RTC and external RAM control signals. . . . . . . . . . . . . . . . . . . . . . . . . 13 Alarm interrupt reset waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Back-up mode alarm waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 RSTIN1 and RSTIN2 timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Calibration waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 AC testing load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 SOH44 44-lead plastic small outline, SNAPHAT, package outline . . . . . . . . . . . . . . . . . 30 SH 4-pin SNAPHAT housing for 48 mAh battery & crystal, package outline. . . . . . . . . . 31 SH 4-pin SNAPHAT housing for 120 mAh battery & crystal, pack. outline . . . . . . . . . . . 32
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M48T201Y, M48T201V
Description
1
Description
The M48T201Y/V are self-contained devices that include a real time clock (RTC), programmable alarms, a watchdog timer, and a square wave output which provides control of up to 512 K x 8 of external low-power static RAM. Access to all RTC functions and the external RAM is the same as conventional bytewide SRAM. The 16 TIMEKEEPER registers offer year, month, date, day, hour, minute, second, calibration, alarm, century, watchdog, and square wave output data. Externally attached static RAMs are controlled by the M48T201Y/V via the GCON and ECON signals. The 44-pin, 330 mil SOIC provides sockets with gold plated contacts at both ends for direct connection to a separate SNAPHAT housing containing the battery and crystal. The unique design allows the SNAPHAT battery package to be mounted on top of the SOIC package after the completion of the surface mount process. Inser tion of the SNAPHAT housing after reflow prevents potential battery damage due to the high temperatures required for device surface-mounting. The SNAPHAT housing is keyed to prevent reverse insertion. The SOIC and battery packages are shipped separately in plastic anti-static tubes or in tape & reel form. For the 44-lead SOIC, the battery/crystal package (e.g., SNAPHAT) part number is "M4Txx-BR12SH" (see Table 19 on page 33).
Caution:
Do not place the SNAPHAT battery/crystal top in conductive foam as this will drain the lithium button-cell battery.
Figure 1.
Logic diagram
VCC
19 A0-A18 WDI W E G RSTIN1 RSTIN2 M48T201Y M48T201V
8 DQ0-DQ7 IRQ/FT RST GCON ECON SQW VOUT
VSS
AI02240
5/35
Description Table 1. Signal names
A0-A18 DQ0-DQ7 RSTIN1 RSTIN2 RST WDI E G W ECON GCON IRQ/FT SQW VOUT VCC VSS NC Address inputs Data inputs / outputs Reset 1 Input Reset 2 Input Reset output (open drain) Watchdog Input Chip enable Input Output enable Input WRITE enable input RAM chip enable output RAM enable output
M48T201Y, M48T201V
Interrupt / frequency test output (open drain) Square wave output Supply voltage output Supply voltage Ground Not connected internally
6/35
M48T201Y, M48T201V Figure 2. SOIC connections
RSTIN1 RSTIN2 RST NC A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 WDI GCON DQ0 DQ1 DQ2 VSS 1 2 3 4 5 6 7 8 9 10 11 M48T201Y 12 M48T201V 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 VCC VOUT SQW IRQ/FT A17 A15 A13 A8 A9 A11 G W NC A10 E ECON DQ7 DQ6 DQ5 DQ4 DQ3 NC
Description
AI02241
7/35
Description Figure 3. Hardware hookup
M48T201Y, M48T201V
A0-A18 32,768 Hz CRYSTAL VOUT 0.1F 5V LITHIUM CELL M48T201Y/V VCC (1) E2
A0-Axx
VCC 0.1F E W G WDI RSTIN1 RSTIN2 VSS GCON RST IRQ/FT SQW DQ0-DQ7 VSS DQ0-DQ7 ECON E W G CMOS SRAM
AI00604
1. If the second chip enable pin (E2) is unused, it should be tied to VOUT.
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M48T201Y, M48T201V
Operation
2
Operation
Automatic backup and write protection for an external SRAM is provided through VOUT, ECON, and GCON pins. (Users are urged to insure that voltage specifications, for both the SUPERVISOR chip and external SRAM chosen, are similar.) The SNAPHAT containing the lithium energy source is used to retain the RTC and RAM data in the absence of VCC power through the VOUT pin. The chip enable output to RAM (ECON) and the output enable output to RAM (GCON) are controlled during power transients to prevent data corruption. The date is automatically adjusted for months with less than 31 days and corrects for leap years (valid until 2100). The internal watchdog timer provides programmable alarm windows. The nine clock bytes (7FFFFh-7FFF9h and 7FFF1h) are not the actual clock counters, they are memory locations consisting of BiPORTTM READ/WRITE memory cells within the static RAM array. Clock circuitry updates the clock bytes with current information once per second. The information can be accessed by the user in the same manner as any other location in the static memory array. Byte 7FFF8h is the clock control register. This byte controls user access to the clock information and also stores the clock calibration setting. Byte 7FFF7h contains the watchdog timer setting. The watchdog timer can generate either a reset or an interrupt, depending on the state of the Watchdog Steering Bit (WDS). Bytes 7FFF6h-7FFF2h include bits that, when programmed, provide for clock alarm functionality. Alarms are activated when the register content matches the month, date, hours, minutes, and seconds of the clock registers. Byte 7FFF1h contains century information. Byte 7FFF0h contains additional flag information pertaining to the watchdog timer, the alarm condition, the battery status and square wave output operation. 4 bits are included within this register (RS0-RS3) that are used to program the Square Wave Output Frequency (see Table 7 on page 20). The M48T201Y/V also has its own Power-Fail Detect circuit. This control circuitry constantly monitors the supply voltage for an out of tolerance condition. When VCC is out of tolerance, the circuit write protects the TIMEKEEPER register data and external SRAM, providing data security in the midst of unpredictable system operation. As VCC falls below the Battery Back-up Switchover Voltage (VSO), the control circuitry automatically switches to the battery, maintaining data and clock operation until valid power is restored.
2.1
Address decoding
The M48T201Y/V accommodates 19 address lines (A0-A18) which allow direct connection of up to 512 K bytes of static RAM. Regardless of SRAM density used, timekeeping, watchdog, alarm, century, flag, and control registers are located in the upper RAM locations. All TIMEKEEPER registers reside in the upper RAM locations without conflict by inhibiting the GCON (output enable RAM) signal during clock access. The RAM's physical locations are transparent to the user and the memory map looks continuous from the first clock address to the upper most attached RAM addresses.
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Operation Table 2.
Mode Deselect WRITE READ READ Deselect Deselect VSO to VPFD (min) VSO(1)
(1)
M48T201Y, M48T201V Operating modes
VCC E VIH 4.5 V to 5.5 V or 3.0 V to 3.6 V VIL VIL VIL X X G X X VIL VIH X X W X VIL VIH VIH X X DQ7DQ0 High-Z DIN DOUT High-Z High-Z High-Z Power Standby Active Active Active CMOS standby Battery back-up
1. See Table 14 on page 29 for details.
Note:
X = VIH or VIL; VSO = battery back-up switchover voltage
2.2
Read mode
The M48T201Y/V executes a READ cycle whenever W (WRITE enable) is high and E (chip enable) is low. The unique address specified by the address inputs (A0-A18) defines which one of the on-chip TIMEKEEPER registers or external SRAM locations is to be accessed. When the address presented to the M48T201Y/V is in the range of 7FFFFh-7FFF0h, one of the on-board TIMEKEEPER registers is accessed and valid data will be available to the eight data output drivers within tAVQV after the address input signal is stable, providing that the E and G access times are also satisfied. If they are not, then data access must be measured from the latter occurring signal (E or G) and the limiting parameter is either tELQV for E or tGLQV for G rather than the address access time. When one of the on-chip TIMEKEEPER registers is selected for READ, the GCON signal will remain inactive throughout the READ cycle. When the address value presented to the M48T201Y/V is outside the range of TIMEKEEPER registers, an external SRAM location will be selected. In this case the G signal will be passed to the GCON pin, with the specified delay times of tAOEL or tOERL.
Figure 4.
GCON timing when switching between RTC and external SRAM
ADDRESS
7FFF0h - 7FFFFh
0 0 0h - 7FFEFh
7FFF0h - 7FFFFh
0 0 0h - 7FFEFh
RTC
External SRAM
RTC
External SRAM
G
GCON tAOEL E tAOEH tOERL tRO
AI02333
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M48T201Y, M48T201V Figure 5. Read cycle timing: RTC and external RAM control signals
Operation
READ tAVAV ADDRESS tELQV E tELQX G tGLQV
READ tAVAV
WRITE tAVAV
tAVQV
tAVWL
tWHAX
tRO GCON
ECON tEPD W tWLWH
tGLQX
tAXQX tGHQZ
DQ0-DQ7
DATA OUT VALID
DATA OUT VALID
DATA IN VALID
AI02334
11/35
Operation Table 3. Read mode AC characteristics
M48T201Y Symbol Parameter(1) Min tAVAV tAVQV tELQV tGLQV tELQX
(2)
M48T201Y, M48T201V
M48T201V 85 Unit M ax ns 85 85 35 5 0 ns ns ns ns ns 25 25 5 ns ns ns 30 30 15 20 15 ns ns ns ns ns
70 M ax Min 85 70 70 25 5 0 20 20 5 20 20 10 15 10
READ cycle time Address valid to output valid Chip enable low to output valid Output enable low to output valid Chip enable low to output transition Output enable low to output transition Chip enable high to output Hi-Z Output enable high to output Hi-Z Address transition to output transition External SRAM address to GCON low SUPERVISOR SRAM address to GCON high E to ECON low or high G low to GCON low G high to GCON high
70
tGLQX(2) tEHQZ(2) tGHQZ(2) tAXQX tAOEL tAOEH tEPD tOERL tRO
1. Valid for ambient operating temperature: TA = 0 to 70C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where noted). 2. CL = 5 pF.
2.3
Write mode
The M48T201Y/V is in the WRITE mode whenever W (WRITE enable) and E (chip enable) are low state after the address inputs are stable. The start of a WRITE is referenced from the latter occurring falling edge of W or E. A WRITE is terminated by the earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W must return high for a minimum of tEHAX from Chip Enable or tWHAX from WRITE enable prior to the initiation of another READ or WRITE Cycle. Data-in must be valid tDVWH prior to the end of WRITE and remain valid for tWHDX afterward. G should be kept high during WRITE cycles to avoid bus contention; although, if the output bus has been activated by a low on E and G a low on W will disable the outputs tWLQZ after W falls. When the address value presented to the M48T201Y/V during the WRITE is in the range of 7FFFFh-7FFF0h, one of the on-board TIMEKEEPER registers will be selected and data will be written into the device. When the address value presented to M48T201Y/V is outside the range of TIMEKEEPER registers, an external SRAM location is selected.
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M48T201Y, M48T201V Figure 6. Write cycle timing: RTC and external RAM control signals
WRITE tAVAV ADDRESS tAVEH tAVEL E tEPD ECON tEPD G tRO GCON tAVWL W tEHQZ DQ0-DQ7
DATA OUT VALID
Operation
WRITE tAVAV
READ tAVAV
tAVWH tEHAX tWHAX tAVQV
tELEH
tGLQV
tEHDX
tWLWH
tWHQX
tWLQZ
tDVEH
DATA IN VALID
tDVWH
DATA IN VALID
tWHDX
DATA OUT VALID AI02336
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Operation Table 4. Write mode AC characteristics
M48T201Y Symbol Parameter(1) Min tAVAV tAVWL tAVEL tWLWH t ELEH tWHAX tEHAX tDVWH tDVEH tWHDX tEHDX tWLQZ(2)(3) tAVWH tAVEH WRITE cycle time Address valid to WRITE enable low Address valid to chip enable low WRITE enable pulse width Chip enable low to chip enable high WRITE enable high to address transition Chip enable high to address transition Input valid to WRITE enable high Input valid to chip enable high WRITE enable high to input transition Chip enable high to input transition WRITE enable low to output High-Z Address valid to WRITE enable high Address valid to chip enable high 55 55 5 70 0 0 45 50 0 0 25 25 0 0 20 70 Max
M48T201Y, M48T201V
M48T201V 85 Min 85 0 0 55 60 0 0 30 30 0 0 25 65 65 5 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
tWHQX(2)(3) WRITE enable high to output transition
1. Valid for ambient operating temperature: TA = 0 to 70C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where noted). 2. CL = 5 pF 3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
2.4
Data retention mode
With valid VCC applied, the M48T201Y/V can be accessed as described above with READ or WRITE cycles. Should the supply voltage decay, the M48T201Y/V will automatically deselect, write protecting itself (and any external SRAM) when VCC falls between VPFD (max) and VPFD (min). This is accomplished by internally inhibiting access to the clock registers via the E signal. At this time, the Reset pin (RST) is driven active and will remain active until VCC returns to nominal levels. External RAM access is inhibited in a similar manner by forcing ECON to a high level. This level is within 0.2 V of the VBAT. ECON will remain at this level as long as VCC remains at an out-of-tolerance condition. When VCC falls below the level of the battery (VBAT), power input is switched from the VCC pin to the SNAPHAT battery and the clock registers are maintained from the attached battery supply. External RAM is also powered by the SNAPHAT battery. All outputs except GCON, ECON, RST, IRQ/FT and VOUT, become high impedance. The VOUT pin is capable of supplying 100A of current to the attached memory with less than 0.3 V drop under this condition. On power up, when VCC returns to a nominal value, write protection continues for 200 ms (max) by inhibiting ECON. The RST signal also remains active during this time (see Figure 14 on page 29).
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M48T201Y, M48T201V Note:
Operation
Most low power SRAMs on the market today can be used with the M48T201Y/V TIMEKEEPER SUPERVISOR. There are, however some criteria which should be used in making the final choice of an SRAM to use. The SRAM must be designed in a way where the chip enable input disables all other inputs to the SRAM. This allows inputs to the M48T201Y/V and SRAMs to be "Don't care" once VCC falls below VPFD (min). The SRAM should also guarantee data retention down to VCC = 2.0 V. The chip enable access time must be sufficient to meet the system needs with the chip enable (and output enable) output propagation delays included.
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Clock operation
M48T201Y, M48T201V
3
3.1
Clock operation
TIMEKEEPER registers
The M48T201Y/V offers 16 internal registers which contain TIMEKEEPER, alarm, watchdog, flag, and control data (see Table 5 on page 17). These registers are memory locations which contain external (user accessible) and internal copies of the data (usually referred to as BiPORTTM TIMEKEEPER cells). The external copies are independent of internal functions except that they are updated periodically by the simultaneous transfer of the incremented internal copy. TIMEKEEPER and alarm registers store data in BCD. control, watchdog and flags (bits D0 to D3) registers store data in binary format.
3.2
Reading the clock
Updates to the TIMEKEEPER registers should be halted before clock data is read to prevent reading data in transition. The BiPORT TIMEKEEPER cells in the RAM array are only data registers and not the actual clock counters, so updating the registers can be halted without disturbing the clock itself. Updating is halted when a '1' is written to the READ bit, D6 in the control register (7FFF8h). As long as a '1' remains in that position, updating is halted. After a halt is issued, the registers reflect the count; that is, the day, date, and time that were current at the moment the halt command was issued. All of the TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an update in progress. Updating occurs approximately 1 second after the READ bit is reset to a '0.'
3.3
Setting the clock
Bit D7 of the control register (7FFF8h) is the WRITE bit. Setting the WRITE bit to a '1,' like the READ bit, halts updates to the TIMEKEEPER registers. The user can then load them with the correct day, date, and time data in 24-hour BCD format (see Table 5 on page 17). Resetting the WRITE bit to a '0' then transfers the values of all time registers (7FFFFh7FFF9h, 7FFF1h) to the actual TIMEKEEPER counters and allows normal operation to resume. After the WRITE bit is reset, the next clock update will occur approximately one second later.
Note:
Upon power-up following a power failure, both the WRITE bit and the READ bit will be reset to '0.'
3.4
Stopping and starting the oscillator
The oscillator may be stopped at any time. If the device is going to spend a significant amount of time on the shelf, the oscillator can be turned off to minimize current drain on the battery. The STOP bit is located at Bit D7 within the seconds register (7FFF9h). Setting it to a '1' stops the oscillator. When reset to a '0,' the M48T201Y/V oscillator starts within one second.
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M48T201Y, M48T201V No te :
Clock operation
It is not necessary to set the WRITE bit when setting or resetting the FREQUENCY TEST bit (FT) or the STOP bit (ST). TIMEKEEPER register map
Data Function/range D3 D2 Year 10 M 10 date 0 0 0 Month Date: Day of Month Day Hours (24-hour format) Minutes Seconds Calibration BMB2 Al.10M BMB1 BMB0 RB1 RB0 D1 D0 BCD format Year Month Date Day Hours Minutes Seconds Control Watchdog Al. month Al. date Al. hours Al. minutes Al. seconds Century RS0 Flags 01-12 01-31 00-23 00-59 00-59 00-99 00-99 01-12 01-31 01-07 00-23 00-59 00-59
Table 5.
Address
D7 7FFFFh 7FFFEh 7FFFDh 7FFFCh 7FFFBh 7FFFAh 7FFF9h 7FFF8h 7FFF7h 7FFF6h 7FFF5h 7FFF4h 7FFF3h 7FFF2h 7FFF1h 7FFF0h WDF 0 0 0 0 0 ST W WDS AFE RPT4 RPT3 RPT2 RPT1
D6
D5
D4
10 years 0 0 FT 0 0
10 hours 10 minutes 10 seconds
R BMB4 SQWE RPT5 0
S BMB3 ABE
Alarm month Alarm date Alarm hours Alarm minutes Alarm seconds 100 years
Al. 10 date Al. 10 hours
Alarm 10 minutes Alarm 10 seconds 1000 years AF 0 BL RS3
RS2
RS1
Keys: S = Sign bit FT = Frequency test bit R = READ bit W = WRITE bit ST = Stop bit 0 = Must be set to '0' WDS = Watchdog steering bit AF = Alarm flag BL = Battery low flag SQWE = Square wave enable bit BMB0-BMB4 = Watchdog multiplier bits RB0-RB1 = Watchdog resolution bits AFE = Alarm flag enable flag ABE = Alarm in battery back-up mode enable bit RPT1-RPT5 = Alarm repeat mode bits WDF = Watchdog flag RS0-RS3 = SQW frequency
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Clock operation
M48T201Y, M48T201V
3.5
Setting the alarm clock
Registers 7FFF6h-7FFF2h contain the alarm settings. The alarm can be configured to go off at a prescribed time on a specific month, day of month, hour, minute, or second or repeat every month, day of month, hour, minute, or second. It can also be programmed to go off while the M48T201Y/V is in the battery back-up to serve as a system wake-up call. Bits RPT5-RPT1 put the alarm in the repeat mode of operation. Table 6 shows the possible configurations. Codes not listed in the table default to the once per second mode to quickly alert the user of an incorrect alarm setting.
Note:
User must transition address (or toggle chip enable) to see flag bit change. When the clock information matches the alarm clock settings based on the match criteria defined by RPT5-RPT1, the AF (alarm flag) is set. If AFE (alarm flag enable) is also set, the alarm condition activates the IRQ/FT pin. To disable alarm, write '0' to the alarm-date register and RPT1-5. The IRQ/FT output is cleared by a READ to the flags register as shown in Figure 7. A subsequent READ of the flags register is necessary to see that the value of the alarm flag has been reset to '0.' The IRQ/FT pin can also be activated in the battery back-up mode. The IRQ/FT will go low if an alarm occurs and both ABE (alarm in battery back-up mode enable) and AFE are set. The ABE and AFE bits are reset during power-up, therefore an alarm generated during power-up will only set AF. The user can read the flag register at system boot-up to determine if an alarm was generated while the M48T201Y/V was in the deselect mode during power-up. Figure 8 on page 19 illustrates the back-up mode alarm timing. Figure 7. Alarm interrupt reset waveforms
ADDRESS 7FFF0h 15ns Min
A0-A18
ACTIVE FLAG BIT
IRQ/FT HIGH-Z
AI02331
Table 6.
RPT5 1 1 1 1 1 0
Alarm repeat modes
RPT4 1 1 1 1 0 0 RPT3 1 1 1 0 0 0 RPT2 1 1 0 0 0 0 RPT1 1 0 0 0 0 0 Alarm setting Once per second Once per minute Once per hour Once per day Once per month Once per year
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M48T201Y, M48T201V Figure 8. Back-up mode alarm waveforms
Clock operation
tREC VCC VPFD (max) VPFD (min) VSO
AFE bit/ABE bit
AF bit in Flags Register
IRQ/FT HIGH-Z
AI03520
HIGH-Z
3.6
Watchdog timer
The watchdog timer can be used to detect an out-of-control microprocessor. The user programs the watchdog timer by setting the desired amount of time-out into the Watchdog Register, address 7FFF7h. Bits BMB4-BMB0 store a binary multiplier and the two lower order bits RB1-RB0 select the resolution, where 00 = 1/16 second, 01 = 1/4 second, 10 = 1 second, and 11 = 4 seconds. The amount of time-out is then determined to be the multiplication of the five-bit multiplier value with the resolution. (For example: writing 00001110 in the watchdog register = 3*1 or 3 seconds).
Note:
Accuracy of timer is within the selected resolution. If the processor does not reset the timer within the specified period, the M48T201Y/V sets the WDF (watchdog flag) and generates a watchdog interrupt or a microprocessor reset. WDF is reset by reading the flag register (address 7FFF0h). The most significant bit of the watchdog register is the watchdog steering bit (WDS). When set to a '0', the watchdog will activate the IRQ/FT pin when timed-out. When WDS is set to a '1,' the watchdog will output a negative pulse on the RST pin for tREC. The watchdog register and the AFE, SQWE, ABE, and FT bits will reset to a '0' at the end of a watchdog time-out when the WDS Bit is set to a '1.' The watchdog timer can be reset by two methods: 1. 2. a transition (high-to-low or low-to-high) can be applied to the watchdog input pin (WDI) or the microprocessor can perform a WRITE of the watchdog register.
The time-out period then starts over. The WDI pin should be tied to VSS if not used. The watchdog will be reset on each transition (edge) seen by the WDI pin.
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Clock operation
M48T201Y, M48T201V
In order to perform a software reset of the watchdog timer, the original time-out period can be written into the watchdog register, effectively restarting the count-down cycle. Should the watchdog timer time-out, and the WDS bit is programmed to output an interrupt, a value of 00h needs to be written to the watchdog register in order to clear the IRQ/FT pin. This will also disable the watchdog function until it is again programmed correctly. A READ of the flags register will reset the watchdog flag (bit D7; register 7FFF0h). The watchdog function is automatically disabled upon power-down and the watchdog register is cleared. If the watchdog function is set to output to the IRQ/FT pin and the frequency test function is activated, the watchdog or alarm function prevails and the frequency test function is denied. Note: The user must transition the address (or toggle chip enable) to see the flag bit change.
3.7
Square wave output
The M48T201Y/V offers the user a programmable square wave function which is output on the SQW pin. RS3-RS0 bits located in 7FFF0h establish the square wave output frequency. These frequencies are listed in Table 7. Once the selection of the SQW frequency has been completed, the SQW pin can be turned on and off under software control with the square wave enable bit (SQWE) located in register 7FFF6h. Table 7. Square wave output frequency
Square wave bits RS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 RS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 RS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 RS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Square wave Frequency Hi-Z 32.768 8.192 4.096 2.048 1.024 512 256 128 64 32 16 8 4 2 1 Units kHz kHz kHz kHz kHz Hz Hz Hz Hz Hz Hz Hz Hz Hz Hz
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M48T201Y, M48T201V
Clock operation
3.8
Power-on reset
The M48T201Y/V continuously monitors VCC. When VCC falls to the power fail detect trip point, the RST pulls low (open drain) and remains low on power-up for tREC after VCC passes VPFD (max). The RST pin is an open drain output and an appropriate pull-up resistor to VCC should be chosen to control rise time.
3.9
Reset inputs (RSTIN1 & RSTIN2)
The M48T201Y/V provides two independent inputs which can generate an output reset. The duration and function of these resets is identical to a reset generated by a power cycle. Figure 9 and Table 8 illustrate the AC reset characteristics of this function. Pulses shorter than tR1 and tR2 will not generate a reset condition. RSTIN1 and RSTIN2 are each internally pulled up to VCC through a 100 K resistor. Figure 9. RSTIN1 and RSTIN2 timing waveforms
RSTIN1
RSTIN2 tR2 Hi-Z RST tR1 tR1HRZ tR2HRZ
AI01679
Hi-Z
Table 8.
Symbol tR1 tR2 tR1HRZ(2) tR2HRZ(2)
Reset AC characteristics
Parameter(1) RSTIN1 low to RST low RSTIN2 low to RST low RSTIN1 high to RST Hi-Z RSTIN2 high to RST Hi-Z Min 50 20 40 40 M ax 200 100 200 200 Unit ns ms ms ms
1. Valid for ambient operating temperature: TA = 0 to 70C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where noted). 2. CL = 5 pF (see Figure 13 on page 27).
3.10
Calibrating the clock
The M48T201Y/V is driven by a quartz controlled oscillator with a nominal frequency of 32,768 Hz. The devices are factory calibrated at 25C and tested for accuracy. Clock accuracy will not exceed 35 ppm (parts per million) oscillator frequency error at 25C, which equates to about 1.53 minutes per month. When the calibration circuit is properly employed, accuracy improves to better than +1/2 ppm at 25C.
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Clock operation
M48T201Y, M48T201V
The oscillation rate of crystals changes with temperature (see Figure 10 on page 23). The M48T201Y/V design employs periodic counter correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage, as shown in Figure 11 on page 23. The number of times pulses which are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five calibration bits found in the control register. Adding counts speeds the clock up, subtracting counts slows the clock down. The calibration bits occupy the five lower order bits (D4-D0) in the control register 7FFF8h. These bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is a sign bit; '1' indicates positive calibration, '0' indicates negative calibration (see Figure 11 on page 23). Calibration occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or 2.034 ppm of adjustment per calibration step in the calibration register. Assuming that the oscillator is running at exactly 32,768 Hz, each of the 31 increments in the calibration byte would represent +10.7 or 5.35 seconds per month which corresponds to a total range of +5.5 or 2.75 minutes per month. Two methods are available for ascertaining how much calibration a given M48T201Y/V may require. The first involves setting the clock, letting it run for a month and comparing it to a known accurate reference and recording deviation over a fixed period of time. Calibration values, including the number of seconds lost or gained in a given period, can be found in the STMicroelectronics Application Note AN934, "TIMEKEEPER CALIBRATION." This allows the designer to give the end user the ability to calibrate the clock as the environment requires, even if the final product is packaged in a non-user serviceable enclosure. The designer could provide a simple utility that accesses the calibration byte. The second approach is better suited to a manufacturing environment, and involves the use of the IRQ/FT pin. The pin will toggle at 512 Hz, when the stop bit (ST, D7 of 7FFF9h) is '0,' the frequency test bit (FT, D6 of 7FFFCh) is '1,' the alarm flag enable bit (AFE, D7 of 7FFF6h) is '0,' and the watchdog steering bit (WDS, D7 of 7FFF7h) is '1' or the watchdog register (7FFF7h=0) is reset. Note: A 4-second settling time must be allowed before reading the 512 Hz output. Any deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at the test temperature. For example, a reading of 512.010124 Hz would indicate a +20 ppm oscillator frequency error, requiring a 10 (WR001010) to be loaded into the calibration byte for correction. Note that setting or changing the calibration byte does not affect the frequency test output frequency. The IRQ/FT pin is an open drain output which requires a pull-up resistor to VCC for proper operation. A 500-10 k resistor is recommended in order to control the rise time. The FT bit is cleared on power-down.
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M48T201Y, M48T201V Figure 10. Crystal accuracy across temperature
Clock operation
Frequency (ppm) 20 0 20 40 60 80 100 120 140 160 40 30 20 10 0 10 20 30 40 50 60 70 80 F = -0.038 ppm (T - T )2 10% 0 F C2 T0 = 25 C
Temperature C
AI00999
Figure 11. Calibration waveform
NORMAL
POSITIVE CALIBRATION
NEGATIVE CALIBRATION
AI00594B
3.11
Battery low warning
The M48T201Y/V automatically performs battery voltage monitoring upon power-up and at factory-programmed time intervals of approximately 24 hours. The battery low (BL) bit, bit D4 of flags register 7FFF0h, will be asserted if the battery voltage is found to be less than approximately 2.5 V. The BL bit will remain asserted until completion of battery replacement and subsequent battery low monitoring tests, either during the next power-up sequence or the next scheduled 24-hour interval. If a battery low is generated during a power-up sequence, this indicates that the battery is below approximately 2.5 V and may not be able to maintain data integrity in the SRAM. Data should be considered suspect and verified as correct. A fresh battery should be installed.
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Clock operation
M48T201Y, M48T201V
If a battery low indication is generated during the 24-hour interval check, this indicates that the battery is near end of life. However, data is not compromised due to the fact that a nominal VCC is supplied. In order to insure data integrity during subsequent periods of battery back-up mode, the battery should be replaced. The SNAPHAT top may be replaced while VCC is applied to the device. Note: This will cause the clock to lose time during the interval the battery/crystal is removed. The M48T201Y/V only monitors the battery when a nominal VCC is applied to the device. Thus applications which require extensive durations in the battery back-up mode should be powered-up periodically (at least once every few months) in order for this technique to be beneficial. Additionally, if a battery low is indicated, data integrity should be verified upon power-up via a checksum or other technique.
3.12
Initial power-on defaults
Upon application of power to the device, the following register bits are set to a '0' state: WDS; BMB0-BMB4; RB0-RB1; AFE; ABE; SQWE; W; R; FT (see Table 9). Table 9. Default values
Condition Initial power-up (Batter y attach for SNAPHAT)(2) RESET(3) Power-down
(4)
W
R
FT
AFE
ABE
SQWE
Watchdog register(1) 0 0 0
0 0 0
0 0 0
0 0 0
0 0 1
0 0 1
0 0 1
1. WDS, BMB0-BMB4, RB0, RB1. 2. State of other control bits undefined. 3. State of other control bits remains unchanged. 4. Assuming these bits set to '1' prior to power-down.
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M48T201Y, M48T201V
Clock operation
3.13
VCC noise and negative going transients
ICC transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if capacitors are used to store energy which stabilizes the VCC bus. The energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1 F (as shown in Figure 12) is recommended in order to provide the needed filtering. In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on VCC that drive it to values below VSS by as much as one volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, STMicroelectronics recommends connecting a schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is recommended for surface mount. Figure 12. Supply voltage protection
VCC VCC
0.1F
DEVICE
VSS
AI00605
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Maximum ratings
M48T201Y, M48T201V
4
Maximum ratings
Stressing the device above the rating listed in the "Absolute maximum ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 10.
Symbol TA TSTG TSLD(1)(2) VIO VCC IO(2) PD
Absolute maximum ratings
Parameter Ambient operating temperature Storage temperature SNAPHAT SOIC Value 0 to 70 40 to 85 55 to 125 260 0.3 to VCC + 0.3 M48T201Y M48T201V 0.3 to 7.0 0.3 to 4.6 20 1 Unit C C C C V V V mA W
Lead solder temperature for 10 seconds Input or output voltage Supply voltage Output current Power dissipation
1. For SO package, standard (SnPb) lead finish: Reflow at peak temperature of 225C (total thermal budget not to exceed 180C for between 90 to 150 seconds). 2. For SO package, Lead-free (Pb-free) lead finish: Reflow at peak temperature of 260C (total thermal budget not to exceed 245C for greater than 30 seconds).
Caution: Caution:
Negative undershoots below 0.3 V are not allowed on any pin while in the Battery Back-up mode. Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
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M48T201Y, M48T201V
DC and AC parameters
5
DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the measurement conditions listed in Table 11: DC and AC measurement conditions. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 11. DC and AC measurement conditions
Parameter VCC supply voltage Ambient operating temperature Load capacitance (CL) Input rise and fall times Input pulse voltages Input and output timing ref. voltages M48T201Y 4.5 to 5.5 0 to 70 100 5 0 to 3 1.5 M48T201V 3.0 to 3.6 0 to 70 50 5 0 to 3 1.5 Unit V C pF ns V V
Note:
Output High Z is defined as the point where data is no longer driven. Figure 13. AC testing load circuit
DEVICE UNDER TEST
645
CL = 100pF
1.75V
CL includes JIG capacitance
AI04764
Note:
Excluding open-drain output pin; 50pF for M48T201V. Table 12.
Symbol CIN COUT
(3)
Capacitance
Parameter(1)(2) Input capacitance Input/output capacitance Min Max 10 10 Unit pF pF
1. Effective capacitance measured with power supply at 5 V; sampled only, not 100% tested. 2. At 25C; f = 1 MHz. 3. Outputs deselected.
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DC and AC parameters Table 13. DC characteristics
M48T201Y Sym Parameter Test condition(1) Min ILI(2) ILO(3) ICC ICC1 ICC2 Input leakage current Output leakage current Supply current Supply current (standby) TTL Supply current (standby) CMOS Battery current OSC ON Battery current OSC OFF Input low voltage Input high voltage Output low voltage VOL VOH VOHB(5) IOUT1(6) IOUT2 VPFD VSO VBAT Output low voltage (open drain)(4) Output high voltage VOH battery back-up VOUT current (active) IOL = 2.1 mA IOL = 10 mA IOH = 1.0 mA IOUT2 = 1.0 A VOUT1 > VCC 0.3 2.4 2.0 3.6 100 100 4.1 4.35 3.0 3.0 4.5 2.7 0V VIN VCC 0V VOUT VCC Outputs open E = VIH E = VCC 0.2 575 VCC = 0 V 100 0.3 2.2 0.8 VCC + 0.3 0.4 0.4 2.4 2.0 0.3 2.0 8 70 Typ Max 1 1 15 5 3 800 Min
M48T201Y, M48T201V
M48T201V 85 Typ Max 1 1 4 10 3 2 575 800 100 0.8 VCC + 0.3 0.4 0.4 A A mA mA mA nA nA V V V V V 3.6 70 100 2.9 VPFD 100 mV 3.0 3.0 V mA A V V V Unit
IBAT
VIL VIH
VOUT current (battery VOUT2 > VBAT 0.3 back-up) Power-fail deselect voltage Battery back-up switchover voltage Battery voltage
1. Valid for ambient operating temperature: TA = 0 to 70C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where noted). 2. RSTIN1 and RSTIN2 internally pulled-up to VCC through 100 K resistor. WDI internally pulled-down to VSS through 100 K resistor. 3. Outputs deselected. 4. For IRQ/FT & RST pins (open drain). 5. Conditioned outputs (ECON - GCON) can only sustain CMOS leakage currents in the battery back-up mode. Higher leakage currents will reduce battery life. 6. External SRAM must match TIMEKEEPER supervisor chip VCC specification.
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M48T201Y, M48T201V Figure 14. Power down/up mode AC waveforms
VCC VPFD (max) VPFD (min) VSO tF tFB tRB
DC and AC parameters
tR tREC
INPUTS
VALID
DON'T CARE
VALID
HIGH-Z OUTPUTS VALID VALID
RST
AI03519
Table 14.
Symbol tF(2) tFB(3) tR tREC tRB
Power down/up mode AC characteristic
Parameter(1) VPFD (max) to VPFD (min) VCC fall time VPFD (min) to VSS VCC fall time VPFD (min) to VPFD (max) VCC rise time VPFD (max) to RST high VSS to VPFD (min) VCC rise time M48T201Y M48T201V Min 300 10 150 10 40 5 200 M ax Unit s s s s ms s
1. Valid for ambient operating temperature: TA = 0 to 70C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where noted). 2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200 s after VCC passes VPFD (min). 3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
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Package mechanical data
M48T201Y, M48T201V
6
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 15. SOH44 44-lead plastic small outline, SNAPHAT, package outline
A2 B e
A C eB CP
D
N
E
H A1 L
1 SOH-A
Note:
Drawing is not to scale. Table 15.
Symb Typ A A1 A2 B C D E e eB H L a 0.81 0.05 2.34 0.36 0.15 17.71 8.23 3.20 11.51 0.41 0 Min Max 3.05 0.36 2.69 0.46 0.32 18.49 8.89 3.61 12.70 1.27 8 0.032 0.002 0.092 0.014 0.006 0.697 0.324 0.126 0.453 0.016 0 Typ Min Max 0.120 0.014 0.106 0.018 0.012 0.728 0.350 0.142 0.500 0.050 8
SOH44 44-lead plastic small outline, SNAPHAT, pack. mech.
mm inches
30/35
M48T201Y, M48T201V Table 15.
Symb Typ N CP Min 44 0.10 Max Typ
Package mechanical data SOH44 44-lead plastic small outline, SNAPHAT, pack. mech. (continued)
mm inches Min 44 0.004 Max
Figure 16. SH 4-pin SNAPHAT housing for 48 mAh battery & crystal, package outline
A1
A2 A A3
eA D
B eB
L
E
SHTK-A
Note:
Drawing is not to scale. Table 16. SH 4-pin SNAPHAT housing for 48 mAh battery & crystal, pack. mech. data
mm Symb Typ A A1 A2 A3 B D E eA eB L 0.46 21.21 14.22 15.55 3.20 2.03 6.73 6.48 Min Max 9.78 7.24 6.99 0.38 0.56 21.84 14.99 15.95 3.61 2.29 0.018 0.835 0.560 0.612 0.126 0.080 0.265 0.255 Typ Min Max 0.385 0.285 0.275 0.015 0.022 0.860 0.590 0.628 0.142 0.090 inches
31/35
Package mechanical data
M48T201Y, M48T201V
Figure 17. SH 4-pin SNAPHAT housing for 120 mAh battery & crystal, pack. outline
A1
A2 A A3
eA D
B eB
L
E
SHTK-A
Note:
Drawing is not to scale. Table 17. SH 4-pin SNAPHAT housing for 120 mAh battery & crystal, pack. mech. data
mm Symb Typ A A1 A2 A3 B D E eA eB L 0.46 21.21 17.27 15.55 3.20 2.03 8.00 7.24 Min Max 10.54 8.51 8.00 0.38 0.56 21.84 18.03 15.95 3.61 2.29 0.018 0.835 0.680 0.612 0.126 0.080 0.315 0.285 Typ Min Max 0.415 .0335 0.315 0.015 0.022 0.860 .0710 0.628 0.142 0.090 inches
32/35
M48T201Y, M48T201V
Part numbering
7
Part numbering
Table 18.
Example:
Ordering information scheme
M48T 201Y 70 MH 1 F
Device type M48T
Supply and write protect voltage 201Y = VCC = 4.5 to 5.5 V; VPFD = 4.1 V to 4.5 V 201V = VCC = 3.0 to 3.6 V; VPFD = 2.7 V to 3.0 V
Speed 70 = 70 ns (for M48T201Y) 85 = 85 ns (for M48T201V)
Package MH(1) = SOH44
Temperature range 1 = 0 to 70C
Shipping method for SOIC blank = tubes (not for new design - use E) E = ECOPACK package, tubes F = ECOPACK package, tape and reel TR = tape and reel (not for new design - use F)
1. The SOIC package (SOH44) requires the battery package (SNAPHAT) which is ordered separately under the part number "M4Txx-BR12SH" in plastic tube or "M4Txx-BR12SHTR" in tape & reel form.
Caution:
Do not place the SNAPHAT battery package "M4Txx-BR12SH" in conductive foam as it will drain the lithium button-cell battery. For a list of available options (e.g., speed, package) or for further information on any aspect of this device, please contact the ST sales office nearest to you. Table 19. SNAPHAT battery table
Description Lithium Battery (48mAh) SNAPHAT Lithium Battery (120mAh) SNAPHAT Package SH SH
Part Number M4T28-BR12SH M4T32-BR12SH
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Revision history
M48T201Y, M48T201V
8
Revision history
Table 20.
Date Nov-1999 10-May-2001 14-May-2001 30-May-2001 01-Aug-2001 08-Aug-2001 18-Dec-2001 13-May-2002 16-Jul-2002 27-Mar-2003 24-Sep-2004
Document revision history
Revision 1.0 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 3.0 4.0 First Issue Reformatted; added Industrial temperature (Table 10, 13, 3, 4, 14) Corrected table footnote (Table 14) Change "controller" references to "supervisor" Formatting changes from recent document review findings; E2 added to Hookup (Figure 3) Improve text in "Setting the Alarm Clock" section Added IBAT values for Industrial Temperature device (Table 13) Modify reflow time and temperature footnote (Table 10) Update DC Characteristics, footnotes (Table 13) v2.2 template applied; update test condition (Table 13) Reformatted, remove Industrial Temperature (Ambient Operating) references (Table 3, 4, 8, 10, 13, 14, 18) Reformatted; added lead-free second level interconnect information to cover page and Section 6: Package mechanical data; updated Table 10. Updated shipping method in Table 18. Changes
12-Sep-2007 22-Apr-2008
5.0 6.0
M48T201, M48T201Y, M48T201V, 48T201, 48T201Y, 48T201V, T201, T201Y, T201V, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Switchover, Switchover, Switchover, Switchover, Switchover, Switchover, Switchover, Switchover, Switchover, Switchover, Powerfail, Power-fail, Power-fail, Power-fail, Power-fail, Power-fail, Power-fail, Power-fail, Power-fail, Power-fail, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 3.3V, 3.3V, 3.3V, 3.3V, 3.3V, 3.3V, 3.3V, 3.3V, 3.3V, 3.3V
34/35
M48T201Y, M48T201V
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