STS12NF30L
N-channel 30V - 0.008 - 12A SO-8 STripFETTM II Power MOSFET
Features
Type STS12NF30L
VDSS 30V
RDS(on) <0.009
ID 12A
Standard outline for easy automated surface mount assembly Low threshold drive
S0-8
Description
This Power MOSFET is the latest development of STMicroelectronics unique "Single Feature SizeTM" strip-based process. The resulting transistor shows extremely high packing density for low on-resistance, rugged avalanche characteristics and less critical alignment steps therefore a remarkable manufacturing reproducibility.
Internal schematic diagram
Application
Switching application
Order code
Part number STS12NF30L Marking S12NF30L Package SO-8 Packaging Tape & reel
May 2007
Rev 9
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Contents
STS12N F30L
Contents
1 2 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Electrical characteristics (curves) . . .. . .. . .. . .. . .... 6
3 4 5
Test circuit
. . .. . .. . .. . .. . .. . .. . .. . .. . .... 8
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
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STS12NF30L
Electrical ratings
1
Electrical ratings
Table 1.
Sy mbol VDS VGS ID ID IDM
(1)
Absolute maximum ratings
Parameter Drain-source voltage (vgs = 0) Gate- source voltage Drain current (continuos) at TC = 25C Drain current (continuos) at TC = 100C Drain current (pulsed) Total dissipation at TC = 25C Value 30 16 12 7.5 48 2.5 Unit V V A A A W
PTOT
1. Pulse width limited by safe operating area
Table 2.
Rthj-a TJ Tstg
Thermal data
Thermal resistance junction-ambient Max Maximum operating junction temperature Storage temperature 50 150 -55 to 150 C/W C C
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Electrical characteristics
STS12NF30L
2
Electrical characteristics
(TCASE=25C unless otherwise specified) Table 3.
Symbol V(BR)DSS IDSS IGSS VGS(th) RDS(on)
On/off states
Parameter Drain-source Breakdown voltage Zero gate voltage Drain current (VGS = 0) Gate-body leakage current (VDS = 0) Gate threshold voltage Static drain-source on resistance Test conditions ID = 250 A, VGS = 0 VDS = Max rating VDS=Max rating,TC=125C VGS = 16V VDS = VGS, ID = 250A VGS = 10V, ID = 6A VGS = 4.5V, ID = 6A 1 0.008 0.01 0.009 0.011 Min. 30 1 10 100 Typ. Max. Unit V A A nA V
Table 4.
Symbol gfs (1) Ciss Coss Crss Qg Qgs Qgd
Dynamic
Parameter Forward transconductance Input capacitance Output capacitance Reverse transfer capacitance Total gate charge Gate-source charge Gate-drain charge VDS = 25V, f = 1 MHz, VGS = 0 Test conditions VDS = 15V, ID=6A Min. Typ. 15 2400 590 200 VDD = 24V, ID = 12A, VGS = 4.5V (see Figure 13) 35 9 18 50 Max. Unit S pF pF pF nC nC nC
1. Pulsed: Pulse duration = 300 s, duty cycle 1.5.
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STS12NF30L Table 5.
Symbol td(on) tr td(off) tf tr(Voff) tf tc
Electrical characteristics Switching times
Parameter Turn-on delay time Rise time Test conditions VDD=15 V, ID=6A, RG=4.7, VGS= 4.5V (see Figure 12) VDD = 15V, ID = 6A, RG = 4.7, VGS = 4.5V (see Figure 12) VDD=24V, ID=12A, RG=4.7, VGS=4.5V (see Figure 14) Min. Typ. 35 90 Max. Unit ns ns
Turn-off-delay time Fall time Off-voltage rise time fall time cross-over time
80 35 35 35 80
ns ns ns ns ns
Table 6.
Symbol ISD ISDM VSD
(1) (2)
Source drain diode
Parameter Source-drain current Source-drain current (pulsed) Forward on voltage Reverse recovery time Reverse recovery charge Reverse recovery current ISD = 12A, VGS = 0 ISD = 12A, VDD = 15V di/dt = 100A/s, Tj = 150C (see Figure 14) 114 456 8 Test conditions Min. Typ. Max 12 48 1.3 Unit A A V ns nC A
t rr Qrr IRRM
1. Pulse width limited by safe operating area. 2. Pulsed: Pulse duration = 300 s, duty cycle 1.5%
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Electrical characteristics
STS12NF30L
2.1
Figure 1.
Electrical characteristics (curves)
Safe operating area Figure 2. Thermal impedance
Figure 3.
Output characteristics
Figure 4.
Transfer characteristics
Figure 5.
Transconductance
Figure 6.
Static drain-source on resistance
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STS12NF30L Figure 7. Gate charge vs. gate-source voltage Figure 8.
Electrical characteristics Capacitance variations
Figure 9.
Normalized gate threshold voltage vs. temperature
Figure 10. Normalized on resistance vs. temperature
Figure 11. Source-drain diode forward characteristics
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Test circuit
STS12N F30L
3
Test circuit
Figure 13. Gate charge test circuit
Figure 12. Switching times test circuit for resistive load
Figure 14. Test circuit for inductive load Figure 15. Unclamped Inductive load test switching and diode recovery times circuit
Figure 16. Unclamped inductive waveform
Figure 17. Switching time waveform
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STS12NF30L
Package mechanical data
4
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a Lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com
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Package mechanical data
STS12NF30L
SO-8 MECHANICAL DATA
DIM. A a1 a2 a3 b b1 C c1 D E e e3 F L M S 3.8 0.4 4.8 5.8 1.27 3.81 4.0 1.27 0.6 8 (max.) 0.14 0.015 5.0 6.2 0.65 0.35 0.19 0.25 0.1 mm. MIN. TYP M AX. 1.75 0.25 1.65 0.85 0.48 0.25 0.5 45 (typ.) 0.188 0.228 0.050 0.150 0.157 0.050 0.023 0.196 0.244 0.025 0.013 0.007 0.010 0.003 MIN. inch TYP. M AX . 0.068 0.009 0.064 0.033 0.018 0.010 0.019
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STS12NF30L
Revision history
5
Revision history
Table 7.
Date 09-Sep-2004 17-Aug-2006 31-Jan-2007 08-May-2007
Revision history
Revision 6 7 8 9 Complete version New template, no content change Typo mistake on Table 1. Mistake on Table 6 Changes
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STS12NF30L
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