TDA7403
BASIC SIGNAL PROCESSOR
DEVICE INCLUDES AUDIO PROCESSOR, STEREO DECODER AND NOISEBLANKER HIGH PERFORMANCE SIGNAL PROCESSOR WITH BASIC FUNCTIONS AM, FM, (MPX) AND CASSETTE INPUTS NO EXTERNAL COMPONENTS REQUIRED FULLY PROGRAMMABLE VIA I2C BUS LOW DISTORTION AND NOISE
SO20
DESCRIPTION The TDA7403 is a high performance signal processor specifically designed for car radio applications focused on the low-end market. The device includes a complete audioprocessor and a stereo decoder with noiseblanker. Switched-capacitors design technique allows to obtain all these features without external components or adjustments. Using TDA7403 results is in a very performant low-cost signal processing BLOCK DIAGRAM
SM
ORDERING NUMBER: TDA7403D
application The device is fully programmable by I2C bus interface allowing to customize key device parameters and especially filter characteristics. The BICMOS process combined with the optimized signal processing assure low noise and low distortion performances.
11 8 SOFT MUTE
OUT LR TREBLE BASS OUT LF OUT RR OUT RF
17 19 16 18
OUT LR OUT LF OUT RR OUT RF
AM
VOLUME
CASS R CASS L
1 2 INPUT MULTIPLEXER + AUTO ZERO
12 DIGITAL CONTROL I2C BUS 13
SCL SDA
FM R FM L
MPX
9
80KHz LP
PILOT CANCELLATION
DEMODULATOR + STEREO ADJUST + STEREO BLEND
25KHz LP
S&H
HIGH CUT CONTROL
VS
15
SUPPLY
PLL
PIL DET
D NOISE BLANKER PULSE FORMER A 10 LEVEL
D98AU918
14 GND
20 CREF
November 2002
1/25
TDA7403
ABSOLUTE MAXIMUM RATINGS
Symbol VS Tamb Tstg Operating Supply Voltage Operating Ambient Temperature Range Operating Storage Temperature Range Parameter Value 10.5 -40 to 80 -55 to 150 Unit V C C
SUPPLY
Symbol VS IS SVRR Parameter Supply Voltage Supply Current Ripple Rejection @ 1KHz VS = 9V Audioprocessor (all filters flat) Stereodecoder + Audioprocessor Test Condition Min. 7.5 25 Typ. 9 30 60 55 Max. 10 35 Unit V mA dB dB
ESD All pins are protected against ESD according to the MIL883 standard. PIN CONNECTION
CASS R CASS L N.C. N.C. N.C. N.C. N.C. AM MPX LEVEL
1 2 3 4 5 6 7 8 9 10
D98AU919
20 19 18 17 16 15 14 13 12 11
CREF OUT LF OUT RF OUT LR OUT RR VS GND SDA SCL SM
THERMAL DATA
Symbol Rth-j pins Parameter Thermal Resistance Junction-pins Max Value 85 Unit C/W
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TDA7403
PIN DESCRIPTION
N. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Name CASSR CASSL n.c. n.c. n.c. n.c. n.c. AM MPX LEVEL SM SCL SDA GND VS OUTRR OUTLR OUTRF OUTLF CREF Cassette Input Right Cassette Input Left not connected not connected not connected not connected not connected AM Input FM Input (MPX) Level Input Stereodecoder Soft Mute Drive I C Clock Line I C Data Line Supply Ground Supply Voltage Right Rear Speaker Output Left Rear Speaker Output Right Front Spaeaker Output Left Front Speaker Output Reference Capacitor Pin
2 2
Function
Type I I
I I I I I/O I/O S S O O O O S
(1) See input configuration tree and databyte specification "configuration" Pin type legenda: I = Input O = Output I/O = Input/Output S = Supply
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TDA7403
AUDIO PROCESSOR PART Input Multiplexer MPX input Cassette stereo input AM mono Volume control 1dB attenuator Max. gain 20dB Max. attenuation 79dB Soft-step gain control Bass Control 2nd order frequency response Center frequency programmable in 4(5) steps DC gain programmable 7 x 2dB steps Treble Control 2nd order frequency response Center frequency programmable in 4 steps 7 x 2dB steps Speaker Control 4 independent speaker controls (1dB steps control range 50dB) Mute Functions Direct mute driven by pin SM Digitally controlled softmute with 4 programmable time constants
ELECTRICAL CHARACTERISTICS (VS = 9V; Tamb = 25C; RL = 10K; all gains = 0dB; f = 1KHz; unless otherwise specified).
Symbol Parameter Test Condition Min. Typ. Max. Unit K VRMS dB 1 dB dB dB mV mV
INPUT SELECTOR
Ri n VCL SIN GIN MIN GIN MAX GSTEP VDC Input Resistance Clipping Level Input Separation Min. Input Gain Max. Input Gain Step Resolution DC Steps Adjacent Gain Step GMIN to GMAX all inputs except Phone 70 2.2 80 -1 100 2.6 100 0 14 2 0 1 130
VOLUME CONTROL
GMAX AMAX ASTEP EA ET VDC Max Gain Max Attenuation Step Resolution Attenuation Set Error Tracking Error DC Steps G = -20 to 20dB G = -60 to 20dB Adjacent Attenuation Steps From 0dB to GMIN -1.25 -4 20 79 1 0 0 0.1 0.5 1.25 3 2 3 5 dB dB dB dB dB dB mV mV
SOFT MUTE
AMUTE TD Mute Attenuation Delay Time 70 T1 T2 T3 T4 VTHlow VTHhigh RPU VPU 4/25 Low Threshold for SM Pin (1) High Threshold for SM Pin Internal Pull-up Resistor Pull-up Voltage 2.5 70 100 4.7 100 0.48 0.96 40.4 324 1 130 dB ms ms ms ms V V K V
TDA7403
ELECTRICAL CHARACTERISTICS (continued)
Symbol Parameter Switch Time Control Range Step Resolution Center Frequency Test Condition Min. Typ. 10 14 2 60 70 80 100(2) 1 1.25 1.5 2 0 4.4 14 2 10 12.5 15 17.5 50 1 80 Adjacent Attenuation Steps d = 0.3% 2.2 2 0.1 2.6 10 120 3 10 Max. Unit ms dB dB Hz Hz Hz Hz
SOFT STEP
TSW CRANGE ASTEP fC
BASS CONTROL
QBASS
Quality Factor
DCGAIN
Bass-Dc-Gain
fC1 fC2 fC3 fC4 Q1 Q2 Q3 Q4 DC = off DC = on
dB dB dB dB KHz KHz KHz KHz dB dB dB dB mV VRMS K nF V V V dB dB % % dB dB dB
TREBLE CONTROL
CRANGE ASTEP fC Control Range Step Resolution Center Frequency
fC1 fC2 fC3 fC4
SPEAKER ATTENUATORS
CRANGE ASTEP AMUTE EE VDC VCLIP RL CL ROUT VDC Control Range Step Resolution Output Mute Attenuation Attenuation Set Error DC Steps Clipping Level Output Load Resistance Output Load Capacitance Output Impedance DC Voltage Level Output Noise
AUDIO OUTPUTS
30 3.8 BW = 20 Hz to 20 KHz output muted BW = 20 Hz to 20 KHz all gain = 0dB all gain = 0dB flat; VO = 2VRMS bass treble at 12dB; VO = 2.6VRMS VIN = 1VRMS; all stages 0dB VIN = 1VRMS; Bass & Treble = 12dB 80 AV = 0 to -20dB AV = -20 to -60dB 5 10 106 96 0.002 0.05 100 0 0
GENERAL
eNO
S/N
Signal to Noise Ratio
d SC ET
Distortion Channel separation Left/Right Total Tracking Error
1 2
1) SM pin is active low (mute condition) 2) See description of Audioprocessor Part - Bass & Treble filter characteristics programming
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TDA7403
DESCRIPTION OF THE AUDIOPROCESSOR Figure 1. Input stages
CASSETTE 100K
IN GAIN
AM 100K STEREODECODER 100K
D98AU951
MPX
Input stages The input circuits are the same as in preceeding ST audioprocessors with exception of the CD inputs (see figure 1). The typical input impedance is 100k. AutoZero In order to reduce the number of pins there is no AC coupling between the In-Gain and the following stage, so that any offset generated by or before the In-Gain stage would be transferred or even amplified to the output. To avoid that effect a special offset cancellation stage called AutoZero is implemented. To avoid audible clicks the audioprocessor is muted before the loudness stage during this time. In some cases, for example if the P is executing a refresh cycle of the I2C bus programming, it is not useful to start a new AutoZero action because no new source is selected and an undesired mute would appear at the outputs. For such applications the TDA7403 could be switched in the "Auto Zero Remain" mode (Bit 6 of the subaddress byte). If this bit is set to high, the DATABYTE 0 could be loaded without invoking the AutoZero and the old adjustment value remains. Softmute The digitally controlled softmute stage allows muting/demuting the signal with a I2C bus programmable slope. The mute process can either be activated by the softmute pin or by the I2C bus. The slope is realized in a special S shaped curve to mute slow in the critical regions (see figure 2). For timing purposes the Bit 3 of the I2C bus output register is set to 1 from the start of muting until the end of demuting.
Figure 2. Softmute Timing
EXT. MUTE
1
+SIGNAL
REF
-SIGNAL
1 I2C BUS OUT
D97AU634
Time
Note: Please notice that a started Mute action is always terminated and could not be interrupted by a change of the mute signal.
Figure 3. Soft Step Timing
VOUT
2dB
1dB
10ms -1dB
Time
-2dB
D97AU635
Note: For steps more than 1dB the softstep mode should be deactivated because it could generate a 1dB error during the blend-time
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TDA7403
Softstep Volume When volume level is changed often an audible click appears at the output. The root cause of those clicks could be either a DC offset before the volume stage or the sudden change of the envelope of the audio signal. With the Softstep feature both kinds of clicks could be reduced to a minimum and are no more audible (see figure 3). Bass There are three parameters programmable in the bass stage (see figs 4, 5, 6, 7): - Attenuation - Center Frequency (60, 70, 80 and 100Hz) - Quality Factors (1, 1.25, 1.5 and 2) DC Mode In this mode the DC gain is increased by 4.4dB. In addition the programmed center frequency and quality factor is decreased by 25% which can be used to reach alternative center frequencies or quality factors. Treble There are two parameters programmable in the treble stage (see figs 8, 9): - Attenuation - Center Frequency (10, 12.5, 15 and 17.5kHz). Speaker Attenuator Due to practical aspects the steps in the speaker attenuators are not linear over the full range. At attenuations more than 24dB the steps increase from 1.5dB to 10dB (please see data byte specification).
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TDA7403
Figure 4. Bass Control @ fc = 80Hz, Q = 1
15.0 10.0 5.0 0.0 -5.0 -10.0 -15.0 10.0 100.0 1.0K 10.0K
Figure 5. Bass Center @ Gain = 14dB, Q = 1
15.0 12.5 10.0 7.5 5.0 2.5 0.0 10.0 100.0 1.0K 10.0K
Figure 6. Bass Quality factors @ Gain = 14dB, fc = 80Hz
15.0 12.5 10.0
Figure 7. Bass normal and DC Mode @ Gain = 14dB, fc = 80Hz
15.0 12.5 10.0 7.5
7.5
5.0
5.0 2.5 0.0 10.0 100.0 1.0K 10.0K
2.5 0.0 10.0 100.0 1.0K 10.0K
Note: In general the center frequency, Q and DC-mode can be set independently. The exception from this rule is the mode (5/xx1111xx) where the center frequency is set to 150Hz instead of 100Hz.
Figure 8. Treble Control @ fc = 17.5KHz
15.0 10.0 5.0 0.0 -5.0
Figure 9. Treble Center Frequencies @ Gain = 14dB
15.0 12.5 10.0 7.5 5.0 2.5
-10.0 0.0 -15.0 10.0 100.0 1.0K 10.0K 10.0 100.0 1.0K 10.0K
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TDA7403
STEREODECODER PART No external components necessary PLL with adjustment free fully integrated VCO Automatic pilot dependent MONO/STEREO switching Very high suppression of intermodulation and interference Programmable Roll-Off compensation Dedicated RDS Softmute Highcut and Stereoblend characterisctics programmable in a wide range Internal Noiseblanker with threshold controls Multipath detector with programmable internal/external influence I2C bus control of all necessary functions
ELECTRICAL CHARACTERISTICS (VS = 9V; deemphasis time constant = 50s, VMPX = 500mV, 75KHz deviation, f = 1KHz. GI = 6dB, Tamb = 25C; unless otherwise specified).
Symbol VIN Ri n Gmin Gmax GSTEP SVRR THD S+N N Parameter MPX Input Level Input Resistance Minimum Input Gain Max Input Gain Step Resolution Supply Voltage Ripple Rejection Max Channel Separation Total Harmonic Distortion Signal plus Noise to Noise Ratio Test Condition Input Gain = 3.5dB Min. Typ. 0.5 100 3.5 11 2.5 60 50 0.05 86 Max. 1.25 Unit VRMS K dB dB dB dB dB % dB
Vripple = 100mv, f = 1khz
S = 2Vrms
MONO/STEREO SWITCH
VPTHST1 VPTHST0 VPTHMO1 VPTHMO0 Pilot Threshold Voltage Pilot Threshold Voltage Pilot Threshold Voltage Pilot Threshold Voltage for Stereo, PTH = 1 for Stereo, PTH = 0 for Mono, PTH = 1 for Stereo, PTH = 0 15 25 12 19 mV mV mV mV
PLL
f/f HC50 HC75 HC50 HC75 Capture Range 0.5 % s s s s
DEEMPHASIS and HIGHCUT
Deemphasis Time Constant Deemphasis Time Constant Highcut Time Constant Highcut Time Constant Bit = 7, Subadr. 10 = 0 VLEVEL >> VHCH Bit = 7, Subadr. 10 = 1 VLEVEL >> VHCH Bit = 7, Subadr. 10 = 0 VLEVEL >> VHCL Bit = 7, Subadr. 10 = 1 VLEVEL >> VHCL 50 75 150 225
STEREOBLEND and HIGHCUT-CONTROL
REF5V TCREF5V LGmin LGmax LGstep VSBLmin VSBLmax VSBLstep Internal Reference Voltage Temperature Coefficient Min. LEVEL Gain Max. LEVEL Gain LEVEL Gain Step Resolution Min.Voltage for Mono Max. Voltage for Mono Step Resolution 5 3300 0 10 0.67 33 58 8.4 V ppm dB dB dB %REF5V %REF5V %REF5V
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TDA7403
ELECTRICAL CHARACTERISTICS (continued)
Symbol Parameter Test Condition Min. Typ. Max. Unit
STEREOBLEND and HIGHCUT CONTROL
VHCHmin VHCHmax VHCHstep VHCLmin VHCLmax 19 38 57 76 2 3 57 67 114 190 Min.Voltage for NO Highcut Max. Voltage for NO Highcut Step Resolution Min. Voltage for FULL High cut Max. Voltage for FULL High cut 42 66 8.4 17 33 %REF5V %REF5V %REF5V %VHCH %VHCH
Carrier and harmonic suppression at the output
Pilot Signal Subcarrier Subcarrier Subcarrier f = 19KHz f = 38KHz f = 57KHz f = 76KHz 50 75 62 90 dB dB dB dB
Intermodulation (Note1)
Pilot Signal fmod = 10KHz; fspur = 1KHz; fmod = 13KHz; fspur = 1KHz; f = 57KHz 65 75 dB dB
Traffic Radio (Note 2)
Signal 70 dB
SCA - Subsidiary Communications Authorization (Note 3)
Signal f = 67KHz 75 dB
ACI - Adjacent Channel Interference (Note 4)
Signal Signal f = 114KHz f = 190KHz 95 84 dB dB
Notes to the characteristics: 1. Intermodulation Suppression: measured with: 91% pilot signal; fm = 10kHz or 13kHz. 2. Traffic Radio (V.F.) Suppression: measured with: 91% stereo signal; 9% pilot signal; fm=1kHz; 5% subcarrier (f = 57kHz, fm = 23Hz AM, m = 60%) 3. SCA ( Subsidiary Communications Authorization ) measured with: 81% mono signal; 9% pilot signal; fm = 1kHz; 10%SCA - subcarrier ( fs = 67kHz, unmodulated ). 4. ACI ( Adjacent Channel Interference ) measured with: 90% mono signal; 9% pilot signal; fm =1kHz; 1% spurious signal ( fs = 110kHz or 186kHz, unmodulated).
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TDA7403
NOISE BLANKER PART internal 2nd order 140kHz high pass filter programmable trigger threshold
additional circuits for trigger adjustment (deviation, field-strenght) very low offset current during hold time four selectable pulse suppression times
ELECTRICAL CHARACTERISTICS (continued)
Symbol VTR Parameter Trigger Threshold 0) 1) Test Condition meas. with VPEAK = 0.9V Min. NBT = 111 NBT = 110 NBT = 101 NBT = 100 NBT = 011 NBT = 010 NBT = 001 NBT = 000 NCT = 00 NCT = 01 NCT = 10 NCT = 11 Typ. 30 35 40 45 50 55 60 65 260 220 180 140 0.9 1.7 2.5 0.9(off) 1.2 2.0 2.8 0.9(off) 1.3 1.8 2.3 Max. Unit mVOP mVOP mVOP mVOP mVOP mVOP mVOP mVOP mVOP mVOP mVOP mVOP V V V VOP VOP VOP VOP V V V V
VTRNOISE
Noise Controlled Trigger Threshold 2)
meas. with VPEAK = 1.5V
VRECT
Rectifier Voltage
VRECT DEV
deviation dependent rectifier Voltage 3)
VRECT FS
Fieldstrength Controlled Rectifier Voltage 4)
VMPX = 0mV VMPX = 50mV; f = 150KHz VMPX = 100mV; f = 150KHz means. with OVD = 11 VMPX = 800mV OVD = 10 (75KHz dev.) OVD = 01 OVD = 00 FSC = 11 means. with VMPX = 0mV FSC = 10 VLEVEL << VSBL FSC = 01 (fully mono) FSC = 00
0) All thresholds are measured using a pulse with TR = 2 s, THIGH = 2 s and TF = 10 s. 1) NBT represents the Noiseblanker-Byte bits D2; D0 for the noise blanker trigger threshold 2) NAT represents the Noiseblanker-Byte bit pair D4,D3 for the noise controlled trigger adjustment 3) OVD represents the Noiseblanker-Byte bit pair D7,D6 for the over deviation detector 4) FSC represents the Fieldstrength-Byte bit pair D1,D0 for the fieldstrength control
VIN VOP
DC
D97AU636
TR
THIGH
TF
Time
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TDA7403
Figure 10. Trigger Threshold vs. VPEAK
VTH
260mV(00) 220mV(01) 180mV(10) 140mV(11) MIN. TRIG. THRESHOLD NOISE CONTROLLED TRIG. THRESHOLD 65mV 8 STEPS 30mV VPEAK(V)
0.9V
D97AU648
1.5V
Figure 11. Deviation Controlled Trigger Adjustment
Figure 12. Fieldstrength Controlled Trigger Adjustment
VPEAK MONO STEREO
VPEAK (VOP) 00
»3V
2.8 2.0
01
10 1.2 0.9
2.3V(00) 1.8V(01) 1.3V(10) NOISE ATC_SB OFF (11)
0.9V
DETECTOR OFF (11)
D97AU649
20
32.5
45
75
DEVIATION(KHz)
noisy signal
D98AU863
good signal
E'
Figure 13. Block diagram of the stereo decoder
DEMODULATOR INGAIN MPX 100K 3.5 ... 11dB STEP 2.5dB INFILTER LP 80KHz 4.th ORDER - PLOT CANC - ROLL-OFF COMP. - LP 25KHz DEEMPHASIS + HIGHCUT t=50 or 75s
FM_L
FM_R
PLL + PILOT-DET. F19 F38 STEREO NOISE BLANKER SB CONTROL
REF 5V VSBL
HC CONTROL D A
VHCCH VHCCL
LEVEL INPUT LEVEL INTERN LP 2.2KHZ 1.th ORDER GAIN 0..10dB
D98AU952
HOLDN
LEVEL
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TDA7403
DESCRIPTION OF STEREODECODER The stereodecoder part of the TDA7403 (see Fig. 16) contains all functions necessary to demodulate the MPX signal like pilot tone dependent MONO/STEREO switching as well as "stereoblend" and "highcut" functions. Adaptations like programmable input gain, roll-off compensation, selectable deemphasis time constant and a programmable fieldstrength input allow to use different IF devices.
Figure 14. Signals during stereodecoder's softmute
SOFTMUTE COMMAND t STD MUTE
t
Stereodecoder Mute The TDA7403 has a fast and easy to control RDS mute function which is a combination of the audioprocessor softmute and the high-ohmic mute of the stereodecoder. If the stereodecoder is selected and a softmute command is sent (or activated through the SM pin) the stereodecoder will be set automatically to the high-ohmic mute condition after the audio signal has been softmuted. Hence a checking of alternate frequencies could be performed. To release the system from the mute condition simply the unmute command must be sent: the stereodecoder is unmuted immediately and the audioprocessor is softly unmuted. Fig. 14 shows the output signal VO as well as the internal stereodecoder mute signal. This influence of Softmute on the stereodecoder mute can be switched off by setting bit 3 of the Softmute byte to "0". A stereodecoder mute command (bit 0, stereodecoder byte set to "1") will set the stereodecoder in any case independently to the high-ohmic mute state. If any other source than the stereodecoder is selected the decoder remains muted and the MPX pin is connected to Vref to avoid any discharge of the coupling capacitor through leakage currents. Input Stages The Ingain stage allows to adjust the MPX signal to a magnitude of about 1Vrms internally which is the recommended value. The 4.th order input filter has a corner frequency of 80kHz and is used to attenuate spikes and noise and acts as an antialiasing filter for the following switch capacitor filters. Demodulator In the demodulator block the left and the right channel are separated from the MPX signal. In this stage also the 19 kHz pilot tone is cancelled. For reaching a high channel separation the TDA7403 offers an I2C bus programmable roll-off adjustment which is able to compensate the low-
VO
D97AU638
t
pass behaviour of the tuner section. If the tuner attenuation at 38kHz is in a range from 20.2% to 31% the TDA7403 needs no external network before the MPX pin. Within this range an adjustment to obtain at least 40dB channel separation is possible. The bits for this adjustment are located together with the fieldstrength adjustment in one byte. This gives the possibility to perform an optimization step during the production of the carradio where the channel separation and the fieldstrength control are trimmed.
Deemphasis and Highcut The lowpass filter for the deemphasis allows to choose between a time constant of 50s and 75s (bit D7, Stereodecoder byte). The highcut control range will be in both cases tHC = 2 tDeemp. Inside the highcut control range (between VHCH and VHCL) the LEVEL signal is converted into a 5 bit word which controls the lowpass time constant between t Deemp...3 tDeemp. There by the resolution will remain always 5 bits independently of the absolute voltage range between the VHCH and VHCL values. The highcut function can be switched off by I2C bus (bit D7, Fieldstrength byte set to "0"). PLL and Pilot Tone Detector The PLL has the task to lock on the 19kHz pilotone during a stereo transmission to allow a correct demodulation. The included detector enables the demodulation if the pilot tone reaches the selected pilottone threshold VPTHST. Two different thresholds are available. The detector output (signal STEREO, see block diagram) can be checked
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TDA7403
by reading the status byte of the TDA7403 via I2C bus. Fieldstrength Control The fieldstrength input is used to control the high cut and the stereoblend function. In addition the signal can be also used to control the noiseblanker thresholds. LEVEL Input and Gain To suppress undesired high frequency modulation on the highcut and stereoblend function the LEVEL signal is lowpass filtered firstly. The filter is a combination of a 1st order RC lowpass at 53kHz (working as anti-aliasing filter) and a 1storder switched capacitor lowpass at 2.2kHz. The second stage is a programmable gain stage to adapt the LEVEL signal internally to different IF. The gain is widely programmable in 16 steps from 0dB to 10dB (step = 0.67dB). These 4 bits are located together with the Roll-Off bits in the "Stereodecoder Adjustment" byte to simplify a possible adaptation during the production of the carradio. Stereoblend Control The stereoblend control block converts the internal LEVEL voltage (LEVEL INTERN) into an demodulator compatible analog signal which is used to control the channel separation between 0dB and the maximum separation. Internally this control range has a fixed upper limit which is the internal reference voltage REF5V. The lower limit can be programmed to be 33%, 42%, 50% or 58% of REF5V (see fig. 16). To adjust the external LEVEL voltage to the internal range two values must be defined: the LEVEL
Figure 15. Internal stereoblend characteristics
gain LG and VSBL. To adjust the voltage where the full channel separation is reached (VST) the LEVEL gain LG has to be defined. The following equation can be used to estimate the gain: LG =
REF5V
Field strength voltage [STEREO]
The gain can be programmed through 4 bits in the "Stereodecoder-Adjustment" byte. The MONO voltage VMO (0dB channel separation) can be choosen selecting 33, 42, 50 or 58% of REF5V. All necessary internal reference voltages like REF5V are derived from a bandgap circuit. Therefore they have a temperature coefficient near zero. This is useful if the fieldstrength signal is also temperature compensated. But most IF devices apply a LEVEL voltage with a TC of 3300ppm. The TDA7403 offers this TC for the reference voltages, too. The TC is selectable with bit D7 of the "stereodecoder adjustment" byte.
Figure 16. Relation between internal and external LEVEL voltage and setup of Stereoblend
INTERNAL VOLTAGES REF 5V INTERNAL VOLTAGES LEVEL INTERN REF 5V
SETUP OF VST
SETUP OF VMO
LEVEL INTERN
LEVEL VSBL
58% 50% VSBL 42% 33%
VMO
VST
t FIELDSTRENGHT VOLTAGE
D97AU639
VMO
VST
t FIELDSTRENGHT VOLTAGE
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TDA7403
Highcut Control The highcut control setup is similar to the stereoblend control setup : the starting point VHCH can be set with 2 bits to be 42, 50, 58 or 66% of REF5V whereas the range can be set to be 17 or 33% of VHCH (see fig. 17). Figure 17. Highcut characteristics
LOWPASS TIME CONSTANT
supplied by his own biasing circuit. Trigger Path The incoming MPX signal is highpass filtered, amplified and rectified. This second order highpass-filter has a corner frequency of 140kHz. The rectified signal, RECT, is lowpass filtered to generate a signal called PEAK. Also noise with a frequency 140kHz increases the PEAK voltage. The PEAK voltage is fed to a threshold generator, which adds to the PEAK voltage a DC dependent threshold VTH. Both signals, RECT and PEAK+VTH are fed to a comparator which triggers a re-triggerable monoflop. The monoflop's output activates the sample-and-hold circuits in the signalpath for 40s. The block diagram of the noiseblanker is given in fig.18. Automatic Noise Controlled Threshold Adjustment (ATC) There are mainly two independent possibilities for programming the trigger threshold: a the low threshold in 8 steps (bits D0 to D2 of the noiseblanker byte) b the noise adjusted threshold in 4 steps (bits D3 and D4 of the noiseblanker byte, see fig. 13). The low threshold is active in combination with a good MPX signal without any noise; the PEAK voltage is less than 1V. The sensitivity in this operation is high. If the MPX signal is noisy the PEAK voltage increases due to the higher noise, which is also rectified. With increasing of the PEAK voltage the trigger threshold increases, too. This particular gain is programmable in 4 steps (see fig. 10).
3·Deemp
Deemp
VHCL
D97AU640
VHCH
FIELDSTRENGHT
FUNCTIONAL DESCRIPTION OF THE NOISEBLANKER In the automotive environment the MPX signal is disturbed by spikes produced by the ignition and for example the wiper motor. The aim of the noiseblanker part is to cancel the audible influence of the spikes. Therefore the output of the stereodecoder is held at the actual voltage for 40s. In a first stage the spikes must be detected but to avoid a wrong triggering on high frequency (white) noise a complex trigger control is implemented. Behind the triggerstage a pulse former generates the "blanking" pulse. To avoid any crosstalk to the signalpath the noiseblanker is Figure 18. Block diagram of the noiseblanker
MPX
HIGH PASS
RECTIFIER
RECT
+ VTH
MONOFLOP
HOLDN
+
PEAK LOWPASS +
THRESHOLD GENERATOR
ADDITIONAL THRESHOLD CONTROL
D98AU861
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TDA7403
Automatic Threshold Control Besides the noise controlled threshold adjustment there is an additional possibility for influencing the trigger threshold. It is depending on the stereoblend control. The point where the MPX signal starts to become noisy is fixed by the RF part. Therefore also the starting point of the normal noise-controlled trigger adjustment is fixed (fig. 15). In some cases the behaviour of the noiseblanker can be improved by increasing the threshold even in a region of higher fieldstrength. Sometimes a wrong triggering occures for the MPX signal often shows distortion in this range which can be avoided even if using a low threshold. Because of the overlap of this range and the range of the stereo/mono transition it can be controlled by stereoblend. This threshold increase is programmable in 3 steps or switched off with bits D0 and D1 of the fieldstrength control byte. Over Deviation Detector If the system is tuned to stations with a high deviation the noiseblanker can trigger on the higher frequencies of the modulation. To avoid this wrong behaviour, which causes noise in the output signal, the noiseblanker offers a deviation dependent threshold adjustment. By rectifying the MPX signal a further signal representing the actual deviation is obtained. It is used to increase the PEAK voltage. Offset and gain of this circuit are programmable in 3 steps with the bits D6 and D7 of the stereodecoder byte (the first step turns off the detector, see fig. 15). TEST MODE During the test mode which can be activated by setting bit D0 of the testing byte and bit D5 of the subaddress byte to "1" several internal signals are available at the CASSR pin. During this mode the input resistance of 100kOhm is disconnected from the pin. The internal signals available are shown in the software specification.
Figure 19. Application Example.
10F
VS +VCC = 9V 100nF CASS R 100nF
CREF
OUTLF
OUTLF
OUTRF CASS R OUTLR
OUTRF
OUTLR
100nF CASS L
CASS L
OUTRR
OUTRR
SDA
SDA
220nF MPX
MPX
SCL
SCL
SMUTE 220nF AM AM
SMUTE
LEVEL GND
D98AUxx5
LEVEL
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I2C BUS INTERFACE DESCRIPTION Interface Protocol The interface protocol comprises: -a start condition (S) -a chip address byte (the LSB bit determines read
CHIP ADDRESS MSB S 1 0 0 0 1 1 LSB 0 R/W ACK MSB X AZ T I
/ write transmission) -a subaddress byte -a sequence of data (N-bytes + acknowledge) -a stop condition (P)
SUBADDRESS LSB A3 A2 A1 A0 ACK MSB
DATA 1 to DATA n LSB DATA ACK P
D97AU627
S = Start ACK = Acknowledge AZ = AutoZero-Remain T = Testing I = Autoincrement P = Stop MAX CLOCK SPEED 500kbits/s The transmitted data is automatically updated after each ACK. Transmission can be repeated without new chip address. SUBADDRESS (receive mode) MSB
X AZ T I A3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
Auto increment If bit I in the subaddress byte is set to "1", the autoincrement of the subaddress is enabled. TRANSMITTED DATA (send mode)
MSB X X X X ST SM X LSB X
SM = Soft mute activated ST = Stereo X = Not Used
LSB
A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
FUNCTION
Not allowed Auto-Zero Volume Softmute Bass / Treble Attenuator Bass / Treble Configuration Speaker attenuator LF Speaker attenuator LR Speaker attenuator RF Speaker attenuator RR / Blanktime adjust Stereodecoder Noiseblanker Fieldstrength Control Configuration Stereodecoder Adjustment Testing
T = Testmode I = Autoincrement AZ = Auto Zero Remain X = not used
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DATA BYTE SPECIFICATION Input Selector MSB
D7 D6 D5 D4 D3 D2 0 0 0 0 1 1 1 1 X 1 0 0 1 0 0 : 1 1 0 0 : 1 1 0 1 : 0 1 0 0 1 1 1 1 0 0 1 1 0 0 D1 0 0 1 1 0 0 1 1
LSB
D0 0 1 0 1 0 1 0 1
FUNCTION
Source Selector don't use Cassette don't use AM Stereo Decoder don't use Mute don't use Don't Care AM/FM Mode AM mono AM stereo AM through Stereo/Decoder FM- Stereo/Decoder In-Gain 14dB 12dB : 2 dB 0 dB
For example to select the CD input in quasi-differential mode with gain of 8dB the Data Byte is: 0/01111000
Autozero MSB
D7 1 D6 1 D5 1 D4 1 D3 0 D2 0 D1 0
LSB
D0 0 setting fix
LOUDNESS
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Mute, Beep and Mixing MSB
D7 D6 D5 D4 D3 D2 D1
LSB
D0 0 1 0 0 1 1 0 1 0 1 0 1
MUTE/BEEP/MIXING
Mute Enable Softmute Disable Softmute Mute time =0.48 ms Mute time =0.96 ms Mute time =40.4 ms Mute time =324 ms Stereo Decoder Softmute Influence = off Stereo Decoder Softmute Influence = on Must be "1"
1
1
1
1
Note: for more information to the Stereodecoder-Softmute-Influence please refer to the stereodecoder description.
Volume MSB
D7 D6 0 0 : 0 0 0 : 0 0 0 : 1 1 0 1 D5 0 0 : 0 0 0 : 0 1 1 : 1 1 D4 0 0 : 0 0 0 : 1 0 0 : 0 0 D3 0 0 : 1 1 1 : 1 0 0 : 1 1 D2 0 0 : 1 1 1 : 1 0 0 : 1 1 D1 0 0 : 0 0 1 : 1 0 0 : 1 1
LSB
D0 0 1 : 0 1 0 : 1 0 1 : 0 1
ATTENUATION
Gain/Attenuation +32dB +31dB : +20dB +19dB +18dB : +1dB 0dB - 1dB : -78dB -79dB Softstep Softstep Volume = off Softstep Volume = on
Note: It is not recommended to use a gain more than 20dB for system performance reason. In general, the max. gain should be limited by software to the maximum value, which is needed for the system.
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Bass & Treble Attenuation MSB
D7 D6 D5 D4 D3 0 0 : 0 0 1 1 : 1 1 0 0 : 0 0 1 1 : 1 1 0 0 : 1 1 1 1 : 0 0 0 0 : 1 1 1 1 : 0 0 0 1 : 0 1 1 0 : 1 0 D2 0 0 : 1 1 1 1 : 0 0 D1 0 0 : 1 1 1 1 : 0 0
LSB
D0 0 1 : 0 1 1 0 : 1 0
BASS & TREBLE ATTENUATION
Treble Steps -14dB -12dB : -2dB 0dB 0dB +2dB : +12dB +14dB Bass Steps -14dB -12dB : -2dB 0dB 0dB +2dB : +12dB +14dB
For example 12dB Treble and -8dB Bass give the following DATA BYTE : 0 0 1 1 1 0 0 1.
Bass & Treble Filter Characteristics MSB
D7 D6 D5 D4 D3 D2 D1 0 0 1 1 0 0 1 1 1 0 1 0 1 1
LSB
D0 0 1 0 1
BASS & TREBLE FILTER
Treble Center Frequency = 10 KHz Center Frequency = 12.5 KHz Center Frequency = 15 KHz Center Frequency = 17.5 KHz Bass Center Frequency = 60 Hz Center Frequency = 70 Hz Center Frequency = 80 Hz Center Frequency = 100Hz Center Frequency = 150Hz Quality factor = 1 Quality factor = 1.25 Quality factor = 1.5 Quality factor = 2 DC-Gain = 0dB DC-Gain = 4.4dB must be "1"
1 0 0 1 1 0 1 1
1 0 1 0 1
For example Treble center frequency = 15kHz, Bass center frequency = 100Hz, Bass Q = 1 and DC = 0dB give the following DATA BYTE: 1 0001110
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Speaker Attenuation (LF, LR, RF, RR) MSB
D7 D6 D5 0 0 : 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 1 0 1 0 1 D4 0 0 : 1 1 1 1 1 1 1 1 1 D3 0 0 : 0 1 1 1 1 1 1 1 1 D2 0 0 : 1 0 0 0 0 1 1 1 1 D1 0 0 : 1 0 0 1 1 0 0 1 1
LSB
D0 0 1 : 1 0 1 0 1 0 1 0 1 Attenuation 0dB -1dB : -23dB -24.5dB -26dB -28dB -30 -32dB -35dB -40dB -50dB Speaker Mute Must be "1" (except RR speaker; see below) Blank Time adj. (only at RR speaker) 38s 25.5s 32s 22s
Stereodecoder MSB
D7 D6 D5 D4 D3 D2 D1
LSB
D0 0 1 STD Unmuted STD Muted IN-Gain 11dB IN-Gain 8.5dB IN-Gain 6dB IN-Gain 3.5dB
FUNCTION
0 0 1 1 1 1 1 0 1 0 1 0 1
0 1 0 1
must be "1" Forced MONO MONO/STEREO switch automatically Pilot Threshold HIGH Pilot Threshold LOW Deemphasis 50s Deemphasis 75s
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Noiseblanker MSB
D7 D6 D5 D4 D3 D2 0 0 0 0 1 1 1 1 0 0 1 1 0 1 0 0 1 1 0 1 0 1 0 1 0 1 D1 0 0 1 1 0 0 1 1
LSB
D0 0 1 0 1 0 1 0 1
FUNCTION
Low Threshold 65mV Low Threshold 60mV Low Threshold 55mV Low Threshold 50mV Low Threshold 45mV Low Threshold 40mV Low Threshold 35mV Low Threshold 30mV Noise Controlled Threshold 320mV Noise Controlled Threshold 260mV Noise Controlled Threshold 200mV Noise Controlled Threshold 140mV Noise blanker OFF Noise blanker ON Over deviation Adjust 2.8V Over deviation Adjust 2.0V Over deviation Adjust 1.2V Over deviation Detector OFF
Fieldstrength Control MSB
D7 D6 D5 D4 D3 D2 D1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 0 1 0 1 0 1 0 1 0 1
LSB
D0 0 1 0 1
FUNCTION
Noiseblanker Field strength Adj 2.3V Noiseblanker Field strength Adj 1.8V Noiseblanker Field strength Adj 1.3V Noiseblanker Field strength Adj OFF VSBL at 33% REF 5V VSBL at 42% REF 5V VSBL at 50% REF 5V VSBL at 58% REF 5V VHCH at 42% REF 5V VHCH at 50% REF 5V VHCH at 58% REF 5V VHCH at 66% REF 5V VHCL at 17% VHCH VHCL at 33% VHCH High cut OFF High cut ON
Configuration MSB
D7 1 D6 1 D5 1 D4 1 D3 1 D2 1 D1 1
LSB
D0 1 setting fix
FUNCTION
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Stereodecoder Adjustment MSB
D7 D6 D5 D4 D3 D2 0 0 0 : 1 : 1 0 0 0 : 1 0 1 0 0 0 : 1 0 0 1 : 1 0 1 0 : 1 D1 0 0 1 : 0 : 1
LSB
D0 0 1 0 : 0 : 1
FUNCTION
Roll-Off Compensation not allowed 20.2% 21.9% : 25.5% : 31.0% LEVEL Gain 0dB 0.66dB 1.33dB : 10dB Temperature compensation at LEVEL input TC = 0 TC = 16.7mV/K (3300ppm)
Testing MSB
D7 D6 D5 D4 D3 D2 D1
LSB
D0 0 1 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
FUNCTION
Stereodecoder test signals OFF Test signals enabled if bit D5 of the subaddress (test mode bit) is set to "1", too External Clock Internal Clock Testsignals at CASS_R VHCCH Level intern Pilot magnitude VCOCON; VCO Control Voltage Pilot threshold HOLDN NB threshold F228 VHCCL VSBL not used not used PEAK not used REF5V not used VCO OFF ON Audioprocessor test mode only if bit D5 of the subaddress (test mode bit) is set to "1" OFF
0 1
Note : This byte is used for testing or evaluation purposes only and must not be set to other values than the default "11111110" in the application!
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mm DIM. MIN. A A1 B C D E e H h L K 10 0.25 0.4 2.35 0.1 0.33 0.23 12.6 7.4 1.27 10.65 0.75 1.27 0.394 0.010 0.016 TYP. MAX. 2.65 0.3 0.51 0.32 13 7.6 MIN. 0.093 0.004 0.013 0.009 0.496 0.291
inch TYP. MAX. 0.104 0.012 0.020 0.013 0.512 0.299 0.050 0.419 0.030 0.050
OUTLINE AND MECHANICAL DATA
SO20
0 (min.)8 (max.)
L
h x 45
A B e K H D A1 C
20
11 E
1
0 1
SO20MEC
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 2002 STMicroelectronics Printed in Italy All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com
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