TDA7502
In-car remote amplifier DSP
Features
24-Bit fixed-point dsp core delivering up to 50 MIPS 2 x 1024 x 24 Bit of RAM for X and Y data memory. 3072 x 24 Bit of RAM for program also usable for delay Serial audio interface. Debug port. Control interface for external GPIOs, interrupts, and reset. SPI and I2C for communication between external micro and DSP. Both master and slave operating modes. PLL clock oscillator 5V-tolerant 3.3V I/O interface The computational power and the memory configuration make this device particularly suitable for in car equalisation. This device will offer the best trade-off between performance and cost when coupled with the TDA7535, or other devices of the same family. A library of sound processing functions is available for this device; some of these functions are: parametric equaliser, cross over filters, acoustic delay, dynamic compression, vol/bass/treble/fader, active equalisation, Stereo spatial enhancement and more.
LQFP44 (10x 10x 1.4mm)
Description
This device is a high-performance, fully programmable DSP, suitable for a wide range of applications and particularly for audio and sound processing. It contains a 24-bit 50 MIPS DSP core, several interfaces for control and data, plus a configurable PLL.
Order codes
Part numbers TDA7502 TDA7502013TR Package LQFP44 (10x 10x 1.4mm) LQFP44 (10x 10x 1.4mm) Packing Tube Tape and Reel
November 2006
Rev 11
1/25
www.st.com 1
Contents
TDA7502
Contents
1 2 3 4 5 6 Block diagram and PIN description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 SAI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 SPI interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 I2C timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.1 6.2 6.3 24-BIT DSP core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 DSP peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Data and program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.3.1 6.3.2 6.3.3 6.3.4 6.3.5 6.3.6 6.3.7 6.3.8 6.3.9 1024 x 24-Bit X-RAM (XRAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1024 x 24 Bit Y-RAM (YRAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3072 X 24-Bit Program RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 512 x 24-Bit Bootstrap ROM (Boot ROM) . . . . . . . . . . . . . . . . . . . . . . . 18 Serial audio interface (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 General purpose input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 PLL clock oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7 8 9
Application scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2/25
TDA7502
List of tables
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Recommended DC operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 General interface electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Low voltage TTL interface DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 DSP core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 SPI interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Debug port interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Casper IC boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3/25
List of figures
TDA7502
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin connection (Top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Maximum DSP clock frequency (Fdsp) versus junction temperature (Tj). . . . . . . . . . . . . . 10 SAI timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 SAI protocol when RLRS=0; RREL=0; RCKP=1; RDIR=0 . . . . . . . . . . . . . . . . . . . . . . . . . 11 SAI protocol when RLRS=1; RREL=0; RCKP=1; RDIR=1. . . . . . . . . . . . . . . . . . . . . . . . . 12 SAI protocol when RLRS=0; RREL=0; RCKP=0; RDIR=0. . . . . . . . . . . . . . . . . . . . . . . . . 12 SAI protocol when RLRS=0; RREL=1; RCKP=1; RDIR=0. . . . . . . . . . . . . . . . . . . . . . . . . 12 SPI clocking scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Debug port serial clock timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Debug port acknowledge timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Debug port data I/O to status timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Debug port read timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Debug port DBCK next command after read register timing. . . . . . . . . . . . . . . . . . . . . . . . 15 Definition of timing for the I2C bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Application schematic for TDA7502 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Block diagram of car amplifier audio sub-system. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 TQFP44 (10x10) mechanical data & package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . 23
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TDA7502
Block diagram and PIN description
1
Block diagram and PIN description
Figure 1. Block diagram
SDI0 SDI1 SDI2 SDO0 SDO1 SDO2 VDD3 GND3 SCANEN TESTEN VDD4 LRCLKT SCKT LRCLKR SCKR YAB SCL SDA I2C INTERFACE YDB 1024 x 24 Y-RAM SERIAL AUDIO INTERFACE XAB XDB 1024 x 24 X-RAM GND4
VDD5 GND5
VDD6 GND6
PAB SS SCK MISO MOSI GPIO3 GPIO4 GPIO5 GPIO RESET 128 x 24 BOOT-ROM SPI INTERFACE PDB 3072 x 24 P/DELAY-RAM
DBCK/GPIO1 DBIN/GPIO2
DEBUG INTERFACE
ORPHEUS 24bit DSP CORE
INT
PLL OSCILLATOR
PVCC PGND
DBRQN/GPIO3
DBRQ
VDD1 GND1
VDD2 GND2
XTO
XTI CLKOUT D99AU1034
Figure 2.
Pin connection (Top view)
GPIO5 GPIO4 GPIO3 GND6 VDD6 MISO MOSI SCK SDA
35
44
43
42
41
40
39
38
37
36
34 33 32 31 30 29 28 27 26 25 24 23
VDD1 GND1 INT SCANEN TESTEN DBRQN DBOUT VDD2 GND2 DBCK DBIN
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
SCL
SS
SCKT LRCKT GND5 VDD5 SDO2 SDO1 SDO0 GND4 VDD4 SCKR LRCKR
CLKOUT
PGND
PVCC
VDD3
RESET
GND3
XTO
XTI
SDI0
SDI1
SDI2
D99AU1035
5/25
Block diagram and PIN description Table 1.
N. 1 2 3
TDA7502
Pin description
Name VDD1 GND1 INT Type P G I/O Reset status 3.3V core supply. Core ground. External interrupt line (Input/Output). When this line is asserted low, the DSP may be interrupted. Acts as IRQA line of DSP core. SCAN enable when active with TESTEN also active, controls theshifting of the internal scan chains. Test enable when active, puts the chip into test mode and muxes the XTI clock to all flip-flops. When SCANEN is also active, the scan chain shifting Debug port request Input. A means of entering the Debug mode of operation. The serial data output for the Debug port. Can also be used as a GPIO. 3.3V core supply. Core ground. Debug port Bit Clock/Chip status 1. The serial clock for the Debug Port is provided when an input. When an output, provides information about the chip status. Can also be used as GPIO Debug port Serial Input/Chip status 0. The serial data input for the Debug Port is provided when an input. When an output, provides information about the chip status. Can also be used as GPIO. Output clock. PLL clock ground Input. Ground connection for oscillator circuit. PLL clock power supply. Positive supply for PLL clock oscillator. Cr ystal oscillator output. Crystal oscillator output drive. Cr ystal oscillator input. External clock input or crystal connection. System reset. A logic low level applied to RESET input initializes DSPs. During debug mode if this pin is pulled low in while the DBRQN line is pulled low then the DSP pointed to by the DBSEL pin will be reset. 3.3V supply. Ground. SDI0 is a stereo digital audio data input pin channel 0. SDI1 is a stereo digital audio data input pin channel 1. SDI2 is a stereo digital audio data input pin channel 2. Function
4
SCANEN
I
5
TESTEN
I
6 7 8 9
DBRQN DBOUT/GPIO2 VDD2 GND2
I I/O I I
I
10
DBCK/GPIO0
I/O
I
11
DBIN/GPIO1
I/O
I
12 13 14 15 16
CLKOUT PGND PVCC XTO (1) XTI (1)
O G P O I
High
17
RESET
I/O
I
18 19 20 21 22
VDD3 GND3 SDI0 SDI1 SDI2
P G I I I
6/25
TDA7502 Table 1.
N. 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
Block diagram and PIN description Pin description (continued)
Name LRCKR SCKR VDD4 GND4 SDO0 SDO1 SDO2 VDD5 GND5 LRCKT SCKT SCL SDA SCK SS MOSI Type I/O I/O P G O O O P G I/O I/O I/O I/O I I I/O Reset status High High High Function Left-right clock for SAI Receiver. Master or slave. SAI receive bit clock. Master or slave. 3.3V supply. Ground. SDO0 is a stereo digital audio data output pin channel 0. SDO1 is a stereo digital audio data output pin channel 1. SDO2 is a stereo digital audio data pin channel 2. 3.3V supply. Ground. SAI transmit left/right clock. Master or slave. SAI transmit bit clock. Master or slave. Clock line for I2C bus. Schmitt trigger input. Data line for I2C bus. Schmitt trigger input. Bit clock for SPI control interface. Slave select input pin for SPI control interface. Serial data output for SPI type serial port when in SPI master mode and serial data input when in SPI slave mode. Serial data input for SPI style serial port when in SPI master mode and serial data output when in SPI slave mode. 3.3V supply. Ground. This pin is dedicated as general I/O. This pin is dedicated as general I/O. This pin is dedicated as general I/O.
39 40 41 42 43 44
MISO VDD6 GND6 GPIO3 GPIO4 GPIO5
I/O P G I/O I/O I/O
1. XTI and XTO are not 5V tolerant
7/25
Electrical specifications
TDA7502
2
Electrical specifications
Table 2.
Symbol Vdd Vin Vin Tj Tstg DC supply voltage Digital input voltage (XTI and XTO only) Digital input voltage
(1)
Absolute maximum ratings
Parameter Value -0.5 to 4.6 -0.5 to (VDD +0.5) 6.5 -40 to 125 -55 to 150 Unit V V V C C
Operating junction temperature range Storage temperature
1. When the IC is powered.
Warning:
Operation at or beyond these limit may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
Table 3.
Symbol
Thermal data
Parameter Value 68 Unit C/W
Rth j-amb (1) Thermal resistance junction to ambient
1. In still air.
Table 4.
Symbol Vdd
Recommended DC operating conditions
Parameter 3.3V power supply voltage Test condition Min. 3.15 Typ. 3.3 Max. 3.45 Unit V
Table 5.
Symbol Idd
Current consumption
Parameter Maximum current Test condition @3.3V and Tj =125C Min. Typ. Max. 250 Unit mA
Note: Table 6.
Symbol
50MHz internal DSP clock Pll characteristics
Parameter Lock time
(1)
Test condition @3.3V and Tj = 125C
Min.
Typ.
Max. 3
Unit ms MHz
Fvco
VCO frequency (2)
70
140
1. Depending on VCO output frequency. 2. Fdsp = Fvco/2 when PLL is running
8/25
TDA7502 Table 7.
Symbol Fosc
Electrical specifications Oscillator characteristics
Parameter Max oscillator frequency (XTI) Test condition @ 3.3V and Tj = 125C Min. 8 Typ. Max. 12.5 Unit MHz
Table 8.
Symbol l il l ih Ioz
General interface electrical characteristics
Parameter Low level input current without pullup device High level input current without pullup device Tri-state output leakage without pull up/down device 5V tolerant tri-state output leakage without pull up/down device I/O latch-up current Electrostatic protection Test Condition Vi = 0V (1) Vi = Vdd (1) Vo = 0V or Vdd (1) Vo = 0V or Vdd (1) Vo = 5.5V V < 0V, V > Vdd Leakage , 1A
(2)
Min.
Typ.
Max. 1 1 1 1
Unit A A A A A mA V
IozFT Ilatchup Vesd
1 200 1500
3
1. The leakage currents are generally very small, <1nA. The value given here, 1mA, ia amaximum that can occur after an electrostatic stress on the pin. 2. Human body model.
Table 9.
Symbol Vil Vih Vilhyst Vihhyst Vhyst Vol Voh
Low voltage TTL interface DC electrical characteristics
Parameter Low level input voltage High level input voltage Low level threshold input falling Low level threshold input falling Schmitt trigger hysteresis Low level output voltage High level output voltage
(1) (1) (1) (1) (1)
Test condition
Min.
Typ.
Max. 0.8
Unit V V
2 0.9 1.3 0.4 1.35 1.9 0.7 0.4 2.4
V V V V V
Iol = XmA (1) (2) (3)
1. TTL specifications only apply to the supply voltage range Vdd = 3.0V to 3.6V. 2. Takes into account 200mV voltage drop in both supply lines. 3. X is the source/sink current under worst case conditions and is reflected in the name of the I/O cell according to the drive capability.
Table 10.
Symbol F dsp
DSP core
Parameter Maximum DSP clock frequency Test condition @3.15V and Tj = 125C Min. 50 Typ. Max. Unit MHz
9/25
Electrical specifications Figure 3.
TDA7502
Maximum DSP clock frequency (Fdsp) versus junction temperature (Tj)
MHz
92
Vdd = 3.3V
80
67
50
-40
25
125
Temp
MHz
88
Vdd = 3.15V
78
65
50
-40
25
125
Temp
MHz
93
Vdd = 3.45V
83
69
50
-40
25
125
Temp
10/25
TDA7502
SAI interface
3
SAI interface
Figure 4.
SDI0-3
SAI timings
VALID
LRCKR
VALID
tlrh SCKR (RCKP=0) tsckpl tlrs tdt tsdis tsckr
D02AU1357
tsckph tsdih
Table 11.
Timing tsckr tdt tlrs tlrh tsdid tsdih tsckph tsckpl
Cycles
Description Minimum Clock Cycle SCKR active edge to data out valid LRCK setup time LRCK hold time SDI setup time SDI hold time Minimum SCK high time Minimum SCK low time Value 4TDSP 10 5 5 15 15 0.35 tsckr 0.35 tsckr Unit ns ns ns ns ns ns ns ns
Note: TDSP = dsp master clock cycle time = 1/FDSP
Figure 5.
SAI protocol when RLRS=0; RREL=0; RCKP=1; RDIR=0
LRCKR (#23)
LEFT
RIGHT
SCKR (#24)
SDI0,1,2 (#20, #21, #22)
LSB(n-1)
MSB(word n)
MSB-1 (n)
MSB-2 (n)
D02AU1358
11/25
SAI interface Figure 6. SAI protocol when RLRS=1; RREL=0; RCKP=1; RDIR=1.
TDA7502
LRCKR (#23)
LEFT
RIGHT
SCKR (#24)
SDI0,1,2 (#20, #21, #22)
MSB(n-1)
LSB(word n)
LSB+1 (n)
LSB+2 (n)
D02AU1359
Figure 7.
SAI protocol when RLRS=0; RREL=0; RCKP=0; RDIR=0.
LEFT RIGHT
LRCKR (#23)
SCKR (#24)
SDI0,1,2 (#20, #21, #22)
LSB(n-1)
MSB(word n)
MSB-1 (n)
MSB-2 (n)
D02AU1360
Figure 8.
SAI protocol when RLRS=0; RREL=1; RCKP=1; RDIR=0.
LEFT RIGHT
LRCKR (#23)
SCKR (#24)
SDI0,1,2 (#20, #21, #22)
LSB(n-1)
MSB(word n)
MSB-1 (n)
MSB-2 (n)
D02AU1361
12/25
TDA7502
SPI interfaces
4
SPI interfaces
Table 12.
Symbol Master tsclk tdtr Clock cycle Sclk edge to MOSI valid 12TDSP 40 16 4 0.5tsclk 0.5tsclk ns ns ns ns ns ns
SPI interfaces
Description Min Value Unit
tmisosetup MISO setup time tmisohold tsclkh tsclkl Slave
tsclk t dtr tmosisetup tmosihold tsclkh tsclkl
MISO hold time SCK high time SCK high low
Clock cycle Sclk edge to MOSI valid MOSI setup time MOSI hold time SCK high time SCK high low
12TDSP 40 16 4 0.5tsclk 0.5tsclk
ns ns ns ns ns ns
Figure 9.
SPI clocking scheme.
SS (#37)
SCK (#36)
(CPOL=0, CPHA=0)
SCK (#36)
(CPOL=0, CPHA=1)
SCK (#36)
(CPOL=1, CPHA=0)
SCK (#36)
(CPOL=1, CPHA=1)
MSB
6
5
4
3
2
1
LSB
MISO, MOSI (#38, #39)
In master mode it is only supported CPHA = 0.
INTERNAL STROBE FOR INTERNAL CAPTURE
D02AU1362
13/25
SPI interfaces Table 13.
No. 1 2 3 4 5 6 7 8 9 10 DBCK rise time DBCK fall time DBCK low DBCK high DBCK cycle time DBRQN asserted to DBOUT (ACK) asserted DBCK high to DBOUT valid DBCK high to DBOUT invalid DBIN valid to DBCK low (set-up) DBCK low to DBIN invalid (hold) DBOUT (ACK) asserted to first DBCK high DBOUT (ACK) assertion width 11 12 Last DBCK low of read register to first DBCK high of next command Last DBCK low to DBOUT invalid (Hold) DBSEL setup to DBCK
TDA7502 Debug port interface
dclk = 40MHz Characteristics Min. --40 40 200 5 TDSP -3 15 3 2 Tc 4.5 TDSP - 3 7 TDSP + 10 3 TDSP Max. 3 3 ----42 ----5 TDSP + 7 --ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Figure 10. Debug port serial clock timing.
(1) (3) (2)
DBCK (input)
(5)
(4)
D02AU1363
Figure 11. Debug port acknowledge timing.
DBRQN (input)
(6)
DBOUT (output)
D02AU1364
(ACK)
14/25
TDA7502 Figure 12. Debug port data I/O to status timing.
DBCK (input) DBOUT (output) (9) DBIN (input)
(Note 1) Note: 1 High Impedance, external pull-down resistor
SPI interfaces
(Last)
(10)
D02AU1365
Figure 13. Debug port read timing.
DBCK (input) (7) DBOUT (output)
Note: 1 High Impedance, external pull-down resistor
(Last)
(Note 1)
(8)
(12)
D02AU1369
Figure 14. Debug port DBCK next command after read register timing.
DBCK (input)
(NEXT COMMAND)
(11)
D02AU1370
15/25
I2C timing
TDA7502
5
I2C timing
Figure 15. Definition of timing for the I2C bus.
SDA tBUF tLOW tSU:STA tF
SCL tHD:STA tR tHD:DAT tHIGH tSU:DAT tHD:STA tSU:STO
D02AU1371
Table 14.
Definitions
Standard mode I2C bus Min. Max. 100 Fast mode I2C bus Min. 0 1.3 Max. 400 kHz s
Symbol
Parameter
Test condition
Unit
FSCL tBUF
SCLl clock frequency Bus free between a STOP and Start Condition
0 4.7
Hold time (repeated) START condition. tHD:STA After this period, the first clock pulse is generated tLOW tHIGH tSU:STA LOW period of the SCL clock HIGH period of the SCL clock Set-up time for a repeated start condition
4.0 4.7 4.0 4.7 0 Cb in pF Cb in pF 4 250
1000 300 -400
0.6 1.3 0.6 0.6 0 20+0.1Cb 20+0.1Cb 0.6 -
0.9 300 300 100 400
s s s s s ns ns s ns pF
tHD:DAT DATA hold time tR tF Rise time of both SDA and SCL signals Fall time of both SDA and SCL signals
tSU;STO Set-up time for STOP condition tSU:DAT Cb Data set-up time Capacitive load for each bus line
16/25
TDA7502
Functional description
6
Functional description
The TDA7502 contains one DSP core and associated peripherals.
6.1
24-BIT DSP core.
The DSP core is used to process the converted analog audio data coming from the CODEC chip via the SAI and return it for analog conversion. Functions such as volume, tone, balance, and fader control, as well as spatial enhancement and general purpose signal processing may be performed by the DSP. Some capabilities of the DSPs are listed below: Single cycle multiply and accumulate with convergent rounding and condition code generation
2 x 56-bit accumulators. Double precision multiply. Scaling and saturation arithmetic. 48-bit or 2 x 24-bit parallel moves. 64 interrupt vector locations. Fast or long interrupts possible. Programmable interrupt priorities and masking. 8 each of address registers, address offset registers and address modulo registers. linear, reverse carry, multiple buffer modulo, multiple wrap-around modulo address arithmetic. Post-increment or decrement by 1 or by offset, index by offset, predecrement address. Repeat instruction and zero overhead DO loops. Hardware stack capable of nesting combinations of 7 DO loops or 15 interrupts/subroutines. Bit manipulation instructions possible on all registers and memory locations. Also jump on bit test.. 4 pin serial debug interface. Debug access to all internal registers, buses and memory locations. 5 word deep program address history FIFO. Hardware and software breakpoints for both program and data memory accesses. Debug single stepping, Instruction injection and disassembly of program memory.
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Functional description
TDA7502
6.2
DSP peripherals
There are a number of peripherals that are tightly coupled to the DSP Core. Each of the peripherals are listed below and described in the following sections.
1024 x 24-Bit X-RAM. 1024 x 24-Bit Y-RAM. 3072 x 24-Bit program RAM. 512 x 24-Bit Boot ROM. Serial audio interface (SAI). Programmable control interface (SPI/I2C). GPIO. PLL clock oscillator.
6.3
Data and program memory
Each of the memories are described below.
6.3.1
1024 x 24-Bit X-RAM (XRAM)
This is a 1024 x 24-Bit single port SRAM used for storing coefficients. The 16-Bit XRAM address, XABx(15:0) is generated by the address generation unit of the DSP core. The 24Bit XRAM Data, XDBx(23:0), may be written to and read from the data ALU of the DSP core. The XDBx Bus is also connected to the internal bus switch so that it can be routed to and from all peripheral blocks.
6.3.2
1024 x 24 Bit Y-RAM (YRAM)
This is a 1024 x 24-Bit single port SRAM used for storing coefficients. The 16-Bit address, YABx(15:0) is generated by the address generation unit of the DSP core. The 24-Bit Data, YDBx(23:0), is written to and read from the Data ALU of the DSP core. The YDBx Bus is also connected to the internal bus switch so that it can be routed to and from other blocks.
6.3.3
3072 X 24-Bit Program RAM
This is a 3072 x 24-Bit single port SRAM used for storing and executing program code. The 16-Bit PRAM Address, PABx(15:0) is generated by the program address generator of the DSP core for instruction fetching, and by the AGU in the case of the move program memory (MOVEM) instruction. The 24-Bit PRAM Data (program code), PDBx(23:0), can only be written to using the MOVEM instruction. During instruction fetching the PDBx bus is routed to the program decode controller of the DSP core for instruction decoding. Spare space in the program area may be used as data memory to implement delay lines for example.
6.3.4
512 x 24-Bit Bootstrap ROM (Boot ROM)
This is a 512 x 24-Bit factory programmed Boot ROM used for storing the program sequence for initializing the DSP.
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TDA7502
Functional description Essentially this consists of a routine that is called when the DSP comes out of reset. There are four different boot modes supported by the boot ROM. The first mode loads the application program via SPI interface where Casper's SPI is in master mode. The second boot mode enables the debug port and waits. The third and fourth modes load the application program via the I2C interface, one with Casper's I2C Interface configured in slave mode and the other in master mode. Which boot mode to enter is configured by sampling the states of the GPIO4 and GPIO3 pins at reset as shown in the table below. Table 15. Casper IC boot modes
Description load PRAM, XRAM and YRAM from SPI enable Debug Port load PRAM, XRAM and YRAM from oad PRAM, XRAM and YRAM from I2C I2C GPIO3 0 0 1 1 GPIO4 0 1 0 1
Modes 0-SPI Master 1-Debug 2-I
2C
Master Slave
3-I
2C
6.3.5
Serial audio interface (SAI)
The SAI is used to deliver digital audio to the DSPs from an external source. Once processed by the DSPs, it can be returned through this interface. The features of the SAI are listed below.
Three synchronized stereo data transmission lines Three synchronized stereo data reception lines Master/Slave operating modes Transmit and receive interrupt logic triggers on left/right data pairs Receive and transmit data registers have two locations to hold left and right data.
6.3.6
Serial peripheral interface
A serial interface allows to receive commands and data over the LAN. During an SPI transfer, data is transmitted and received simultaneously. Both master and slave modes are supported. In master mode the SPI supports combination of CPOL =0/1 and CPHA =0 only, while in slave mode all the 4 possible combinations of CPOL and CPHA are supported. See Figure 9. A serial clock line synchronizes shifting and sampling of the information on the two serial data lines. A slave select line allows individual selection of a slave SPI device. When an SPI transfer occurs an 8-bit word is shifted out one data pin while another 8-bit character is simultaneously shifted in a second data pin.The central element in the SPI system is the shift register and the read data buffer. The system is single buffered in the transfer direction and double buffered in the receive direction.
6.3.7
I2C interface
The inter integrated circuit bus is a single bidirectional two-wire bus used for efficient inter IC control. All I2C bus compatible devices incorporate an on-chip interface which allows them communicate directly with each other via the I2C bus.
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Functional description
TDA7502
Every component hooked up to the I2C bus has its own unique address whether it is a CPU, memory or some other complex function chip. Each of these chips can act as a receiver and /or transmitter on its functionality.
6.3.8
General purpose input/output
The DSP requires a set of external general purpose input/output lines, and a reset line. These signals are used by external devices to signal events to the DSP. The GPIO lines are implemented as DSP's peripherals.
6.3.9
PLL clock oscillator
The PLL clock oscillator can accept an external clock at XTI or it can be configured to run an internal oscillator when a crystal is connected across pins XTI & XTO. There is an input divide block IDF (1 -> 32) at the XTI clock input and a multiply block MF (9 -> 128) in the PLL loop. Hence the PLL can multiply the external input clock by a ratio MF/IDF to generate the internal clock. This allows the internal clock to be within 2 MHz of any desired frequency even when XTI is much greater than 1 MHz. It is recommended that the input clock is not divided down to less than 1 MHz as this reduces the phase detector's update rate. The clocks to the DSP can be selected to be either the VCO output divided by 2 to 16, or be driven by the XTI pin directly. The crystal oscillator and the PLL will be gated off when entering the power-down mode (by setting a register on DSP0).
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7
TDA7502
THE HW INSIDE DASHED LINE BOX IS A POSSIBLE SOLUTION TO BOOT STRAP AND TO INTERFACE TP A PC.
CONFIGURING THE PINS TO J1 OF THE CONNECTOR AS DESCRIBED IN THE FIGURE YOU CAN USE THE PC_INTERFACE AND THEN DOWNLOAD DSP SW PROGRAM INTO EEPROM OR DIRECTLY INTO THE CHIP MEMORY. P DGND_1 DGND_6 3V3_6 BOOT MODE SELECTION 3V3_6 DGND_6 3V3_6 DGND_6 10K INT SCANEN GND6 41 43 GPIO3 10K GPIO4 2 10K 2 40 VDD6 3 4 5 2 1 8 42 6 7 44 39 38 36 37 9 SS SDA SCL 10K 47R 47R 5V 14 15 16 17 18 19 20 SDI0 SDI1 SDI2 21 22 23 24 25 26 27 28 29 30 31 32 33 M24256-WMW6 WC SCL VDD5 SDO2 GND5 SCKT SDA 3V3_4 DGND_4
D02AU1383
3V3_1
BOOT MODE SELECTION GPIO3 GPIO4 SPI-MASTER DEBUG-MODE I2C-MASTER I2C-SLAVE 0 0 1 1 0 1 0 1
GND1
TESTEN
VDD1
1
3
1
3
3V3_2
VDD2
Application scheme
10K GPIO5 MISO MOSI SCK
10K
DBRON
DBOUT
GPI/0
DEBUG INTERFACE 10 11
GPI/O
DBCK
DBIN
10K
10K
DGND_2
GND2
Figure 16. Application schematic for TDA7502
TDA7502
34
35
I2C/SPI INTERFACE
10K 3V3_6
1 12 13
CLKOUT
CLK-OUT FROM PLL 2
PGND
J1 1 SCK/EN SDA READY 3 5 7 9 2 4 6 8 10 DGND_6
PGND
3V3_P
PVCC
XTO
24M576Hz
XTI
P
RESET
15pF
2.2M 15pF
3V3_3
VDD3
DGND_3
GND3
DGND_6 7 6 5 32 x 8 I2C 1,2,3 8 4 N.C. VCC VSS 3V3_6 DGND_6 LRCKT 0.1F
PGND VDD4 SDO0 SCKR LRCKR GND4 SDO1
3V3_4 DGND_4 SAI INTERFACE MASTER/SLAVE
NOT USED PINS TO BE CONNECTED TO GROUND
Application scheme
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Application scheme Figure 17. Block diagram of car amplifier audio sub-system.
TDA7502
EPROM (64Kx8)
To Microprocessor
Control Bus
POWER AMPLIFIER DIGITAL AUDIO
TDA7502
TDA7535
D99AU1036
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TDA7502
Package information
8
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 18. TQFP44 (10x10) mechanical data & package dimensions
mm DIM. MIN. A A1 A2 B C D D1 D3 E E1 E3 e L L1 k ccc 0.45 11.80 9.80 0.05 1.35 0.30 0.09 11.80 9.80 12.00 10.00 8 .0 0 12.00 10.00 8 .0 0 0.80 0.60 1.00 0.75 0.018 12.20 10.20 0.464 0.386 1 .4 0 0.37 TYP. M AX . 1.60 0.15 1.45 0.45 0.20 12.20 10.20 0.002 0.053 0.012 0.004 0.464 0.386 0.472 0.394 0.315 0.472 0.394 0.315 0.031 0.024 0.039 0.030 0.480 0.401 0.055 0.015 MIN. TYP. MAX. 0.063 0.006 0.057 0.018 0.008 0.480 0.401 inch
OUTLINE AND MECHANICAL DATA
0 (min.), 3.5(typ.), 7(max.) 0.10 0.0039
LQFP44 (10 x 10 x 1.4mm)
0076922 E
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Revision history
TDA7502
9
Revision history
Table 16.
Date January 2004 September 2004 March 2005 24-Nov-2006
Revision history
Revision 8 9 10 11 Description of changes First Issue in EDOCS dms. Changed the style-sheet look. Cancelled the "Package Marking" information. Changed SPI interface description and Figure 4. Package changed, layout changes, text modifications.
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TDA7502
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