M48T212V
3.3V TIMEKEEPER supervisor
Features
Integrated real-time clock, power-fail control circuit, battery and crystal Converts low power SRAM into NVRAMs Year 2000 compliant (4-digit year) Battery low flag Microprocessor power-on reset Programmable alarm output active in the battery backed-up mode Watchdog timer Automatic power-fail chip deselect and WRITE protection WRITE protect voltage (VPFD = Power-fail deselect voltage): M48T212V: VCC = 3.0 to 3.6V 2.7V VPFD 3.0V Packaging includes a 44-lead SOIC and SNAPHAT top (to be ordered separately) RoHS compliant Lead-free second level interconnect
SNAPHAT (SH) Crystal/battery
44 1
SOH44 (MH)
November 2007
Rev 7
1/35
www.st.com 1
Contents
M48T212V
Contents
1 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 2.2 2.3 2.4 Address decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3
Clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 TIMEKEEPER registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Reading the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Setting the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Stopping and starting the oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Setting the alarm clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 VCC switch output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Reset inputs (RSTIN1 & RSTIN2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Calibrating the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Battery low warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Initial power-on defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 VCC noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . 25
4 5 6 7 8
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
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M48T212V
List of tables
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Truth table for SRAM bank select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Chip enable control and bank select characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Read mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Write mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 TIMEKEEPER register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Alarm repeat modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Reset AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Default values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 DC and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Power down/up mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 SOH44 44-lead plastic small outline, SNAPHAT, pack. mech. data . . . . . . . . . . . . . . . . 30 SH 4-pin SNAPHAT housing for 48 mAh battery & crystal, pack. mech. data. . . . . . . . . 31 SH 4-pin SNAPHAT housing for 120mAh battery & crystal, pack. mech. data . . . . . . . . 32 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 SNAPHAT battery table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
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List of figures
M48T212V
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 SOIC connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Chip enable control and bank select timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Read cycle timing: RTC control signal waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Write cycle timing: RTC control signal waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Alarm interrupt reset waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Back-up mode alarm waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 (RSTIN1 & RSTIN2) timing waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Calibration waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 AC testing load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 SOH44 44-lead plastic small outline, SNAPHAT, package outline . . . . . . . . . . . . . . . . . 30 SH 4-pin SNAPHAT housing for 48 mAh battery & crystal, package outline. . . . . . . . . . 31 SH 4-pin SNAPHAT housing for 120mAh battery & crystal, package outline . . . . . . . . . 32
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M48T212V
Description
1
Description
The M48T212V is a self-contained device that includes a real-time clock (RTC), programmable alarms, a watchdog timer, and two external chip enable outputs which provide control of up to four (two in parallel) external low-power static RAMs. Access to all TIMEKEEPER functions and the external RAM is the same as conventional byte-wide SRAM. The 16 TIMEKEEPER Registers offer Century, Year, Month, Date, Day, Hour, Minute, Second, Calibration, Alarm, Watchdog, and Flags. Externally attached static RAMs are controlled by the M48T212V via the E1CON and E2CON signals (see Table 3 on page 10). The 44-pin, 330mil SOIC provides sockets with gold plated contacts at both ends for direct connection to a separate SNAPHAT housing containing the battery and crystal. The unique design allows the SNAPHAT battery package to be mounted on top of the SOIC package after the completion of the surface mount process. Inser tion of the SNAPHAT housing after reflow prevents potential battery and crystal damage due to the high temperatures required for device surface-mounting. The SNAPHAT housing is keyed to prevent reverse insertion. The SOIC and battery/crystal packages are shipped separately in plastic anti-static tubes or in Tape & Reel form. For the-44 lead SOIC, the battery/crystal package (e.g., SNAPHAT) part number is "M4TXX-BR12SH" (see Table 20 on page 33).
Caution:
Do not place the SNAPHAT battery/crystal top in conductive foam, as this will drain the lithium button-cell battery. Figure 1. Logic diagram
VCC VCCSW
4 A0-A3 A E EX W G WDI RSTIN1 RSTIN2 M48T212V
8 DQ0-DQ7
IRQ/FT RST E1CON E2CON
VOUT
VSS
AI03019
5/35
Description Table 1. Signal names
A0-A3 DQ0-DQ7 RSTIN1 RSTIN2 RST WDI A E EX G W E1CON E2CON IRQ/FT VCCSW VOUT VCC VSS NC Address inputs Data inputs/outputs Reset 1 input Reset 2 input Reset output (open drain) Watchdog input Bank select input Chip enable input External chip enable input Output enable input WRITE enable input RAM chip enable 1 output RAM chip enable 2 output Int/freq test output (open drain) VCC switch output Supply voltage output Supply voltage Ground Not connected internally
M48T212V
6/35
M48T212V Figure 2. SOIC connections
RSTIN1 RSTIN2 RST NC NC NC NC NC A NC NC NC A3 A2 A1 A0 WDI E2CON DQ0 DQ1 DQ2 VSS 1 2 3 4 5 6 7 8 9 10 11 M48T212V 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 VCC VOUT VCCSW IRQ/FT EX NC NC NC NC NC G W NC NC E E1CON DQ7 DQ6 DQ5 DQ4 DQ3 NC
Description
AI03020
7/35
Description Figure 3. Hardware hookup
M48T212V
A0-A18
5V/3.3V
A0-A3 VCC 1N5817(1) A E EX W G E2CON WDI RSTIN1 RSTIN2 DQ0-DQ7 VSS M48T212V RST IRQ/FT E1CON Note 2 VCCSW
MOTOROLA MTD20P06HDL
A0-Axx VOUT VCC E2(3) E CMOS SRAM
A0-Axx VCC E2(3) E CMOS SRAM
AI03046
1. Traces connecting E1CON and E2CON to external SRAM should be as short as possible. 2. If the second chip enable pin (E2) is unused, it should be tied to VOUT.
Note:
See description in Power Supply Decoupling and Undershoot Protection.
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M48T212V
Operation
2
Operation
Automatic backup and write protection for an external SRAM is provided through VOUT, E1CON and E2CON pins. (Users are urged to ensure that voltage specifications, for both the SUPERVISOR chip and external SRAM chosen, are similar). The SNAPHAT containing the lithium energy source used to permanently power the real-time clock is also used to retain RAM data in the absence of VCC power through the VOUT pin. The chip enable outputs to RAM (E1CON and E2CON) are controlled during power transients to prevent data corruption. The date is automatically adjusted for months with less than 31 days and corrects for leap years (valid until 2100). The internal watchdog timer provides programmable alarm windows. The nine clock bytes (Fh-9h and 1h) are not the actual clock counters, they are memory locations consisting of BiPORTTM READ/WRITE memory cells within the static RAM array. Clock circuitry updates the clock bytes with current information once per second. The information can be accessed by the user in the same manner as any other location in the static memory array. Byte 8h is the clock control register. This byte controls user access to the clock information and also stores the clock calibration setting. Byte 7h contains the watchdog timer setting. The watchdog timer can generate either a reset or an interrupt, depending on the state of the Watchdog Steering Bit (WDS). Bytes 6h-2h include bits that, when programmed, provide for clock alarm functionality. Alarms are activated when the register content matches the month, date, hours, minutes, and seconds of the clock registers. Byte 1h contains century information. Byte 0h contains additional flag information pertaining to the watchdog timer, alarm and battery status. The M48T212V also has its own Power-Fail Detect circuit. This control circuitry constantly monitors the supply voltage for an out of tolerance condition. When VCC is out of tolerance, the circuit write protects the TIMEKEEPER register data and external SRAM, providing data security in the midst of unpredictable system operation. As VCC falls below VSO, the control circuitry automatically switches to the battery, maintaining data and clock operation until valid power is restored.
2.1
Address decoding
The M48T212YV accommodates 4 address lines (A3-A0) which allow access to the sixteen bytes of the TIMEKEEPER clock registers. All TIMEKEEPER registers reside in the SUPERVISOR chip itself. All TIMEKEEPER registers are accessed by enabling E (Chip Enable).
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Operation Table 2.
Mode Deselect WRITE READ READ Deselect Deselect VSO to VPFD (min) VSO(1)
(1)
M48T212V Operating modes
VCC E VIH 3.0V to 3.6V VIL VIL VIL X X G X X VIL VIH X X W X VIL VIH VIH X X DQ7-DQ0 High-Z DIN DOUT High-Z High-Z High-Z Power Standby Active Active Active CMOS standby Battery back-up
1. See Table 14 on page 28 for details.
Note: Table 3.
Mode Select Deselect Deselect Deselect
X = VIH or VIL; VSO = Battery back-up switchover voltage Truth table for SRAM bank select
VCC 3.0V to 3.6V VSO to VPFD (min)(1)( VSO(1) EX Low Low High X X A Low High X X X E1CON Low High High High High E2CON High Low High High High Power Active Active Standby CMOS standby Batter y back-up
1. See Table 14 on page 28 for details.
Note: Figure 4.
X = VIH or VIL; VSO = Battery back-up switchover voltage Chip enable control and bank select timing
EX tEXPD A tEXPD E1CON tAPD
E2CON
AI02639
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M48T212V Table 4. Chip enable control and bank select characteristics
M48T212V Symbol Parameter Min tEXPD tAPD EX to E1CON or E2CON (low or high) A to E1CON or E2CON (low or high) 85 Max 15 15
Operation
Unit
ns ns
2.2
Read mode
The M48T212V executes a READ cycle whenever W (WRITE Enable) is high and E (Chip Enable) is low. The unique address specified by the address inputs (A3-A0) defines which one of the on-chip TIMEKEEPER registers is to be accessed. When the address presented to the M48T212V is in the range of 0h-Fh, one of the on-board TIMEKEEPER registers is accessed and valid data will be available to the eight data output drivers within tAVQV after the address input signal is stable, providing that the E and G access times are also satisfied.If they are not, then data access must be measured from the latter occurring signal (E or G) and the limiting parameter is either tELQV for E or tGLQV for G rather than the address access time. When EX input is low, an external SRAM location will be selected.
Note:
Care should be taken to avoid taking both E and EX low simultaneously to avoid bus contention. Read cycle timing: RTC control signal waveforms
READ tAVAV ADDRESS tELQV E tELQX G tGLQV tWLWH W tAVQV tAVWL tWHAX READ tAVAV WRITE tAVAV
Figure 5.
tGLQX
tAXQX tGHQZ
DQ7-DQ0
DATA OUT VALID
DATA OUT VALID
DATA IN VALID
AI02640
Note:
EX is assumed high.
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Operation Table 5. Read mode AC characteristics
M48T212V Symbol Parameter(1) Min tAVAV tAVQV tELQV tGLQV tELQX(2) tGLQX(2) tEHQZ(2) tGHQZ(2) tAXQX
2. CL = 5pF.
M48T212V
85 Max
Unit
Read cycle time Address valid to output valid Chip enable low to output valid Output enable low to output valid Chip enable low to output transition Output enable low to output transition Chip enable high to output Hi-Z Output enable high to output Hi-Z Address transition to output transition
85 85 85 35 5 0 25 25 5
ns ns ns ns ns ns ns ns ns
1. Valid for ambient operating temperature: TA = 0 to 70C; VCC = 3.0 to 3.6V (except where noted).
2.3
Write mode
The M48T212V is in the WRITE Mode whenever W (WRITE Enable) and E (Chip Enable) are in a low state after the address inputs are stable. The start of a WRITE is referenced from the latter occurring falling edge of W or E. A WRITE is terminated by the earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W must return high for a minimum of tEHAX from Chip Enable or tWHAX from WRITE Enable prior to the initiation of another READ or WRITE cycle. Data-in must be valid tDVWH prior to the end of WRITE and remain valid for tWHDX afterward. G should be kept high during WRITE cycles to avoid bus contention; although, if the output bus has been activated by a low on E and G a low on W will disable the outputs tWLQZ after W falls. When E is low during the WRITE, one of the on-board TIMEKEEPER registers will be selected and data will be written into the device. When EX is low (and E is high) an external SRAM location is selected.
Note:
Care should be taken to avoid taking both E and EX low simultaneously to avoid bus contention.
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M48T212V Figure 6. Write cycle timing: RTC control signal waveforms
WRITE tAVAV ADDRESS tAVEH tAVEL E tGLQV G tEHDX tAVWL W tEHQZ DQ0-DQ7
DATA OUT VALID
Operation
WRITE tAVAV
READ tAVAV
tAVWH tEHAX tWHAX tAVQV
tELEH
tWLWH
tWHQX
tWLQZ
tDVEH
DATA IN VALID
tDVWH
DATA IN VALID
tWHDX
DATA OUT VALID
AI02641
Note:
EX is assumed high.
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Operation Table 6. Write mode AC characteristics
M48T212V Symbol Parameter(1) Min tAVAV tAVWL tAVEL tWLWH t ELEH tWHAX tEHAX tDVWH tDVEH tWHDX tEHDX tWLQZ(2)(3) tAVWH tAVEH tWHQX(2)(3)
2. CL = 5pF 3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
M48T212V
85 Max
Unit
Write cycle time Address valid to write enable low Address valid to chip enable low Write enable pulse width Chip enable low to chip enable high Write enable high to address transition Chip enable high to address transition Input valid to write enable high Input valid to chip enable high Write enable high to input transition Chip enable high to input transition Write enable low to output High-Z Address valid to write enable high Address valid to chip enable high Write enable high to output transition
85 0 0 55 60 0 0 30 30 0 0 25 65 65 5
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
1. Valid for ambient operating temperature: TA = 0 to 70C; VCC = 3.0 to 3.6V (except where noted).
2.4
Data retention mode
With valid VCC applied, the M48T212V can be accessed as described above with READ or WRITE cycles. Should the supply voltage decay, the M48T212V will automatically deselect, write protecting itself (and any external SRAM) when VCC falls between VPFD (max) and VPFD (min). This is accomplished by internally inhibiting access to the clock registers via the E signal. At this time, the Reset pin (RST) is driven active and will remain active until VCC returns to nominal levels. External RAM access is inhibited in a similar manner by forcing E1CON and E2CON to a high level. This level is within 0.2 volts of the VBAT. E1CON and E2CON will remain at this level as long as VCC remains at an out-of-tolerance condition. When VCC falls below battery back-up switchover voltage (VSO), power input is switched from the VCC pin to the SNAPHAT battery and the clock registers and external SRAM are maintained from the attached battery supply. All outputs become high impedance. The VOUT pin is capable of supplying 100A of current to the attached memory with less than 0.3V drop under this condition. On power up, when VCC returns to a nominal value, write protection continues for 200ms (max) by inhibiting E1CON or E2CON. The RST signal also remains active during this time (see Figure 14 on page 29).
Note:
Most low power SRAMs on the market today can be used with the M48T212V TIMEKEEPER SUPERVISOR. There are, however some criteria which should be used in
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M48T212V
Operation making the final choice of an SRAM to use. The SRAM must be designed in a way where the chip enable input disables all other inputs to the SRAM. This allows inputs to the M48T212V and SRAMs to be "Don't care" once VCC falls below VPFD(min). The SRAM should also guarantee data retention down to VCC = 2.0V. The chip enable access time must be sufficient to meet the system needs with the chip enable output propagation delays included. If the SRAM includes a second chip enable pin (E2), this pin should be tied to VOUT. If data retention lifetime is a critical parameter for the system, it is important to review the data retention current specifications for the particular SRAMs being evaluated. Most SRAMs specify a data retention current at 3.0V. Manufacturers generally specify a typical condition for room temperature along with a worst case condition (generally at elevated temperatures). The system level requirements will determine the choice of which value to use. The data retention current value of the SRAMs can then be added to the IBAT value of the M48T212V to determine the total current requirements for data retention. The available battery capacity for the SNAPHAT of your choice can then be divided by this current to determine the amount of data retention available (see Table 20 on page 33). For a further more detailed review of lifetime calculations, please see Application Note AN1012.
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Clock operation
M48T212V
3
3.1
Clock operation
TIMEKEEPER registers
The M48T212V offers 16 internal registers which contain TIMEKEEPER, Alarm, Watchdog, Flag, and Control data. These registers are memory locations which contain external (user accessible) and internal copies of the data (usually referred to as BiPORTTM TIMEKEEPER cells). The external copies are independent of internal functions except that they are updated periodically by the simultaneous transfer of the incremented internal copy. TIMEKEEPER and Alarm Registers store data in BCD. Control, Watchdog and Flags Registers store data in Binary Format.
3.2
Reading the clock
Updates to the TIMEKEEPER registers should be halted before clock data is read to prevent reading data in transition. The BiPORT TIMEKEEPER cells in the RAM array are only data registers and not the actual clock counters, so updating the registers can be halted without disturbing the clock itself. Updating is halted when a '1' is written to the READ Bit, D6 in the Control Register (8h). As long as a '1' remains in that position, updating is halted. After a halt is issued, the registers reflect the count; that is, the day, date, and time that were current at the moment the halt command was issued. All of the TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an update in progress. Updating occurs 1 second after the READ Bit is reset to a '0.'
3.3
Setting the clock
Bit D7 of the Control Register (8h) is the WRITE Bit. Setting the WRITE Bit to a '1,' like the READ Bit, halts updates to the TIMEKEEPER registers. The user can then load them with the correct day, date, and time data in 24 hour BCD format (see Table 7 on page 18). Resetting the WRITE Bit to a '0' then transfers the values of all time registers (Fh-9h, 1h) to the actual TIMEKEEPER counters and allows normal operation to resume. After the WRITE Bit is reset, the next clock update will occur one second later.
Note:
Upon power-up following a power failure, the READ Bit will automatically be set to a '1.' This will prevent the clock from updating the TIMEKEEPER registers, and will allow the user to read the exact time of the power-down event. Resetting the READ Bit to a '0' will allow the clock to update these registers with the current time. The WRITE Bit will be reset to a '0' upon power-up.
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M48T212V
Clock operation
3.4
Stopping and starting the oscillator
The oscillator may be stopped at any time. If the device is going to spend a significant amount of time on the shelf, the oscillator can be turned off to minimize current drain on the battery. The STOP Bit is located at Bit D7 within the Seconds Register (9h). Setting it to a '1' stops the oscillator. When reset to a '0,' the M48T212V oscillator starts within one second.
No te :
It is not necessary to set the WRITE Bit when setting or resetting the FREQUENCY TEST Bit (FT) or the STOP Bit (ST).
17/35
Clock operation Table 7.
Address D7 Fh Eh Dh Ch Bh Ah 9h 8h 7h 6h 5h 4h 3h 2h 1h 0h WDF 0 0 0 0 0 ST W WDS AFE RPT4 RPT3 RPT2 RPT1 R 0 0 FT 0 0 D6 D5 D4 D3 D2 Year 10M 10 date 0 10 hours 10 minutes 10 seconds S BMB2 Al 10M 0 Month Date: Day of month Day of week Hours (24 hour format) Minutes Seconds Calibration BMB1 BMB0 RB1 RB0 D1 D0 10 Years 0
M48T212V TIMEKEEPER register map
Function/range BCD format Year Month Date Day Hours Min Sec Control Watchdog A month A date A hour A min A sec Centur y Y Flag 01-12 01-31 00-23 00-59 00-59 00-99 00-99 01-12 01-31 01-7 00-23 00-59 00-59
BMB4 BMB3 0 RPT5 0 ABE
Alarm month Alarm date Alarm hour Alarm minutes Alarm seconds 100 year
AI 10 date AI 10 hour
Alarm 10 minutes Alarm 10 seconds 1000 year AF Y BL Y
Y
Y
Keys: S = Sign bit FT = Frequency test bit R = READ bit W = WRITE bit ST = Stop bit 0 = Must be set to '0' BL = Battery low flag (read only) BMB0-BMB4 = Watchdog multiplier bits AFE = Alarm flag enable flag RB0-RB1 = Watchdog resolution bits WDS = Watchdog steering bit ABE = Alarm in battery back-up mode enable bit RPT1-RPT5 = Alarm repeat mode bits WDF = Watchdog flag (read only) AF = Alarm flag (read only) Y = '1' or '0'
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M48T212V
Clock operation
3.5
Setting the alarm clock
Address locations 6h-2h contain the alarm settings. The alarm can be configured to go off at a prescribed time on a specific month, date, hour, minute, or second or repeat every year, month, day, hour, minute, or second. It can also be programmed to go off while the M48T212V is in the battery back-up to serve as a system wake-up call. Bits RPT5-RPT1 put the alarm in the repeat mode of operation. Table 8 shows the possible configurations. Codes not listed in the table default to the once per second mode to quickly alert the user of an incorrect alarm setting.
Note:
User must transition address (or toggle chip enable) to see Flag Bit change. When the clock information matches the alarm clock settings based on the match criteria defined by RPT5-RPT1, the AF (Alarm Flag) is set. If AFE (Alarm Flag Enable) is also set, the alarm condition activates the IRQ/FT pin. To disable alarm, write '0' to the Alarm Date registers and RPT1-5. The IRQ/FT output is cleared by a READ to the Flags Register as shown in Figure 7. A subsequent READ of the Flags Register is necessary to see that the value of the Alarm Flag has been reset to '0.' The IRQ/FT pin can also be activated in the battery back-up mode. The IRQ/FT will go low if an alarm occurs and both ABE (Alarm in Battery Back-up Mode Enable) and AFE are set. The ABE and AFE Bits are reset during power-up, therefore an alarm generated during power-up will only set AF. The user can read the Flag Register at system boot-up to determine if an alarm was generated while the M48T212V was in the deselect mode during power-up. Figure 8 on page 20 illustrates the back-up mode alarm timing. Figure 7. Alarm interrupt reset waveforms
A0-A3
1h
ADDRESS 0h
Fh
ACTIVE FLAG BIT
IRQ/FT HIGH-Z
AI03021
Table 8.
RPT5 1 1 1 1 1 0
Alarm repeat modes
RPT4 1 1 1 1 0 0 RPT3 1 1 1 0 0 0 RPT2 1 1 0 0 0 0 RPT1 1 0 0 0 0 0 Alarm setting Once per second Once per minute Once per hour Once per day Once per month Once per year
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Clock operation Figure 8. Back-up mode alarm waveforms
tREC VCC VPFD (max) VPFD (min)
M48T212V
AFE Bit/ABE Bit
AF Bit in Flags Register
IRQ/FT HIGH-Z HIGH-Z
AI03622
3.6
Watchdog timer
The watchdog timer can be used to detect an out-of-control microprocessor. The user programs the watchdog timer by setting the desired amount of time-out into the Watchdog Register, address 7h. Bits BMB4-BMB0 store a binary multiplier and the two lower-order bits RB1-RB0 select the resolution, where 00=1/16 second, 01=1/4 second, 10=1 second, and 11=4 seconds. The amount of time-out is then determined to be the multiplication of the five-bit multiplier value with the resolution. (For example: writing 00001110 in the Watchdog Register = 3*1 or 3 seconds).
Note:
Accuracy of timer is within the selected resolution. If the processor does not reset the timer within the specified period, the M48T212V sets the WDF (Watchdog Flag) and generates a watchdog interrupt or a microprocessor reset. WDF is reset by reading the Flags Register (Address 0h). The most significant bit of the Watchdog Register is the Watchdog Steering Bit (WDS). When set to a '0.' the watchdog will activate the IRQ/FT pin when timed-out. When WDS is set to a '1,' the watchdog will output a negative pulse on the RST pin for 40 to 200 ms. The Watchdog register, AFE, ABE, and FT Bits will reset to a '0' at the end of a Watchdog timeout when the WDS Bit is set to a '1.' The watchdog timer can be reset by two methods: 1. 2. a transition (high-to-low or low-to-high) can be applied to the Watchdog Input pin (WDI) or the microprocessor can perform a WRITE of the Watchdog Register.
The time-out period then starts over. The WDI pin should be tied to VSS if not used. The watchdog will be reset on each transition (edge) seen by the WDI pin. In the order to
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M48T212V
Clock operation perform a software reset of the watchdog timer, the original time-out period can be written into the Watchdog Register, effectively restarting the count-down cycle. Should the watchdog timer time-out, and the WDS Bit is programmed to output an interrupt, a value of 00h needs to be written to the Watchdog Register in order to clear the IRQ/FT pin. This will also disable the watchdog function until it is again programmed correctly. A READ of the Flags Register will reset the Watchdog Flag (Bit D7; Register 0h). The watchdog function is automatically disabled upon power-down and the Watchdog Register is cleared. If the watchdog function is set to output to the IRQ/FT pin and the frequency test function is activated, the watchdog or alarm function prevails and the frequency test function is denied.
3.7
VCC switch output
Vccsw output goes low when VOUT switches to VCC turning on a customer supplied PChannel MOSFET (see Figure 3 on page 8). The Motorola MTD20P06HDL is recommended. This MOSFET in turn connects VOUT to a separate supply when the current requirement is greater than IOUT1 (see Table 14 on page 28). This output may also be used simply to indicate the status of the internal battery switchover comparator, which controls the source (VCC or battery) of the VOUT output.
3.8
Power-on reset
The M48T212V continuously monitors VCC. When VCC falls to the power fail detect trip point, the RST pulls low (open drain) and remains low on power-up for trec after VCC passes VPFD (max). The RST pin is an open drain output and an appropriate pull-up resistor to VCC should be chosen to control rise time.
Note:
If the RST output is fed back into either of the RSTIN inputs (for a microprocessor with a bidirectional reset) then a 1k (max) pull-up resistor is recommended.
3.9
Reset inputs (RSTIN1 & RSTIN2)
The M48T212V provides two independent inputs which can generate an output reset. The duration and function of these resets is identical to a reset generated by a power cycle. Table 9 and Figure 9 illustrate the AC reset characteristics of this function. During the time RST is enabled (tR1HRH & tR2HRH), the Reset Inputs are ignored.
Note:
RSTIN1 and RSTIN2 are each internally pulled up to VCC through a 100K resistor.
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Clock operation Figure 9. (RSTIN1 & RSTIN2) timing waveforms
M48T212V
RSTIN1 tR1 RSTIN2 tR2 RST tR1HRH tR2HRH
AI02642
Table 9.
Symbol tR1(2) tR2(3) tR1HRH(4) tR2HRH(4)
Reset AC characteristics
Parameter(1) RSTIN1 low to RSTIN1 high RSTIN2 low to RSTIN2 high RSTIN1 high to RST high RSTIN2 high to RST high Min 200 100 40 40 200 200 Max Unit ns ms ms ms
1. Valid for ambient operating temperature: TA = 0 to 70C or 40 to 85C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted). 2. Pulse width less than 50ns will result in no RESET (for noise immunity). 3. Pulse width less than 20ms will result in no RESET (for noise immunity). 4. CL = 5pF (see Figure 13 on page 27).
3.10
Calibrating the clock
The M48T212V is driven by a quartz controlled oscillator with a nominal frequency of 32,768 Hz. The devices are tested not to exceed 35 ppm (parts per million) oscillator frequency error at 25C, which equates to about 1.53 minutes per month (see Figure 10 on page 24). When the Calibration circuit is properly employed, accuracy improves to better than +1/2 ppm at 25C. The oscillation rate of crystals changes with temperature. The M48T212V design employs periodic counter correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage, as shown in Figure 11 on page 25. The number of times pulses which are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five Calibration bits found in the Control Register. Adding counts speeds the clock up, subtracting counts slows the clock down. The Calibration bits occupy the five lower-order bits (D4-D0) in the Control Register 8h. These bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is a Sign Bit; '1' indicates positive calibration, `0' indicates negative calibration. Calibration occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary `1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on.
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M48T212V
Clock operation Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or 2.034 ppm of adjustment per calibration step in the calibration register. Assuming that the oscillator is running at exactly 32,768 Hz, each of the 31 increments in the Calibration byte would represent +10.7 or 5.35 seconds per month which corresponds to a total range of +5.5 or 2.75 minutes per month. Two methods are available for ascertaining how much calibration a given M48T212Y/V may require. The first involves setting the clock, letting it run for a month and comparing it to a known accurate reference and recording deviation over a fixed period of time. Calibration values, including the number of seconds lost or gained in a given period, can be found in Application Note, "AN934, TIMEKEEPER Calibration." This allows the designer to give the end user the ability to calibrate the clock as the environment requires, even if the final product is packaged in a non-user serviceable enclosure. The designer could provide a simple utility that accesses the Calibration byte. The second approach is better suited to a manufacturing environment, and involves the use of the IRQ/FT pin. The pin will toggle at 512Hz, when the Stop Bit (ST, D7 of 9h) is '0,' the Frequency Test Bit (FT, D6 of Ch) is '1,' the Alarm Flag Enable Bit (AFE, D7 of 6h) is '0,' and the Watchdog Steering Bit (WDS, D7 of 7h) is '1' or the Watchdog Register (7h=0) is reset. Any deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at the test temperature. For example, a reading of 512.010124 Hz would indicate a +20 ppm oscillator frequency error, requiring a 10 (WR001010) to be loaded into the Calibration Byte for correction. Note that setting or changing the Calibration Byte does not affect the Frequency test output frequency. The IRQ/FT pin is an open drain output which requires a pull-up resistor to VCC for proper operation. A 500-10k resistor is recommended in order to control the rise time. The FT Bit is cleared on power-up.
3.11
Battery low warning
The M48T212V automatically performs battery voltage monitoring upon power-up and at factory-programmed time intervals of approximately 24 hours. The Battery Low (BL) Bit, Bit D4 of Flags Register 0h, will be asserted if the battery voltage is found to be less than approximately 2.5V. The BL Bit will remain asserted until completion of battery replacement and subsequent battery low monitoring tests, either during the next power-up sequence or the next scheduled 24-hour interval. If a battery low is generated during a power-up sequence, this indicates that the battery is below approximately 2.5 volts and may not be able to maintain data integrity in the SRAM. Data should be considered suspect and verified as correct. A fresh battery should be installed. If a battery low indication is generated during the 24-hour interval check, this indicates that the battery is near end of life. However, data is not compromised due to the fact that a nominal VCC is supplied. In order to ensure data integrity during subsequent periods of battery back-up mode, the battery should be replaced. The SNAPHAT battery/crystal top should be replaced with VCC powering the device to avoid data loss.
Note:
This will cause the clock to lose time during the time interval the battery crystal is removed. The M48T212V only monitors the battery when a nominal VCC is applied to the device. Thus applications which require extensive durations in the battery back-up mode should be
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Clock operation
M48T212V
powered-up periodically (at least once every few months) in order for this technique to be beneficial. Additionally, if a battery low is indicated, data integrity should be verified upon power-up via a checksum or other technique.
3.12
Initial power-on defaults
Upon application of power to the device, the following register bits are set to a '0' state: WDS, BMB0-BMB4, RB0-RB1, AFE, ABE, W, and FT (see Table 10).
Table 10.
Default values
Condition W 0 0 0 0 R 0 0 1 1 FT 0 0 0 0 AFE 0 0 1 0 ABE 0 0 1 0 Watchdog register(1) 0 0 0 0
Initial power-up (Battery attach for SNAPHAT)(2) RESET (3) Power-down (4) Subsequent power-up
1. WDS, BMB0-BMB4, RB0, RB1. 2. State of other control bits undefined. 3. State of other control bits remains unchanged.
4. Assuming these bits set to '1' prior to power-down.
Figure 10. Crystal accuracy across temperature
Frequency (ppm) 20 0 20 40 60 80 100 120 140 160 40 30 20 10 0 10 20 30 40 50 60 70 80 F = -0.038 ppm (T - T )2 10% 0 F C2 T0 = 25 C
Temperature C
AI00999
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M48T212V Figure 11. Calibration waveform
NORMAL
Clock operation
POSITIVE CALIBRATION
NEGATIVE CALIBRATION
AI00594B
3.13
VCC noise and negative going transients
ICC transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if capacitors are used to store energy which stabilizes the VCC bus. The energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1F (as shown in Figure 12) is recommended in order to provide the needed filtering. In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on VCC that drive it to values below VSS by as much as one volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, STMicroelectronics recommends connecting a Schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is recommended for surface mount.
Figure 12. Supply voltage protection
VCC VCC
0.1F
DEVICE
VSS
AI02169
25/35
Maximum rating
M48T212V
4
Maximum rating
Stressing the device above the rating listed in the "Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 11.
Symbol TA TSTG TSLD
(1)
Absolute maximum ratings
Parameter Ambient operating temperature Storage temperature SNAPHAT SOIC Value 0 to 70 40 to 85 55 to 125 260 0.3 to VCC + 0.3 M48T212V 0.3 to 4.6 20 1 Unit C C C C V V mA W
Lead solder temperature for 10 seconds Input or output voltage Supply voltage Output current Power dissipation
VIO VCC IO PD
1. For SO package, Lead-free (Pb-free) lead finish: Reflow at peak temperature of 260C (total thermal budget not to exceed 245C for greater than 30 seconds).
Caution: Caution:
Negative undershoots below 0.3V are not allowed on any pin while in the battery back-up mode. Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
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M48T212V
DC and AC parameters
5
DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the Measurement Conditions listed in Table 12: DC and AC measurement conditions. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 12. DC and AC measurement conditions
Parameter VCC supply voltage Ambient operating temperature Load capacitance (CL) Input rise and fall times Input pulse voltages Input and output timing ref. voltages Grade 1 M48T212V 3.0 to 3.6V 0 to 70C 50pF 5ns 0 to 3V 1.5V
Note:
Output High Z is defined as the point where data is no longer driven. Figure 13. AC testing load circuit
DEVICE UNDER TEST
645
CL = 100pF or 5pF (1) CL = 30 pF (2)
1.75V
CL includes JIG capacitance
AI03239
Note:
Excluding open-drain output pins; 50pF for M48T212V.
1. DQ0-DQ7 2. E1CON and E2CON
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DC and AC parameters Table 13.
Symbol CIN COUT(3)
M48T212V
Capacitance
Parameter(1)(2) Input capacitance Input/output capacitance Min Max 10 10 Unit pF pF
1. Effective capacitance measured with power supply at 3.3V (M48T212V); sampled only, not 100% tested. 2. At 25C, f = 1MHz. 3. Outputs deselected.
Table 14.
DC characteristics
M48T212V
Sym
Parameter
Test condition(1) Min
85 Typ Max 1 1 4 10 3 2 575 800 1250 100 0.3 2.0 0.8 VCC + 0.3 0.4 0.4 2.4 2.0 3.6 70 100 2.7 2.9 VPFD 100mV 3.0 3.0
Unit
ILI
(2) (3)
Input leakage current Output leakage current Supply current Supply current (standby) TTL Supply current (standby) CMOS Battery current OSC ON ON(4)
0V VIN VCC 0V VOUT VCC Outputs open E = V IH E = VCC 0.2 VCC = 0V 950
A A mA mA mA nA nA nA V V V V V V mA A V V V
ILO
ICC ICC1 ICC2 IBAT VIL VIH VOL VOH VOHB(6) IOU1(7) IOUT2 VPFD VSO VBAT
Battery current OSC
Battery current OSC OFF Input low voltage Input high voltage Output low voltage Output low voltage (open drain) Output high voltage VOH battery back-up VOUT current (active) VOUT current (battery back-up) Power-fail deselect voltage Battery back-up switchover voltage Battery voltage
(5)
IOL = 2.1mA IOL = 10mA IOH = 1.0mA IOUT2 = 1.0A VOUT1 > VCC 0.3 VOUT2 > VBAT 0.3
1. Valid for ambient operating temperature: TA = 0 to 70C; VCC = 3.0 to 3.6V (except where noted). 2. RSTIN1 and RSTIN2 internally pulled-up to VCC through 100K resistor. WDI internally pulled-down to VSS through 100K resistor. 3. Outputs deselected. 4. IBAT (OSC ON) = Industrial Temperature Range - Grade 6 device. 5. For IRQ/FT & RST pins (open drain). 6. Conditioned outputs (E1CON - E2CON) can only sustain CMOS leakage currents in the battery back-up mode. Higher leakage currents will reduce battery life. 7. External SRAM must match TIMEKEEPER supervisor chip VCC specification.
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M48T212V Figure 14. Power down/up mode AC waveforms
VCC VPFD (max) VPFD (min) VSO tF tFB tRB
DC and AC parameters
tR trec
INPUTS
VALID
DON'T CARE
VALID
HIGH-Z OUTPUTS VALID VALID
RST
VCCSW
AI02638
Table 15.
Symbol tF tFB tR tRB t rec
Power down/up mode AC characteristics
Parameter(1) VPFD (max) to VPFD (min) VCC fall time VPFD (min) to VSS VCC fall time VPFD (min) to VPFD (max) VCC rise time VSS to VPFD (min) VCC rise time VPFD (max) to RST high M48T212V Min 300 150 10 1 40 200 Max Unit s s s s ms
1. Valid for ambient operating temperature: TA = 0 to 70C; VCC = 3.0 to 3.6V (except where noted).
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Package mechanical data
M48T212V
6
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 15. SOH44 44-lead plastic small outline, SNAPHAT, package outline
A2 B e A C eB CP
D
N
E
H A1 L
1 SOH-A
Note:
Drawing is not to scale. Table 16.
Symb Typ A A1 A2 B C D E e eB H L a N CP 0.81 0.05 2.34 0.36 0.15 17.71 8.23 3.20 11.51 0.41 0 44 0.10 Mi n Max 3.05 0.36 2.69 0.46 0.32 18.49 8.89 3.61 12.70 1.27 8 0.032 0.002 0.092 0.014 0.006 0.697 0.324 0.126 0.453 0.016 0 44 0.004 Typ Min Max 0.120 0.014 0.106 0.018 0.012 0.728 0.350 0.142 0.500 0.050 8
SOH44 44-lead plastic small outline, SNAPHAT, pack. mech. data
mm inches
30/35
M48T212V
Package mechanical data Figure 16. SH 4-pin SNAPHAT housing for 48 mAh battery & crystal, package outline
A1
A2 A A3
eA D
B eB
L
E
SHTK-A
Note:
Drawing is not to scale. Table 17.
Symb Typ A A1 A2 A3 B D E eA eB L 0.46 21.21 14.22 15.55 3.20 2.03 6.73 6.48 Min Max 9.78 7.24 6.99 0.38 0.56 21.84 14.99 15.95 3.61 2.29 0.018 0.835 0.560 0.612 0.126 0.080 0.265 0.255 Typ Min Max 0.385 0.285 0.275 0.015 0.022 0.860 0.590 0.628 0.142 0.090
SH 4-pin SNAPHAT housing for 48 mAh battery & crystal, pack. mech. data
mm inches
31/35
Package mechanical data
M48T212V
Figure 17. SH 4-pin SNAPHAT housing for 120mAh battery & crystal, package outline
A1
A2 A A3
eA D
B eB
L
E
SHTK-A
Note:
Drawing is not to scale. Table 18. SH 4-pin SNAPHAT housing for 120mAh battery & crystal, pack. mech. data
mm Symb Typ A A1 A2 A3 B D E eA eB L 0.46 21.21 17.27 15.55 3.20 2.03 8.00 7.24 Min Max 10.54 8.51 8.00 0.38 0.56 21.84 18.03 15.95 3.61 2.29 0.018 0.835 0.680 0.612 0.126 0.080 0.315 0.285 Typ Min Max 0.415 .0335 0.315 0.015 0.022 0.860 .0710 0.628 0.142 0.090 inches
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M48T212V
Part numbering
7
Part numbering
Table 19.
Example: Device type M48T
Ordering information scheme
M48T 212V 85 MH 1 F
Supply and write protect voltage 212V = VCC = 3.0 to 3.6V; 2.7V VPFD 3.0V
Speed 85 = 85ns (for M48T212V)
Package MH(1) = SOH44
Temperature range 1 = 0 to 70C
Shipping method E = Lead-free package (ECOPACK), tubes F = Lead-free package (ECOPACK), tape & reel
1. The SOIC package (SOH44) requires the SNAPHAT battery package which is ordered separately under the part number "M4Txx-BR12SH1" in plastic tubes (see Table 20).
Caution:
Do not place the SNAPHAT battery package "M4Txx-BR12SH" in conductive foam as it will drain the lithium button-cell battery. For other options, or for more information on any aspect of this device, please contact the ST sales office nearest you. Table 20. SNAPHAT battery table
Description Lithium battery (48mAh) SNAPHAT Lithium battery (120mAh) SNAPHAT Package SH SH
Part number M4T28-BR12SH1 M4T32-BR12SH1
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Revision history
M48T212V
8
Revision history
Table 21.
Date Oct-1999 01-Mar-2000 21-Apr-2000 10-Nov-2000 30-May-2001 10-Sep-2001 13-May-2002 16-Jul-2002 27-Mar-2003 31-Mar-2004 05-Nov-2007
Document revision history
Revision 1.0 2.0 3.0 3.1 3.2 4.0 4.1 4.1 5.0 6.0 7.0 First Issue Document layout changed; default Values table added (Table 10) From Preliminary Data to datasheet Table 16 changed Changed "Controller" references to "SUPERVISOR" Reformatted; added temp./voltage info. to tables (Table 14, 5, 6, 15, 9); added E2 to Hookup (Figure 3); Improve text in "Setting the alarm clock" section Modify reflow time and temperature footnote (Table 11) Updated DC characteristics, footnotes (Table 14) v2.2 template applied; updated test condition (Table 14) Reformatted; updated with Pb-free information (Table 11, 19) Reformatted; added lead-free second level interconnect to cover page and Section 6: Package mechanical data; removed M48T212Y and references throughout document; updated Table 19, 20. Changes
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M48T212V
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