STS8DNF3LL
Dual N-channel 30V - 0.017 - 8A SO-8 Low gate charge STripFETTM II Power MOSFET
General features
Type STS8DNF3LL
VDSS 30V
RDS(on) <0.020
ID 8A
Optimal RDS(on) x Qg trade-off @ 4.5V Conduction losses reduced Switching losses reduced
S0-8
Description
This application specific Power MOSFET is the second generation of STMicroelectronics unique "Single Feature SizeTM" strip-based process. The resulting transistor shows the best trade-off between on-resistance and gate charge. When used as high and low side in buck regulators, it gives the best performance in terms of both conduction and switching losses. This is extremely important for motherboards where fast switching and high efficiency are of paramount importance.
Internal schematic diagram
Applications
Switching application
Order codes
Part number STS8DNF3LL Marking S8DNF3LL Package SO-8 Packaging Tape & reel
January 2007
Rev 10
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Contents
STS8DNF3LL
Contents
1 2 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Electrical characteristics (curves) . . .. . .. . .. . .. . .... 6
3 4 5
Test circuit
. . .. . .. . .. . .. . .. . .. . .. . .. . .... 8
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
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STS8DNF3LL
Electrical ratings
1
Electrical ratings
Table 1.
Sy mbol VDS VGS ID ID IDM (1) PTOT
Absolute maximum ratings
Parameter Drain-source voltage (vgs = 0) Gate- source voltage Drain current (continuos) at TC = 25C single operating Drain current (continuos) at TC = 100C single operating Drain current (pulsed) Total dissipation at TC = 25C dual operating Total dissipation at TC = 25C single operating Value 30 16 8 5 32 2 1.6 Unit V V A A A W W
1. Pulse width limited by safe operating area
Table 2.
Rthj-a TJ Tstg
Thermal data
(1)Ther mal
resistance junction-ambient single operating Thermal resistance junction-ambient dual operating
78 62.5 150 -55 to 150
C/W C/W C C
Thermal operating junction-ambient Storage temperature
1. Mounted on FR-4 board with 0.5 in2 pad of Cu.
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Electrical characteristics
ST S 8 D N F 3 L L
2
Electrical characteristics
(TCASE=25C unless otherwise specified) Table 3.
Symbol V(BR)DSS
On/off states
Parameter Drain-source Breakdown voltage Zero gate voltage Drain current (VGS = 0) Gate-body leakage current (VDS = 0) Gate threshold voltage Static drain-source on resistance Test conditions ID = 250 A, VGS = 0 VDS = Max rating VDS=Max rating, TC=125C VGS = 16V VDS = VGS, ID = 250A VGS = 10V, ID = 4A VGS = 4.5V, ID = 4A 1 0.017 0.020 0.020 0.024 Min. 30 1 10 100 Typ. Max. Unit V A A nA V
IDSS
IGSS VGS(th) RDS(on)
Table 4.
Symbol gfs (1) Ciss Coss Crss Qg Qgs Qgd
Dynamic
Parameter Forward transconductance Input capacitance Output capacitance Reverse transfer capacitance Total gate charge Gate-source charge Gate-drain charge VDS = 25V, f = 1 MHz, VGS = 0 Test conditions VDS = 15V, ID= 4 A Min. Typ. 12.5 800 250 60 VDD = 15V, ID = 8A, VGS = 5V (see Figure 14) 12.5 3.2 4.5 17 Max. Unit S pF pF pF nC nC nC
1. Pulsed: Pulse duration = 300 s, duty cycle 1.5.
Table 5.
Symbol td(on) tr td(off) tf
Switching times
Parameter Turn-on delay time Rise time Test conditions VDD=15 V, ID=4A, RG=4.7, VGS= 4.5V (see Figure 13) VDD=15 V, ID=4A, RG=4.7, VGS= 4.5V (see Figure 13) Min. Typ. 18 32 21 11 Max. Unit ns ns ns ns
Turn-off Delay Time Fall Time
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STS8DNF3LL Table 6.
Symbol ISD ISDM VSD
(1) (2)
Electrical characteristics Source drain diode
Parameter Source-drain current Source-drain current (pulsed) Forward on voltage Reverse recovery time Reverse recovery charge Reverse recovery current ISD = 8A, VGS = 0 ISD = 8A, VDD = 15V di/dt = 100A/s, Tj = 150C (see Figure 15) 23 17 1.5 Test conditions Min. Typ. Max 8 32 1.2 Unit A A V ns nC A
t rr Qrr IRRM
1. Pulse width limited by safe operating area. 2. Pulsed: Pulse duration = 300 s, duty cycle 1.5%
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Electrical characteristics
ST S 8 D N F 3 L L
2.1
Figure 1.
Electrical characteristics (curves)
Safe operating area Figure 2. Thermal impedance
Figure 3.
Output characteristics
Figure 4.
Transfer characteristics
Figure 5.
Transconductance
Figure 6.
Static drain-source on resistance
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STS8DNF3LL Figure 7. Gate charge vs. gate-source voltage Figure 8.
Electrical characteristics Capacitance variations
Figure 9.
Normalized gate threshold voltage vs. temperature
Figure 10. Normalized on resistance vs. temperature
Figure 11. Source-drain diode forward characteristics
Figure 12. Normalized breakdown voltage vs. temperature
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Test circuit
STS8DNF3LL
3
Test circuit
Figure 14. Gate charge test circuit
Figure 13. Switching times test circuit for resistive load
Figure 15. Test circuit for inductive load Figure 16. Unclamped Inductive load test switching and diode recovery times circuit
Figure 17. Unclamped inductive waveform
Figure 18. Switching time waveform
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STS8DNF3LL
Package mechanical data
4
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a Lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at : www.st.com
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Package mechanical data
STS8DNF3LL
SO-8 MECHANICAL DATA
DIM. A a1 a2 a3 b b1 C c1 D E e e3 F L M S 3.8 0.4 4.8 5.8 1.27 3.81 4.0 1.27 0.6 8 (max.) 0.14 0.015 5.0 6.2 0.65 0.35 0.19 0.25 0.1 mm. MIN. TYP M AX. 1.75 0.25 1.65 0.85 0.48 0.25 0.5 45 (typ.) 0.188 0.228 0.050 0.150 0.157 0.050 0.023 0.196 0.244 0.025 0.013 0.007 0.010 0.003 MIN. inch TYP. M AX . 0.068 0.009 0.064 0.033 0.018 0.010 0.019
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STS8DNF3LL
Revision history
5
Revision history
Table 7.
Date 11-Sep-2006 15-Nov-2006 30-Jan-2007
Revision history
Revision 8 9 10 Complete document The document has been reformatted Typo mistake on Table 1. Changes
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STS8DNF3LL
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