M41ST85W
3.0/3.3 V I2C combination serial RTC, NVRAM super visor and microprocessor supervisor
Features
SNAPHAT (SH) battery & crystal
Automatic battery switchover and WRITE protect for: Internal serial RTC and External low power SRAM (LPSRAM) 400 kHz I2C serial interface 3.0/3.3 V operating voltage VCC = 2.7 to 3.6 V Ultralow battery supply current of 500 nA (max) RoHS compliant Lead-free second level interconnect
SOX28 (MX)
28 1
SOH28 (MH) Embedded crystal
Serial RTC features
400 kHz I2C 44 bytes of general purpose NVRAM Counters for: Seconds, minutes, hours, day, date, month, and year Century Tenths/hundredths of seconds Clock calibration register allows compensation for crystal variations over temperature Programmable alarm with repeat modes Functions in battery back-up mode Power-down timestamp (HT bit) 2.5 to 5.5 V oscillator operating voltage
Power-on reset/low voltage detect Open drain reset output Reset voltage, VPFD = 2.60 V (nom) Two reset input pins Watchdog can be steered to reset output
NVRAM supervisor features
Non-volatizes external LPSRAM Automatically switches to back-up battery and deselects (write-protects) external LPSRAM via chip-enable gate Power-fail deselect (write protect) voltage, VPFD = 2.60 V (nom) Switchover, VSO = 2.50 V (nom) Battery monitor (battery low flag)
Microprocessor supervisor features
Programmable watchdog 62.5 ms to 128 s time-out period Early power-fail warning circuit (PFI/PFO) with 1.25 V precision reference
Other features
Programmable squarewave generator (1 Hz to 32 KHz) 40C to +85C operation Package options: 28-lead SNAPHAT IC (SOH28) SNAPHAT battery/crystal top to be ordered separately 28-lead embedded crystal SOIC (SOX28)
December 2008
Rev 10
1/41
www.st.com 1
Contents
M41ST85W
Contents
1 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1 2-wire bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1.1 2.1.2 2.1.3 2.1.4 2.1.5 Bus not busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Star t data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Stop data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Data valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2 2.3 2.4
Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3
Clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 Power-down time-stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 TIMEKEEPER registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Calibrating the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Setting alarm clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Square wave output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Reset inputs (RSTIN1 & RSTIN2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Power-fail input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Century bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Output driver pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Battery low warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 trec bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Initial power-on defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4 5
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
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M41ST85W
Contents
6 7 8 9
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Environmental information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
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List of tables
M41ST85W
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 TIMEKEEPER register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Alarm repeat modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Square wave output frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Reset AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 trec definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Default values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 DC and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Power down/up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 SOH28 28-lead plastic small outline, battery SNAPHAT, package mechanical data . . 34 SH 4-pin SNAPHAT housing for 48 mAh battery & crystal, mechanical data . . . . . . . . 35 SH 4-pin SNAPHAT housing for 120 mAh battery & crystal, mechanical data . . . . . . . 36 SOX28 28-lead plastic small outline, 300 mils, embedded crystal, mechanical data . . . 37 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 SNAPHAT battery/crystal table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
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M41ST85W
List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 28-pin SOIC connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 28-pin, 300 mil SOIC (MX) connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Serial bus data transfer sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Acknowledgement sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Write cycle timing: RTC & external SRAM control signals . . . . . . . . . . . . . . . . . . . . . . . . . 14 Slave address location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Read mode sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Alternate read mode sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Calibration waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Alarm interrupt reset waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Backup mode alarm waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 RSTIN1 & RSTIN2 timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 AC testing input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Bus timing requirements sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 SOH28 28-lead plastic small outline, battery SNAPHAT, package outline . . . . . . . . . . 34 SH 4-pin SNAPHAT housing for 48 mAh battery & crystal, package outline. . . . . . . . . 35 SH 4-pin SNAPHAT housing for 120 mAh battery & crystal, package outline. . . . . . . . 36 SOX28 28-lead plastic small outline, 300 mils, embedded crystal, package outline . . . . 37 Recycling symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
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Description
M41ST85W
1
Description
The M41ST85W is a combination serial real-time clock, microprocessor supervisor, and NVRAM supervisor. It is built in a low power CMOS SRAM process and has a 64-byte memory space with 44 bytes of NVRAM and 20 memory-mapped RTC registers (see Table 2 on page 20). The RTC registers are configured in binary coded decimal (BCD) format. The M41ST85W combines a 400 kHz I2C serial RTC with an automatic backup battery switchover circuit for powering an external LPSRAM as well as the internal RTC. When power begins to fail, the switchover automatically connects to the backup battery to keep the RTC and external LPSRAM alive in the absence of system power. Access to the LPSRAM is also cut off via a chip-enable gate function, thereby write-protecting the memory. A programmable watchdog and power-on reset/low voltage detect function are the key elements in the microprocessor supervisor section. The real-time clock includes a built-in 32.768 kHz oscillator (crystal-controlled), which provides the time base for the timekeeping and calendar functions. Eight of the 20 clock registers provide the basic clock/calendar functions while the other 12 bytes provide status/control for the alarm, watchdog, and squarewave functions. RTC addresses and data are transferred serially via the two-line, bidirectional I2C interface. The built-in address register is incremented automatically after each WRITE or READ data byte. The M41ST85W has a built-in power sense circuit which detects power failures and automatically switches to the backup battery when a power failure occurs. During an outage, the power to sustain the SRAM and clock operations is typically supplied by a small lithium button-cell battery as is the case when using the SNAPHAT package option. Functions available to the user include a non-volatile, time-of-day clock/calendar, alarm interrupts, watchdog timer, and programmable squarewave generator. Other features include a power-on reset as well as two additional debounce reset inputs (RSTIN1 and RSTIN2) which can also generate an output reset (RST). The eight registers for basic clock/calendar functions contain the century, year, month, date, day, hour, minute, second, and tenths/hundredths of a second in 24-hour BCD format. Corrections for 28, 29 (leap year - valid until year 2100), 30 and 31 day months are made automatically. The M41ST85W is offered in two 28-lead SOIC packages. The 300 mil SOH28 SNAPHAT IC package mates with ST's SNAPHAT battery/crystal top (ordered separately). SNAPHAT battery options include 48 mAh and 120 mAh. ST's 300 mil SOX28 embedded crystal IC includes the 32 KHz crystal and is perfect for applications where a low profile is a must. The SOH28 SNAPHAT SOIC includes sockets with gold plated contacts at both ends for direct connection to the SNAPHAT top. The SNAPHAT battery/crystal top is inserted atop the IC package after the completion of the surface mount assembly process which avoids potential battery and crystal damage due to the high temperatures required for device surface-mounting. The unique design allows the battery to be replaced, thus extending the life of the RTC and NVRAM indefinitely. The SNAPHAT top is keyed to prevent reverse insertion. The SNAPHAT IC and SNAPHAT tops are shipped separately. The ICs are available in plastic anti-static tubes or in tape & reel form. The SNAPHAT tops are shipped in plastic anti-static tubes. The part numbers are
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M41ST85W
Description M4T28-BR12SH1 (48 mAh) and M4T32-BR12SH1 (120 mAh). For the extended temperature requirement, the 120 mAh M4T32-BR12SH6 is available. For more information, see Table 19 on page 38.
Caution:
Do not place the SNAPHAT battery/crystal top in conductive foam, as this will drain the lithium button-cell battery. The 300 mil SOX embedded crystal SOIC typically requires a user-supplied battery for nonvolatile operation. Capacitor backup can also be implemented with this package. Figure 1. Logic diagram
VCC VBAT(1)
SCL ECON SDA RST EX IRQ/FT/OUT RSTIN1 RSTIN2 PFO WDI VOUT PFI M41ST85W SQW
VSS
1. For 28-pin, 300 mil embedded crystal SOIC only.
AI03658
7/41
Description Table 1.
ECON EX IRQ/FT/OUT PFI PFO RST RSTIN1 RSTIN2 SCL SDA SQW WDI VCC VOUT VSS VBAT NC NF
(1)
M41ST85W Signal names
Conditioned chip enable output External chip enable Interrupt/frequency test/out output (open drain) Power fail input Power fail output Reset output (open drain) Reset 1 Input Reset 2 Input Serial clock input Serial data input/output Square wave output Watchdog input Supply voltage Voltage output Ground Battery supply voltage No connect No function
1. For 28-pin, 300 mil embedded crystal SOIC only.
Figure 2.
28-pin SOIC connections
SQW NC NC NC NC NC NC WDI RSTIN1 RSTIN2 NC NC PFO VSS 28 1 2 27 3 26 4 25 5 24 6 23 7 22 M41ST85W 8 21 9 20 10 19 11 18 12 17 13 16 14 15
AI03659
VCC EX IRQ/FT/OUT VOUT NC NC PFI NC SCL NC RST NC SDA ECON
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M41ST85W Figure 3. 28-pin, 300 mil SOIC (MX) connections
NF NF NF NF NC NC NC SQW WDI RSTIN1 RSTIN2 PFO NC VSS 28 1 2 27 3 26 4 25 5 24 6 23 7 22 M41ST85W 8 21 9 20 10 19 11 18 12 17 13 16 14 15 VCC EX IRQ/FT/OUT VOUT NC PFI SCL NC NC RST NC SDA ECON VBAT
AI06370d
Description
Note:
No function (NF) pins should be tied to VSS. Pins 1, 2, 3, and 4 are internally shorted together.
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Description Figure 4. Block diagram
REAL TIME CLOCK CALENDAR SDA I2C INTERFACE SCL 44 BYTES USER RAM RTC w/ALARM & CALIBRATION WATCHDOG SQUARE WAVE AFE WDS
M41ST85W
IRQ/FT/OUT(1)
(2) Cr ystal
32KHz OSCILLATOR
SQW
WDI VCC
VOUT
VBAT VBL= 2.5V COMPARE BL
VSO = 2.5V
COMPARE
VPFD = 2.65V RSTIN1 RSTIN2
COMPARE
POR RST(1)
EX PFI COMPARE 1.25V (Internal)
ECON PFO
AI03932
1. Open drain output. 2. Crystal integrated into SOIC package for MX package option.
10/41
M41ST85W Figure 5. Hardware hookup
Description
Regulator Unregulated Voltage VIN VCC VCC
M41ST85W VOUT ECON EX SCL From MCU SDA WDI RSTIN1 RST SQW PFO PFI (1) IRQ/FT/OUT VBAT VSS To RST To LED Display To NMI To INT VCC E LPSRAM
R1
Pushbutton Reset
RSTIN2
R2
AI03660
1. Required for embedded crystal (MX) package only.
11/41
Operating modes
M41ST85W
2
Operating modes
The M41ST85W clock operates as a slave device on the serial bus. Access is obtained by implementing a start condition followed by the correct slave address (D0h). The 64 bytes contained in the device can then be accessed sequentially in the following order: 1. 2. 3. 4. 5. 6. 7. 8. 9. Tenths/hundredths of a second register Seconds register Minutes register Century/hours register Day register Date register Month register Year register Control register
10. Watchdog register 11 - 16. Alarm registers 17 - 19. Reserved 20. Square wave register 21 - 64. User RAM The M41ST85W clock continually monitors VCC for an out-of-tolerance condition. Should VCC fall below VPFD, the device terminates an access in progress and resets the device address counter. Inputs to the device will not be recognized at this time to prevent erroneous data from being written to the device from a an out-of-tolerance system. When VCC falls below VSO, the device automatically switches over to the battery and powers down into an ultralow current mode of operation to conserve battery life. As system power returns and VCC rises above VSO, the battery is disconnected, and the power supply is switched to external VCC. Write protection continues until VCC reaches VPFD(min) plus trec (min). For more information on battery storage life refer to application note AN1012.
2.1
2-wire bus characteristics
The bus is intended for communication between different ICs. It consists of two lines: a bidirectional data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must be connected to a positive supply voltage via a pull-up resistor. The following protocol has been defined:
Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line, while the clock line is high, will be interpreted as control signals.
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M41ST85W Accordingly, the following bus conditions have been defined:
Operating modes
2.1.1
Bus not busy
Both data and clock lines remain high.
2.1.2
Start data transfer
A change in the state of the data line, from high to low, while the clock is high, defines the START condition.
2.1.3
Stop data transfer
A change in the state of the data line, from low to high, while the clock is high, defines the STOP condition.
2.1.4
Data valid
The state of the data line represents valid data when after a start condition, the data line is stable for the duration of the high period of the clock signal. The data on the line may be changed during the low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a start condition and terminated with a stop condition. The number of data bytes transferred between the start and stop conditions is not limited. The information is transmitted byte-wide and each receiver acknowledges with a ninth bit. By definition a device that gives out a message is called "transmitter," the receiving device that gets the message is called "receiver." The device that controls the message is called "master." The devices that are controlled by the master are called "slaves."
2.1.5
Acknowledge
Each byte of eight bits is followed by one acknowledge bit. This acknowledge bit is a low level put on the bus by the receiver whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed is obliged to generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is a stable low during the high period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master receiver must signal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this case the transmitter must leave the data line high to enable the master to generate the STOP condition.
13/41
Operating modes Figure 6. Serial bus data transfer sequence
DATA LINE STABLE DATA VALID
M41ST85W
CLOCK
DATA
START CONDITION
CHANGE OF DATA ALLOWED
STOP CONDITION
AI00587
Figure 7.
Acknowledgement sequence
CLOCK PULSE FOR ACKNOWLEDGEMENT 1 2 8 9
START SCL FROM MASTER
DATA OUTPUT BY TRANSMITTER
MSB
LSB
DATA OUTPUT BY RECEIVER
AI00601
Figure 8.
Write cycle timing: RTC & external SRAM control signals
EX tEXPD tEXPD ECON
AI03663
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M41ST85W
Operating modes
2.2
Read mode
In this mode the master reads the M41ST85W slave after setting the slave address (see Figure 9). Following the WRITE mode control bit (R/W=0) and the acknowledge bit, the word address 'An' is written to the on-chip address pointer. Next the START condition and slave address are repeated followed by the READ mode control bit (R/W=1). At this point the master transmitter becomes the master receiver. The data byte which was addressed will be transmitted and the master receiver will send an acknowledge bit to the slave transmitter (see Figure 10 on page 16). The address pointer is only incremented on reception of an acknowledge clock. The M41ST85W slave transmitter will now place the data byte at address An+1 on the bus, the master receiver reads and acknowledges the new byte and the address pointer is incremented to An+2. This cycle of reading consecutive addresses will continue until the master receiver sends a STOP condition to the slave transmitter. The system-to-user transfer of clock data will be halted whenever the address being read is a clock address (00h to 07h). The update will resume either due to a stop condition or when the pointer increments to a non-clock or RAM address.
Note:
This is true both in READ mode and WRITE mode. An alternate READ mode may also be implemented whereby the master reads the M41ST85W slave without first writing to the (volatile) address pointer. The first address that is read is the last one stored in the pointer (see Figure 11 on page 16). Figure 9. Slave address location
R/W
START
SLAVE ADDRESS
A
MSB
1
1
0
1
0
0
LSB 0
AI00602
15/41
Operating modes Figure 10. Read mode sequence
START START
M41ST85W
R/W
BUS ACTIVITY: MASTER
SDA LINE
S
WORD ADDRESS (An) ACK
S
R/W
DATA n
DATA n+1
ACK
ACK
ACK
BUS ACTIVITY: SLAVE ADDRESS
SLAVE ADDRESS STOP
DATA n+X
P
AI00899
Figure 11. Alternate read mode sequence
START
NO ACK
BUS ACTIVITY: MASTER SDA LINE
S ACK
R/W
DATA n ACK
DATA n+1 ACK ACK
DATA n+X
P NO ACK
BUS ACTIVITY: SLAVE ADDRESS
AI00895
16/41
STOP
ACK
M41ST85W
Operating modes
2.3
Write mode
In this mode the master transmitter transmits to the M41ST85W slave receiver. Bus protocol is shown in Figure 12. Following the START condition and slave address, a logic '0' (R/W=0) is placed on the bus and indicates to the addressed device that word address An will follow and is to be written to the on-chip address pointer. The data word to be written to the memory is strobed in next and the internal address pointer is incremented to the next memory location within the RAM on the reception of an acknowledge clock. The M41ST85W slave receiver will send an acknowledge clock to the master transmitter after it has received the slave address and again after it has received the word address and each data byte.
Figure 12. Write mode sequence
START BUS ACTIVITY: MASTER R/W STOP WORD ADDRESS (An) ACK ACK DATA n DATA n+1 DATA n+X P ACK ACK
AI00591
SDA LINE
S
BUS ACTIVITY: SLAVE ADDRESS
2.4
Data retention mode
With valid VCC applied, the M41ST85W can be accessed as described above with READ or WRITE cycles. Should the supply voltage decay, the M41ST85W will automatically deselect, write protecting itself (and any external SRAM) when VCC falls between VPFD(max) and VPFD(min). This is accomplished by internally inhibiting access to the clock registers. At this time, the reset pin (RST) is driven active and will remain active until VCC returns to nominal levels. External RAM access is inhibited in a similar manner by forcing ECON to a high level. This level is within 0.2 volts of the VBAT. ECON will remain at this level as long as VCC remains at an out-of-tolerance condition. When VCC falls below the battery backup switchover voltage (VSO), power input is switched from the VCC pin to the SNAPHAT battery, and the clock registers and external SRAM are maintained from the attached battery supply. All outputs become high impedance. The VOUT pin is capable of supplying 100 A of current to the attached memory with less than 0.3 volts drop under this condition. On power-up, when VCC returns to a nominal value, write protection continues for trec by inhibiting ECON. The RST signal also remains active during this time (see Figure 20 on page 33).
Note:
Most low power SRAMs on the market today can be used with the M41ST85W RTC SUPERVISOR. There are, however some criteria which should be used in making the final choice of an SRAM to use. The SRAM must be designed in a way where the chip enable input disables all other inputs to the SRAM. This allows inputs to the M41ST85W and SRAMs to be "Don't Care" once VCC falls below VPFD(min). The SRAM should also guarantee data retention down to VCC = 2.0 volts. The chip enable access time must be sufficient to meet the system needs with the chip enable output propagation delays included. If the SRAM includes a second chip enable pin (E2), this pin should be tied to VOUT.
17/41
ACK
Operating modes
M41ST85W
If data retention lifetime is a critical parameter for the system, it is important to review the data retention current specifications for the particular SRAMs being evaluated. Most SRAMs specify a data retention current at 3.0 volts. Manufacturers generally specify a typical condition for room temperature along with a worst case condition (generally at elevated temperatures). The system level requirements will determine the choice of which value to use. The data retention current value of the SRAMs can then be added to the IBAT value of the M41ST85W to determine the total current requirements for data retention. The available battery capacity for the SNAPHAT top of your choice can then be divided by this current to determine the amount of data retention available (see Table 19 on page 38). For a further more detailed review of lifetime calculations, please see application note AN1012.
18/41
M41ST85W
Clock operation
3
Clock operation
The eight byte clock register (see Table 2 on page 20) is used to both set the clock and to read the date and time from the clock, in a binary coded decimal format. Tenths/hundredths of seconds, seconds, minutes, and hours are contained within the first four registers.
Note:
A WRITE to any clock register will result in the tenths/hundredths of seconds being reset to "00," and tenths/hundredths of seconds cannot be written to any value other than "00." Bits D6 and D7 of clock register 03h (century/hours register) contain the CENTURY ENABLE bit (CEB) and the CENTURY bit (CB). Setting CEB to a '1' will cause CB to toggle, either from '0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial state). If CEB is set to a '0,' CB will not toggle. Bits D0 through D2 of register 04h contain the day (day of week). Registers 05h, 06h, and 07h contain the date (day of month), month and years. The ninth clock register is the control register (this is described in the clock calibration section). Bit D7 of register 01h contains the STOP bit (ST). Setting this bit to a '1' will cause the oscillator to stop. If the device is expected to spend a significant amount of time on the shelf, the oscillator may be stopped to reduce current drain. When reset to a '0' the oscillator restarts within one second. The eight clock registers may be read one byte at a time, or in a sequential block. The control register (address location 08h) may be accessed independently. Provision has been made to assure that a clock update does not occur while any of the eight clock addresses are being read. If a clock address is being read, an update of the clock registers will be halted. This will prevent a transition of data during the READ.
3.1
Power-down time-stamp
When a power failure occurs, the halt update bit (HT) will automatically be set to a '1.' This will prevent the clock from updating the TIMEKEEPER registers, and will allow the user to read the exact time of the power-down event. Resetting the HT bit to a '0' will allow the clock to update the TIMEKEEPER registers with the current time. For more information, see application note AN1572.
3.2
TIMEKEEPER registers
The M41ST85W offers 20 internal registers which contain clock, alarm, watchdog, flag, square wave and control data. These registers are memory locations which contain external (user accessible) and internal copies of the data (usually referred to as BiPORTTM TIMEKEEPER cells). The external copies are independent of internal functions except that they are updated periodically by the simultaneous transfer of the incremented internal copy. The internal divider (or clock) chain will be reset upon the completion of a WRITE to any clock address. The system-to-user transfer of clock data will be halted whenever the address being read is a clock address (00h to 07h). The update will resume either due to a stop condition or when the pointer increments to a non-clock or RAM address. TIMEKEEPER and alarm registers store data in BCD. control, watchdog and square wave registers store data in binary format.
19/41
Clock operation Table 2.
Address D7 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h Keys: OUT WDS AFE RPT4 RPT3 RPT2 RPT1 WDF 0 0 0 RS3 S = Sign bit FT = Frequency test bit ST = Stop bit 0 = Must be set to zero BL = Battery low flag (read only) BMB0-BMB4 = Watchdog multiplier bits CEB = Century enable bit CB = Century bit OUT = Output level AFE = Alarm flag enable flag ST 0 CEB TR 0 0 CB 0 0 0 0 D6 D5 D4 D3 D2 D1 D0 0.1 seconds 10 seconds 10 minutes 10 hours 0 10 date 10M 0 0 0.01 seconds Seconds Minutes Hours (24-hour format) Day of week Date: day of month Month Year Calibration BMB2 Al 10M BMB1 BMB0 RB1 RB0
M41ST85W
TIMEKEEPER register map
Data Function/range BCD format Seconds Seconds Minutes Centur y/hours Day Date Month Year Control Watchdog Al month Al date Al hour Al min Al sec 0 0 0 0 0 Flags Reserved Reserved Reserved SQW 01-12 01-31 00-23 00-59 00-59 00-99 00-59 00-59 0-1/00-23 01-7 01-31 01-12 00-99
10 years FT BMB4 SQWE RPT5 HT S BMB3 ABE
Alarm month Alarm date Alarm hour Alarm minutes Alarm seconds 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
AI 10 date AI 10 hour
Alarm 10 minutes Alarm 10 seconds AF 0 0 0 RS2 0 0 0 0 RS1 BL 0 0 0 RS0
RB0-RB1 = Watchdog resolution bits WDS = Watchdog steering bit ABE = Alarm in battery backup mode enable bit RPT1-RPT5 = Alarm repeat mode bits WDF = Watchdog flag (read only) AF = Alarm flag (read only) SQWE = Square wave enable RS0-RS3 = SQW frequency HT = Halt update bit TR = trec bit
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M41ST85W
Clock operation
3.3
Calibrating the clock
The M41ST85W is driven by a quartz controlled oscillator with a nominal frequency of 32,768 Hz. The devices are tested not exceed +/35 ppm (parts per million) oscillator frequency error at 25oC, which equates to about +/1.53 minutes per month. When the Calibration circuit is properly employed, accuracy improves to better than 2 ppm at 25C. The oscillation rate of crystals changes with temperature (see Figure 13 on page 22). Therefore, the M41ST85W design employs periodic counter correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage, as shown in Figure 14 on page 22. The number of times pulses which are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five calibration bits found in the control register. Adding counts speeds the clock up, subtracting counts slows the clock down. The calibration bits occupy the five lower order bits (D4-D0) in the control register (08h). These bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is a sign bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or 2.034 ppm of adjustment per calibration step in the calibration register. Assuming that the oscillator is running at exactly 32,768 Hz, each of the 31 increments in the calibration byte would represent +10.7 or 5.35 seconds per month which corresponds to a total range of +5.5 or 2.75 minutes per month. Two methods are available for ascertaining how much calibration a given M41ST85W may require. The first involves setting the clock, letting it run for a month and comparing it to a known accurate reference and recording deviation over a fixed period of time. Calibration values, including the number of seconds lost or gained in a given period, can be found in application note AN934, "TIMEKEEPER calibration." This allows the designer to give the end user the ability to calibrate the clock as the environment requires, even if the final product is packaged in a non-user serviceable enclosure. The designer could provide a simple utility that accesses the calibration byte. The second approach is better suited to a manufacturing environment, and involves the use of the IRQ/FT/OUT pin. The pin will toggle at 512 Hz, when the stop bit (ST, D7 of 01h) is '0,' the frequency test bit (FT, D6 of 08h) is '1,' the alarm flag enable bit (AFE, D7 of 0Ah) is '0,' and the watchdog steering bit (WDS, D7 of 09h) is '1' or the watchdog register (09h = 0) is reset. Any deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at the test temperature. For example, a reading of 512.010124 Hz would indicate a +20 ppm oscillator frequency error, requiring a 10 (XX001010) to be loaded into the calibration byte for correction. Note that setting or changing the calibration byte does not affect the frequency test output frequency. The IRQ/FT/OUT pin is an open drain output which requires a pull-up resistor to VCC for proper operation. A 500 to 10 k resistor is recommended in order to control the rise time. The FT bit is cleared on power-down.
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Clock operation Figure 13. Crystal accuracy across temperature
M41ST85W
Frequency (ppm) 20 0 20 40 60 80 100 120 140 160 40 30 20 10 0 10 20 30 40 50 60 70 80 F = K x (T T )2 O F K = 0.036 ppm/C 0.006 ppm/C TO = 25C 5C
2 2
Temperature C
AI07888
Figure 14. Calibration waveform
NORMAL
POSITIVE CALIBRATION
NEGATIVE CALIBRATION
AI00594B
22/41
M41ST85W
Clock operation
3.4
Setting alarm clock registers
Address locations 0Ah-0Eh contain the alarm settings. The alarm can be configured to go off at a prescribed time on a specific month, date, hour, minute, or second, or repeat every year, month, day, hour, minute, or second. It can also be programmed to go off while the M41ST85W is in the battery backup to serve as a system wake-up call. Bits RPT5RPT1 put the alarm in the repeat mode of operation. Table 3 shows the possible configurations. Codes not listed in the table default to the once per second mode to quickly alert the user of an incorrect alarm setting. When the clock information matches the alarm clock settings based on the match criteria defined by RPT5RPT1, the AF (alarm flag) is set. If AFE (alarm flag enable) is also set, the alarm condition activates the IRQ/FT/OUT pin as shown in Figure 15. To disable alarm, write '0' to the alarm date register and to RPT5RPT1.
Note:
If the address pointer is allowed to increment to the flag register address, an alarm condition will not cause the interrupt/flag to occur until the address pointer is moved to a different address. It should also be noted that if the last address written is the "Alarm Seconds," the address pointer will increment to the flag address, causing this situation to occur. The IRQ/FT/OUT output is cleared by a READ to the flags register. A subsequent READ of the flags register is necessary to see that the value of the alarm flag has been reset to '0.' The IRQ/FT/OUT pin can also be activated in the battery backup mode. The IRQ/FT/OUT will go low if an alarm occurs and both ABE (alarm in battery backup mode enable) and AFE are set. The ABE and AFE bits are reset during power-up, therefore an alarm generated during power-up will only set AF. The user can read the flag register at system boot-up to determine if an alarm was generated while the M41ST85W was in the deselect mode during power-up. Figure 16 on page 24 illustrates the backup mode alarm timing.
Figure 15. Alarm interrupt reset waveform
0Eh
0Fh
10h
ACTIVE FLAG
IRQ/FT/OUT
HIGH-Z
AI03664
Table 3.
RPT5 1 1 1 1 1 0
Alarm repeat modes
RPT4 1 1 1 1 0 0 RPT3 1 1 1 0 0 0 RPT2 1 1 0 0 0 0 RPT1 1 0 0 0 0 0 Alarm setting Once per second Once per minute Once per hour Once per day Once per month Once per year
23/41
Clock operation Figure 16. Backup mode alarm waveform
M41ST85W
VCC VPFD
VSO trec ABE, AFE Bits in Interrupt Register
AF bit in Flags Register
IRQ/FT/OUT HIGH-Z HIGH-Z
AI03920
3.5
Watchdog timer
The watchdog timer can be used to detect an out-of-control microprocessor. The user programs the watchdog timer by setting the desired amount of time-out into the watchdog register, address 09h. Bits BMB4-BMB0 store a binary multiplier and the two lower order bits RB1-RB0 select the resolution, where 00 = 1/16 second, 01 = 1/4 second, 10 = 1 second, and 11 = 4 seconds. The amount of time-out is then determined to be the multiplication of the five-bit multiplier value with the resolution. (For example: writing 00001110 in the watchdog register = 3*1 or 3 seconds).
Note:
The accuracy of the timer is within the selected resolution. If the processor does not reset the timer within the specified period, the M41ST85W sets the WDF (watchdog flag) and generates a watchdog interrupt or a microprocessor reset. The most significant bit of the watchdog register is the watchdog steering bit (WDS). When set to a '0,' the watchdog will activate the IRQ/FT/OUT pin when timed-out. When WDS is set to a '1,' the watchdog will output a negative pulse on the RST pin for trec. The watchdog register, FT, AFE, ABE and SQWE bits will reset to a '0' at the end of a watchdog time-out when the WDS bit is set to a '1.' The watchdog timer can be reset by two methods: 1) a transition (high-to-low or low-to-high) can be applied to the watchdog input pin (WDI) or 2) the microprocessor can perform a WRITE of the watchdog register. The time-out period then starts over.
Note:
The WDI pin should be tied to VSS if not used. In order to perform a software reset of the watchdog timer, the original time-out period can be written into the watchdog register, effectively restarting the count-down cycle. Should the watchdog timer time-out, and the WDS bit is programmed to output an interrupt, a value of 00h needs to be written to the watchdog register in order to clear the IRQ/FT/OUT
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M41ST85W
Clock operation pin. This will also disable the watchdog function until it is again programmed correctly. A READ of the flags register will reset the watchdog flag (bit D7; register 0Fh). The watchdog function is automatically disabled upon power-up and the watchdog register is cleared. If the watchdog function is set to output to the IRQ/FT/OUT pin and the frequency test function is activated, the watchdog function prevails and the frequency test function is denied.
3.6
Square wave output
The M41ST85W offers the user a programmable square wave function which is output on the SQW pin. RS3-RS0 bits located in 13h establish the square wave output frequency. These frequencies are listed in Table 4. Once the selection of the SQW frequency has been completed, the SQW pin can be turned on and off under software control with the square wave enable bit (SQWE) located in register 0Ah. Table 4. Square wave output frequency
Square wave bits RS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 RS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 RS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 RS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Square wave Frequency None 32.768 8.192 4.096 2.048 1.024 512 256 128 64 32 16 8 4 2 1 Units kHz kHz kHz kHz kHz Hz Hz Hz Hz Hz Hz Hz Hz Hz Hz
3.7
Power-on reset
The M41ST85W continuously monitors VCC. When VCC falls to the power fail detect trip point, the RST pulls low (open drain) and remains low on power-up for trec after VCC passes VPFD(max). The RST pin is an open drain output and an appropriate pull-up resistor should be chosen to control rise time.
25/41
Clock operation
M41ST85W
3.8
Reset inputs (RSTIN1 & RSTIN2)
The M41ST85W provides two independent inputs which can generate an output reset. The duration and function of these resets is identical to a reset generated by a power cycle. Table 5 and Figure 17 illustrate the AC reset characteristics of this function. Pulses shorter than tRLRH1 and tRLRH2 will not generate a reset condition. RSTIN1 and RSTIN2 are each internally pulled up to VCC through a 100 k resistor.
Figure 17. RSTIN1 & RSTIN2 timing waveforms
RSTIN1 tRLRH1 RSTIN2 tRLRH2 RST
(1)
tR1HRH
tR2HRH
AI03665
Note: Table 5.
With pull-up resistor Reset AC characteristics
Parameter(1) RSTIN1 low to RSTIN1 high RSTIN2 low to RSTIN2 high RSTIN1 high to RST high RSTIN2 high to RST high Min 200 100 40 40 200 200 Max Unit ns ms ms ms
Symbol tRLRH1(2) tRLRH2(3) tR1HRH(4) tR2HRH(4)
1. Valid for ambient operating temperature: TA = 40 to 85C; VCC = 2.7 to 3.6 V (except where noted). 2. Pulse width less than 50 ns will result in no RESET (for noise immunity). 3. Pulse width less than 20 ms will result in no RESET (for noise immunity). 4. Programmable (see Table 6 on page 28).
3.9
Power-fail input/output
The power-fail input (PFI) is compared to an internal reference voltage (1.25 V). If PFI is less than the power-fail threshold (VPFI), the power-fail output (PFO) will go low. This function is intended for use as an undervoltage detector to signal a failing power supply. Typically PFI is connected through an external voltage divider (see Figure 5 on page 11) to either the unregulated DC input (if it is available) or the regulated output of the VCC regulator. The voltage divider can be set up such that the voltage at PFI falls below VPFI several milliseconds before the regulated VCC input to the M41ST85W or the microprocessor drops below the minimum operating voltage. During battery backup, the power-fail comparator turns off and PFO goes (or remains) low. This occurs after VCC drops below VPFD(min). When power returns, PFO is forced high, irrespective of VPFI for the write protect time (trec), which is the time from VPFD(max) until the inputs are recognized. At the end of this time, the power-fail comparator is enabled and PFO
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M41ST85W
Clock operation follows PFI. If the comparator is unused, PFI should be connected to VSS and PFO left unconnected.
3.10
Century bit
Bits D7 and D6 of clock register 03h contain the CENTURY ENABLE bit (CEB) and the CENTURY bit (CB). Setting CEB to a '1' will cause CB to toggle, either from a '0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial state). If CEB is set to a '0,' CB will not toggle.
3.11
Output driver pin
When the FT bit, AFE bit and watchdog register are not set, the IRQ/FT/OUT pin becomes an output driver that reflects the contents of D7 of the control register. In other words, when D7 (OUT bit) and D6 (FT bit) of address location 08h are a '0,' then the IRQ/FT/OUT pin will be driven low.
Note:
The IRQ/FT/OUT pin is an open drain which requires an external pull-up resistor.
3.12
Battery low warning
The M41ST85W automatically performs battery voltage monitoring upon power-up and at factory-programmed time intervals of approximately 24 hours. The battery low (BL) bit, bit D4 of flags register 0Fh, will be asserted if the battery voltage is found to be less than approximately 2.5 V. The BL bit will remain asserted until completion of battery replacement and subsequent battery low monitoring tests, either during the next power-up sequence or the next scheduled 24-hour interval. If a battery low is generated during a power-up sequence, this indicates that the battery is below approximately 2.5 volts and may not be able to maintain data integrity in the SRAM. Data should be considered suspect and verified as correct. A fresh battery should be installed. If a battery low indication is generated during the 24-hour interval check, this indicates that the battery is near end of life. However, data is not compromised due to the fact that a nominal VCC is supplied. In order to insure data integrity during subsequent periods of battery backup mode, the battery should be replaced. The SNAPHAT top may be replaced while VCC is applied to the device.
Note:
This will cause the clock to lose time during the interval the SNAPHAT battery/crystal top is disconnected. The M41ST85W only monitors the battery when a nominal VCC is applied to the device. Thus applications which require extensive durations in the battery backup mode should be powered-up periodically (at least once every few months) in order for this technique to be beneficial. Additionally, if a battery low is indicated, data integrity should be verified upon power-up via a checksum or other technique.
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Clock operation
M41ST85W
3.13
trec bit
Bit D7 of clock register 04h contains the trec bit (TR). trec refers to the automatic continuation of the deselect time after VCC reaches VPFD. This allows for a voltage settling time before WRITEs may again be performed to the device after a power-down condition. The trec bit will allow the user to set the length of this deselect time as defined by Table 6.
3.14
Initial power-on defaults
Upon initial application of power to the device, the following register bits are set to a '0' state: watchdog register, FT, AFE, ABE, SQWE, and TR. The following bits are set to a '1' state: ST, OUT, and HT (see Table 7).
Table 6.
trec definitions
STOP bit (ST) Min 0 1 X 96 40 50 trec time Max 98 200
(1)
trec bit (TR) 0 0 1
1. Default setting
Units ms ms s
2000
Table 7.
Default values
TR 0 UC ST 1 UC HT 1 1 Out 1 UC FT 0 0 AFE 0 0 ABE 0 0 SQWE 0 0 Watchdog register(1) 0 0
Condition Initial power-up(2) Subsequent power-up (with battery backup)(3)
1. WDS, BMB0-BMB4, RB0, RB1. 2. State of other control bits undefined. 3. UC = Unchanged
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M41ST85W
Maximum ratings
4
Maximum ratings
Stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 8.
Symbol TSTG TSLD VIO VCC IO PD
Absolute maximum ratings
Parameter Storage temperature (VCC off, oscillator off) Lead solder temperature for 10 seconds Input or output voltage Supply voltage Output current Power dissipation SNAPHAT SOIC SOH28(1) SOX28(2) Value 40 to 85 55 to 150 260 240 0.3 to VCC+0.3 0.3 to 4.6 20 1 Unit C C C C V V mA W
1. For SOH28 package, lead-free (pb-free) lead finish: reflow at peak temperature of 260C (the time above 255C must not exceed 30 seconds). 2. The SOX28 package has lead-free (pb-free) lead finish, but cannot be exposed to peak reflow temperature in excess of 240C. Reflow at peak temperature of 240C (the time above 235C must not exceed 20 seconds).
Caution: Caution:
Negative undershoots below 0.3 V are not allowed on any pin while in the battery backup mode. Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
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DC and AC parameters
M41ST85W
5
DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC characteristic tables are derived from tests performed under the measurement conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 9. DC and AC measurement conditions
Parameter VCC supply voltage Ambient operating temperature Load capacitance (CL) Input rise and fall times Input pulse voltages Input and output timing ref. voltages M41ST85W 2.7 to 3.6 V 40 to 85C 50 pF 50 ns 0.2 to 0.8VCC 0.3 to 0.7VCC
Note:
Output High Z is defined as the point where data is no longer driven. Figure 18. AC testing input/output waveforms
0.8VCC
0.7VCC 0.3VCC
AI02568
0.2VCC
Table 10.
Symbol CIN COUT(3) tLP
Capacitance
Parameter(1)(2) Input capacitance Output capacitance Low-pass filter input time constant (SDA and SCL) Min Max 7 10 50 Unit pF pF ns
1. Effective capacitance measured with power supply at 5 V. Sampled only, not 100% tested. 2. At 25C, f = 1 MHz. 3. Outputs are deselected.
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M41ST85W Table 11.
Sym
DC and AC parameters DC characteristics
Parameter Test condition(1) Min M41ST85W Unit Typ 400 50 0.75 0.50 1 25 0V VIN VCC VOUT1 > VCC 0.3 V VOUT2 > VBAT 0.3 V 0.7VCC 0.3 2.5 IOH = 1.0 mA RST, IRQ/FT/OUT IOUT2 = 1.0 A IOL = 3.0 mA IOL = 10 mA 2.55 VCC = 3 V(W) PFI rising 1.225 2.60 1.250 20 2.5 2.5 2.9 2.4 3.6 3.5 0.4 0.4 2.70 1.275 70 3.0 2 25 1 100 100 VCC + 0.3 0.3VCC 3.5(6) Max 500 nA nA mA mA A nA A mA A V V V V V V V V V V mV V
IBAT(2) ICC1 ICC2 ILI(3) ILO(4) IOUT1(5) IOUT2 VIH VIL VBAT VOH VOHB(8) VOL VPFD VPFI VSO
Batter y current OSC ON Batter y current OSC OFF Supply current Supply current (standby) Input leakage current Input leakage current (PFI) Output leakage current VOUT current (active) VOUT current (battery backup) Input high voltage Input low voltage Batter y voltage Output high voltage(7) Pull-up supply voltage (open drain) VOH (battery backup) Output low voltage Output low voltage (open drain)(9) Power fail deselect PFI input threshold PFI hysteresis Batter y backup switchover
TA = 25C, VCC = 0 V, VBAT = 3 V f = 400 kHz SCL, SDA = VCC 0.3 V or VSS + 0.3 V 0V VIN VCC
1. Valid for ambient operating temperature: TA = 40 to 85C; VCC = 2.7 to 3.6 V (except where noted). 2. Measured with VOUT and ECON open. 3. RSTIN1 and RSTIN2 internally pulled-up to VCC through 100 K resistor. WDI internally pulled-down to VSS through 100 K resistor. 4. Outputs deselected. 5. External SRAM must match RTC supervisor chip VCC specification. 6. For rechargeable backup, VBAT (max) may be considered VCC. 7. For PFO and SQW pins (CMOS). 8. Conditioned output (ECON) can only sustain CMOS leakage current in the battery backup mode. Higher leakage currents will reduce battery life. 9. For IRQ/FT/OUT, RST pins (open drain): if pulled-up to supply other than VCC, this supply must be equal to, or less than 3.0 V when VCC = 0 V (during battery backup mode).
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DC and AC parameters Figure 19. Bus timing requirements sequence
M41ST85W
SDA tBUF tHD:STA tR SCL tHIGH P S tLOW tSU:DAT tHD:DAT tSU:STA SR P tSU:STO tF tHD:STA
AI00589
Table 12.
Symbol f SCL tBUF tEXPD tF tHD:DAT(2) tHD:STA tHIGH tLOW tR tSU:DAT tSU:STA tSU:STO
AC characteristics
Parameter(1) SCL clock frequency Time the bus must be free before a new transmission can start EX to ECON propagation delay SDA and SCL fall time Data hold time START condition hold time (after this period the first clock pulse is generated) Clock high period Clock low period SDA and SCL rise time Data setup time START condition setup time (only relevant for a repeated start condition) STOP condition setup time 100 600 600 0 600 600 1.3 300 Min 0 1.3 15 300 Max 400 Unit kHz s ns ns s ns ns s ns ns ns ns
1. Valid for ambient operating temperature: TA = 40 to 85C; VCC = 2.7 to 3.6 V (except where otherwise noted). 2. Transmitter must internally provide a hold time to bridge the undefined region (300 ns max) of the falling edge of SCL.
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M41ST85W Figure 20. Power down/up mode AC waveforms
VCC VPFD (max) VPFD (min) VSO tF tFB tPD PFO tDR tRB
DC and AC parameters
tR trec
INPUTS
RECOGNIZED
DON'T CARE
RECOGNIZED
RST HIGH-Z OUTPUTS VALID
(PER CONTROL INPUT)
VALID
(PER CONTROL INPUT)
ECON
AI03661
Table 13.
Symbol tF(2) tFB(3) tPD tPFD tR tRB trec
(4)
Power down/up AC characteristics
Parameter(1) VPFD(max) to VPFD(min) VCC fall time VPFD(min) to VSS VCC fall time EX at VIH before power down PFI to PFO propagation delay VPFD(min) to VPFD(max) VCC rise time VSS to VPFD(min) VCC rise time Power-up deselect time 10 1 40 200 Min 300 10 0 15 25 Typ Max Unit s s s s s s ms
1. Valid for ambient operating temperature: TA = 40 to 85C; VCC = 2.7 to 3.6 V (except where otherwise noted). 2. VPFD(max) to VPFD(min) fall time of less than tF may result in deselection/write protection not occurring until 200 s after VCC passes VPFD(min). 3. VPFD(min) to VSS fall time of less than tFB may cause corruption of RAM data. 4. Programmable (see Table 6 on page 28)
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Package mechanical data
M41ST85W
6
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark.
Figure 21. SOH28 28-lead plastic small outline, battery SNAPHAT, package outline
A2 B e A C eB CP
D
N
E
H A1 L
1 SOH-A
Note: Table 14.
Symbol
Drawing is not to scale. SOH28 28-lead plastic small outline, battery SNAPHAT, package mechanical data
millimeters Typ A A1 A2 B C D E e eB H L a N CP 1.27 0.05 2.34 0.36 0.15 17.71 8.23 3.20 11.51 0.41 0 28 0.10 Min Max 3.05 0.36 2.69 0.51 0.32 18.49 8.89 3.61 12.70 1.27 8 0.050 0.002 0.092 0.014 0.006 0.697 0.324 0.126 0.453 0.016 0 28 0.004 Typ inches Min Max 0.120 0.014 0.106 0.020 0.012 0.728 0.350 0.142 0.500 0.050 8
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M41ST85W
Package mechanical data
Figure 22. SH 4-pin SNAPHAT housing for 48 mAh battery & crystal, package outline
A1
A2 A A3
eA D
B eB
L
E
SHTK-A
Note: Table 15.
Symbol
Drawing is not to scale. SH 4-pin SNAPHAT housing for 48 mAh battery & crystal, mechanical data
millimeters Typ A A1 A2 A3 B D E eA eB L 0.46 21.21 14.22 15.55 3.20 2.03 6.73 6.48 Min Max 9.78 7.24 6.99 0.38 0.56 21.84 14.99 15.95 3.61 2.29 0.0181 0.8350 0.5598 0.6122 0.1260 0.0799 0.2650 0.2551 Typ inches Min Max 0.3850 0.2850 0.2752 0.0150 0.0220 0.8598 0.5902 0.6280 0.1421 0.0902
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Package mechanical data
M41ST85W
Figure 23. SH 4-pin SNAPHAT housing for 120 mAh battery & crystal, package outline
A1
A2 A A3
eA D
B eB
L
E
SHTK-A
Note: Table 16.
Symbol
Drawing is not to scale. SH 4-pin SNAPHAT housing for 120 mAh battery & crystal, mechanical data
millimeters Typ A A1 A2 A3 B D E eA eB L 0.46 21.21 17.27 15.55 3.20 2.03 8.00 7.24 Min Max 10.54 8.51 8.00 0.38 0.56 21.84 18.03 15.95 3.61 2.29 0.018 0.835 0.680 0.612 0.126 0.080 0.315 0.285 Typ inches Min Max 0.415 0.335 0.315 0.015 0.022 0.860 0.710 0.628 0.142 0.090
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M41ST85W
Package mechanical data
Figure 24. SOX28 28-lead plastic small outline, 300 mils, embedded crystal, package outline
D
14 1
h x 45
C E H
15
28
A2 B SO-E e A1
A ddd A1 L
Note: Table 17.
Symbol
Drawing is not to scale. SOX28 28-lead plastic small outline, 300 mils, embedded crystal, mechanical data
millimeters Typ A A1 A2 B C D ddd E e H L a N 1.27 7.57 10.16 0.51 0 28 Min 2.44 0.15 2.29 0.41 0.20 17.91 Max 2.69 0.31 2.39 0.51 0.31 18.01 0.10 7.67 10.52 0.81 8 0.050 0.298 0.400 0.020 0 28 Typ inches Min 0.096 0.006 0.090 0.016 0.008 0.705 Max 0.106 0.012 0.094 0.020 0.012 0.709 0.004 0.302 0.414 0.032 8
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Part numbering
M41ST85W
7
Part numbering
Table 18.
Example:
Ordering information scheme
M41ST 85W MH 6 E
Device type M41ST
Supply voltage and write protect voltage 85W = VCC = 2.7 to 3.6 V; 2.55V VPFD 2.70 V Package MH(1) = SOH28 MX(2) = SOX28
Temperature range 6 = 40 to 85C
Shipping method For SOH28: Blank = tubes (Not for New Design - use E) E = ECOPACK package, tubes F = ECOPACK package, tape & reel TR = tape & reel (Not for New Design - use F) For SOX28: Blank = ECOPACK package, tubes TR = ECOPACK package, tape & reel
1. The 28-pin SOIC package (SOH28) requires the SNAPHAT battery/crystal package which is ordered separately under the part number "M4TXX-BR12SHX" in plastic tube or "M4Txx-BR12SHXTR" in tape & reel form (see Table 19). 2. The SOX28 package includes an embedded 32,768 Hz crystal.
Caution:
Do not place the SNAPHAT battery package "M4Txx-BR12SH" in conductive foam as it will drain the lithium button-cell battery.
For other options, or for more information on any aspect of this device, please contact the ST sales office nearest you. Table 19. SNAPHAT battery/crystal table
Description Lithium battery (48 mAh) and crystal SNAPHAT top Lithium battery (120 mAh) and crystal SNAPHAT top
Part number M4T28-BR12SH M4T32-BR12SH
Package SH SH
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M41ST85W
Environmental information
8
Environmental information
Figure 25. Recycling symbols
This product contains a non-rechargeable lithium (lithium carbon monofluoride chemistry) button cell battery fully encapsulated in the final product. Recycle or dispose of batteries in accordance with the battery manufacturer's instructions and local/national disposal and recycling regulations. Please refer to the following web site address for additional information regarding compliance statements and waste recycling. Go to www.st.com/rtc, then select "Lithium Battery Recycling" from "Related Topics".
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Revision history
M41ST85W
9
Table 20.
Date Aug-2000
Revision history
Document revision history
Revision 1 1.1 1.2 2 First issue Block Diagram added (Figure 4) trec Table removed, cross references corrected Reformatted, TOC added, and PFI Input Leakage Current added (Table 11) Addition of trec information, table changed, one added (Table 2, 6); changed PFI/PFO graphic (see Figure 4); change to DC and AC Characteristics, Order Information (Table 11, 12, 18); note added to "Setting Alarm Clock Registers" section; added temp./voltage info. to tables (Table 10, 11, 6, 12, 13); addition of Default Values (Table 7) Note added to Clock Operation section Change in Product Maturity Improve text in "Setting the Alarm Clock" section Change VPFD values in document DC Characteristics VBAT changed; VOHB changed; PFI Hysteresis (PFI Rising) spec. added; and Crystal Electrical Characteristics table removed (Table 11, 6) Changed READ/WRITE Mode Sequences (Figure 10, 12); change in VPFD lower limit for 5V (M41ST85Y) part only (Table 11, 18) Change trec Definition (Table 6); modify reflow time and temperature footnote (Table 8) Modify DC Characteristics table footnote, Default Values (Table 11, 7) Added embedded crystal (MX) package option; corrected initial power-up condition (cover page, Figure 1, 3, 4, 5, 24, Table 1, 7, 18, ) Update diagrams (Figure 4, 5, 24); update values (Table 13, 5, 6, 7, ) New Si changes (Table 13, 5, 6); corrected dimensions (Figure 24; Table ) Reformatted; correct dimensions; update Lead-free information (Figure 20, 13, 16; Table 8, 16, 18) Update characteristics; add package shipping (Figure 3; Table 1, 11, 18) Update Maximum ratings (Table 8) Updated template, Lead-free text, removed 5V references (Figure 1, 2, 3, 4, 5; Table 5, 8, 9, 11, 12, 13, 18, 19) Reformatted document, some text changes; added lead-free second level interconnect information to cover page and Section 6: Package mechanical data; updated Table 8. Added Section 8: Environmental information; updated Table 8, Section 6: Package mechanical data; minor reformatting. Changes
24-Aug-2000 12-Oct-2000 18-Dec-2000
18-Jun-2001
2.1
22-Jun-2001 26-Jul-2001 07-Aug-2001 20-Aug-2001 06-Sep-2001 03-Dec-2001 01-May-2002 03-Jul-2002 15-Nov-2002 24-Jan-2003 25-Feb20-03 20-May-2004 15-Jun-2004 13-Sep-2004 10-Jan-2006 03-Oct-2007 16-Dec-2008
2.2 3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 4 5 6 7 8 9 10
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M41ST85W
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