M41T80
Serial access Real Time Clock with alarm
Feature summary
Counters for tenths/hundredths of seconds, seconds, minutes, hours, day, date, month, year, and century 32KHz crystal oscillator integrating load capacitance (12.5pF) providing exceptional oscillator stability and high crystal series resistance operation Serial interface supports I2C bus (400kHz) 2.0 to 5.5V clock operating voltage 32KHz square wave on power-up to drive a microcontroller in low power mode Programmable (1Hz to 32KHz) square wave
Programmable Alarm and Interrupt function
8 1
SO8 (M) 8-pin SOIC
Low operating current of 200A Operating temperature of 40 to 85C ECOPACK package available
August 2006
Rev 3
1/25
www.st.com 1
Contents
M41T80
Contents
1 2 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 2-Wire bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1.1 2.1.2 2.1.3 2.1.4 2.1.5 Bus not busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Star t data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Stop data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Data valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 2.3
READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3
Clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1 3.2 3.3 3.4 3.5 3.6 Clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Setting alarm clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Full-time 32kHz square wave output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Century bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Output driver pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Preferred power-on default . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4 5 6 7 8
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Package mechanical information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
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M41T80
List of tables
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Clock register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Alarm repeat modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Square wave output frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Preferred power-on default values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Crystal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 SO8 8 lead plastic small outline, 150 mils body width, package mechanical data . . . . . 22 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
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List of figures
M41T80
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 8-pin SOIC connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Serial bus data transfer sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Acknowledgement sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Bus timing requirements sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Slave address location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 READ mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Alternative READ mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 WRITE mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Alarm interrupt reset waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 SO8 8 lead plastic small outline, 150 mils body width, package mechanical drawing. . . 22
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M41T80
Summary description
1
Summary description
The M41T80 is a low power Serial RTC with a built-in 32.768kHz oscillator (external crystal controlled). Eight registers (see Table 3: Clock register map on page 14) are used for the clock/calendar function and are configured in binary coded decimal (BCD) format. An additional 12 registers provide status/control of Alarm, 32kHz output, and Square Wave functions. Addresses and data are transferred serially via a two line, bi-directional I2C interface. The built-in address register is incremented automatically after each WRITE or READ data byte. Functions available to the user include a time-of-day clock/calendar, Alarm interrupts, 32kHz output, and programmable Square Wave output. The eight clock address locations contain the century, year, month, date, day, hour, minute, second and tenths/hundredths of a second in 24 hour BCD format. Corrections for 28, 29 (leap year - valid until year 2100), 30 and 31 day months are made automatically. The M41T80 is supplied in an 8-pin SOIC. Figure 1. Logic diagram
VCC
XI XO M41T80 SCL SDA F32k IRQ/OUT/SQW
VSS
AI07005
Table 1.
Signal names
XI XO IRQ/OUT/SQW SDA SCL F32k VCC VSS Oscillator input Oscillator output Interrupt / output driver / square wave (open drain) Serial data input/output Serial clock input 32kHz square wave output (open drain) Supply voltage Ground
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Summary description Figure 2. 8-pin SOIC connections
XI XO F32k(1) VSS 1 2 3 4 8 7 6 5 VCC IRQ/OUT/SQW(1) SCL SDA
AI07006
M41T80
M41T80
1. open drain output.
Figure 3.
Block diagram
REAL TIME CLOCK CALENDAR 32KHz OSCILLATOR
CRYSTAL
RTC W/ALARM
AF IRQ/OUT/SQW(1)
SDA
I2C INTERFACE
SQUARE WAVE
SCL
F32k(1)
AI07007
1. Open drain output
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M41T80
Operation
2
Operation
The M41T80 clock operates as a slave device on the serial bus. Access is obtained by implementing a start condition followed by the correct slave address (D0h). The 20 Bytes contained in the device can then be accessed sequentially in the following order:
1st Byte: tenths/hundredths of a second register 2nd Byte: seconds register 3rd Byte: minutes register 4th Byte: century/hours register 5th Byte: day register 6th Byte: date register 7th Byte: month register 8th Byte: year register 9th Byte: control register 10th Byte: 32kE bit 11th - 16th Bytes: alarm registers 17th - 19th Bytes: reserved 20th Byte: square wave register
2.1
2-Wire bus characteristics
The bus is intended for communication between different IC's. It consists of two lines: a bidirectional data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must be connected to a positive supply voltage via a pull-up resistor. The following protocol has been defined:
Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is High. Changes in the data line, while the clock line is High, will be interpreted as control signals.
Accordingly, the following bus conditions have been defined:
2.1.1
Bus not busy
Both data and clock lines remain High.
2.1.2
Start data transfer
A change in the state of the data line, from high to Low, while the clock is High, defines the START condition.
2.1.3
Stop data transfer
A change in the state of the data line, from Low to High, while the clock is High, defines the STOP condition.
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Operation
M41T80
2.1.4
Data valid
The state of the data line represents valid data when after a start condition, the data line is stable for the duration of the high period of the clock signal. The data on the line may be changed during the Low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a start condition and terminated with a stop condition. The number of data bytes transferred between the start and stop conditions is not limited. The information is transmitted byte-wide and each receiver acknowledges with a ninth bit. By definition a device that gives out a message is called "transmitter," the receiving device that gets the message is called "receiver." The device that controls the message is called "master." The devices that are controlled by the master are called "slaves."
2.1.5
Acknowledge
Each byte of eight bits is followed by one Acknowledge Bit. This Acknowledge Bit is a low level put on the bus by the receiver whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed is obliged to generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is a stable Low during the High period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master receiver must signal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this case the transmitter must leave the data line High to enable the master to generate the STOP condition.
Figure 4.
Serial bus data transfer sequence
DATA LINE STABLE DATA VALID
CLOCK
DATA
START CONDITION
CHANGE OF DATA ALLOWED
STOP CONDITION
AI00587
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M41T80 Figure 5. Acknowledgement sequence
START SCL FROM MASTER 1 2 8
Operation
CLOCK PULSE FOR ACKNOWLEDGEMENT 9
DATA OUTPUT BY TRANSMITTER
MSB
LSB
DATA OUTPUT BY RECEIVER
AI00601
Figure 6.
Bus timing requirements sequence
SDA tBUF tHD:STA tR SCL tHIGH P S tLOW tSU:DAT tHD:DAT tSU:STA SR P tSU:STO tF tHD:STA
AI00589
9/25
Operation Table 2.
Sym fSCL tLOW tHIGH tR tF tHD:STA tSU:STA tSU:DAT(2) tHD:DAT tSU:STO tBUF
M41T80 AC characteristics
Parameter(1) SCL clock frequency Clock low period Clock high period SDA and SCL rise time SDA and SCL fall time START condition hold time (after this period the first clock pulse is generated) START condition setup time (only relevant for a repeated start condition) Data setup time Data hold time STOP condition setup time Time the bus must be free before a new transmission can start 600 600 100 0 600 1.3 Min 0 1.3 600 300 300 Typ Max 400 Units kHz s ns ns ns ns ns ns s ns s
1. Valid for Ambient Operating Temperature: TA = 40 to 85C; VCC = 2.0 to 5.5V (except where noted). 2. Transmitter must internally provide a hold time to bridge the undefined region (300ns max) of the falling edge of SCL.
2.2
READ mode
In this mode the master reads the M41T80 slave after setting the slave address (Figure 8: READ mode sequence). Following the WRITE Mode Control Bit (R/W=0) and the Acknowledge Bit, the word address 'An' is written to the on-chip address pointer. Next the START condition and slave address are repeated followed by the READ Mode Control Bit (R/W=1). At this point the master transmitter becomes the master receiver. The data byte which was addressed will be transmitted and the master receiver will send an Acknowledge Bit to the slave transmitter. The address pointer is only incremented on reception of an Acknowledge Clock. The M41T80 slave transmitter will now place the data byte at address An+1 on the bus, the master receiver reads and acknowledges the new byte and the address pointer is incremented to "An+2." This cycle of reading consecutive addresses will continue until the master receiver sends a STOP condition to the slave transmitter. The system-to-user transfer of clock data will be halted whenever the address being read is a clock address (00h to 07h). The update will resume due to a Stop Condition or when the pointer increments to any non-clock address (08h-13h).
Note:
This is true both in READ Mode and WRITE Mode. An alternate READ Mode may also be implemented whereby the master reads the M41T80 slave without first writing to the (volatile) address pointer. The first address that is read is the last one stored in the pointer (see Figure 9: Alternative READ mode sequence).
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M41T80 Figure 7. Slave address location
R/W
Operation
START
SLAVE ADDRESS
A
MSB
1
1
0
1
0
0
LSB 0
AI00602
Figure 8.
READ mode sequence
START START R/W R/W
BUS ACTIVITY: MASTER
SDA LINE
S
WORD ADDRESS (An) ACK
S
DATA n
DATA n+1
ACK
ACK
ACK
BUS ACTIVITY: SLAVE ADDRESS
SLAVE ADDRESS STOP
DATA n+X
P
AI00899
Figure 9.
Alternative READ mode sequence
START
NO ACK
BUS ACTIVITY: MASTER SDA LINE
S
ACK
R/W
DATA n
ACK
DATA n+1
ACK ACK
DATA n+X
P
NO ACK
BUS ACTIVITY: SLAVE ADDRESS
AI00895
STOP
ACK
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Operation
M41T80
2.3
WRITE mode
In this mode the master transmitter transmits to the M41T80 slave receiver. Bus protocol is shown in Figure 10: WRITE mode sequence on page 12. Following the START condition and slave address, a logic '0' (R/W=0) is placed on the bus and indicates to the addressed device that word address "An" will follow and is to be written to the on-chip address pointer. The data word to be written to the memory is strobed in next and the internal address pointer is incremented to the next address location on the reception of an acknowledge clock. The M41T80 slave receiver will send an acknowledge clock to the master transmitter after it has received the slave address see Figure 7: Slave address location on page 11 and again after it has received the word address and each data byte.
Figure 10. WRITE mode sequence
START
BUS ACTIVITY: MASTER
R/W
SDA LINE
S
WORD ADDRESS (An)
DATA n
DATA n+1
DATA n+X
P
ACK
ACK
ACK
ACK
BUS ACTIVITY: SLAVE ADDRESS
AI00591
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ACK
STOP
M41T80
Clock operation
3
Clock operation
The M41T80 is driven by a quartz-controlled oscillator with a nominal frequency of 32,768Hz. The accuracy of the Real Time Clock depends on the frequency of the quartz crystal that is used as the time-base for the RTC. The 20-byte Register Map (see Table 3: Clock register map on page 14) is used to both set the clock and to read the date and time from the clock, in a binary coded decimal format. Tenths/Hundredths of Seconds Minutes, and Hours are contained within the first four registers.
Note:
A WRITE to any clock register will result in the Tenths/Hundredths of Seconds being reset to "00," and Tenths/Hundredths of Seconds cannot be written to any value other than "00." Bits D6 and D7 of Clock Register 03h (Century/Hours Register) contain the CENTURY ENABLE Bit (CEB) and the CENTURY Bit (CB). Setting CEB to a '1' will cause CB to toggle, either from '0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial state). If CEB is set to a '0,' CB will not toggle. Bits D0 through D2 of Register 04h contain the Day (day of week). Registers 05h, 06h, and 07h contain the Date (day of month), Month and Years. The ninth clock register is the Control Register. Bit D7 of Register 01h contains the STOP Bit (ST). Setting this bit to a '1' will cause the oscillator to stop. If the device is expected to spend a significant amount of time on the shelf, the oscillator may be stopped to reduce current drain. When reset to a '0' the oscillator restarts within four seconds (typically one second). The eight Clock Registers may be read one byte at a time, or in a sequential block. Provision has been made to assure that a clock update does not occur while any of the eight clock addresses are being read. If a clock address is being read, an update of the clock registers will be halted. This will prevent a transition of data during the READ.
3.1
Clock registers
The M41T80 offers 20 internal registers which contain Clock, Alarm, 32kHz, Flag, Square Wave, and Control data. These registers are memory locations which contain external (user accessible) and internal copies of the data (usually referred to as BiPORTTM cells). The external copies are independent of internal functions except that they are updated periodically by the simultaneous transfer of the incremented internal copy. The internal divider (or clock) chain will be reset upon the completion of a WRITE to any clock address. The system-to-user transfer of clock data will be halted whenever the address being read is a clock address (00h to 07h). The update will resume either due to a Stop Condition or when the pointer increments to any non-clock address (08h-13h). Clock and Alarm Registers store data in BCD. Control, 32kHz, and Square Wave Registers store data in Binary Format.
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Clock operation Table 3.
Addr D7 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h OUT 32kE AFE RPT4 RPT3 RPT2 RPT1 0 0 0 0 RS3 ST 0 CEB 0 0 0 CB 0 0 0 0 D6 D5 D4 D3 D2 D1 D0
M41T80 Clock register map(1)
Function/range BCD format 10s/100s of seconds Seconds Minutes Century/ hours Day Date Month Year 0 0 0 0 Control 32kHz Al month Al date Al hour Al min Al sec 0 0 0 0 0 Flags Reserved Reserved Reserved SQW 01-12 01-31 00-23 00-59 00-59 00-99 00-59 00-59 0-1/00-23 01-7 01-31 01-12 00-99
0.1 seconds 10 seconds 10 minutes 10 hours 0 0 10 date 10M 0
0.01 seconds Seconds Minutes Hours (24 hour format) Day of week Date: day of month Month Year 0 0 Al 10M 0 0 0 0
10 years 0 0 SQWE RPT5 0 0 0 0
Alarm month Alarm date Alarm hour Alarm minutes Alarm seconds 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
AI 10 date AI 10 hour
Alarm 10 minutes Alarm 10 seconds AF 0 0 0 RS2 0 0 0 0 RS1 0 0 0 0 RS0
1. Keys: ST = Stop Bit 0 = Must be set to '0' 32kE = 32kHz Enable Bit CEB = Century Enable Bit CB = Century Bit OUT = Output level AFE = Alarm Flag Enable Flag RPT1-RPT5 = Alarm Repeat Mode Bits AF = Alarm Flag (Read only) SQWE = Square Wave Enable RS0-RS3 = SQW Frequency
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M41T80
Clock operation
3.2
Setting alarm clock registers
Address locations 0Ah-0Eh contain the alarm settings. The alarm can be configured to go off at a prescribed time on a specific month, date, hour, minute, or second or repeat every year, month, day, hour, minute, or second. Bits RPT5-RPT1 put the alarm in the repeat mode of operation. Table 4: Alarm repeat modes shows the possible configurations. Codes not listed in the table default to the once per second mode to quickly alert the user of an incorrect alarm setting. When the clock information matches the alarm clock settings based on the match criteria defined by RPT5-RPT1, the AF (Alarm Flag) is set. If AFE (Alarm Flag Enable) is also set (and SQWE is '0.'), the alarm condition activates the IRQ/OUT/SQW pin.
Note:
If the address pointer is allowed to increment to the Flag Register address, an alarm condition will not cause the Interrupt/Flag to occur until the address pointer is moved to a different address. It should also be noted that if the last address written is the "Alarm Seconds," the address pointer will increment to the Flag address, causing this situation to occur. The IRQ/OUT/SQW output is cleared by a READ to the Flags Register as shown in Figure Figure 11. A subsequent READ of the Flags Register is necessary to see that the value of the Alarm Flag has been reset to '0.' Figure 11. Alarm interrupt reset waveform
0Eh 0Fh 10h
ACTIVE FLAG
IRQ/OUT/SQW
HIGH-Z
AI07021
Table 4.
RPT5 1 1 1 1 1 0
Alarm repeat modes
RPT4 1 1 1 1 0 0 RPT3 1 1 1 0 0 0 RPT2 1 1 0 0 0 0 RPT1 1 0 0 0 0 0 Alarm setting Once per second Once per minute Once per hour Once per day Once per month Once per year
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Clock operation Table 5. Square wave output frequency
Square wave bits RS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 RS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 RS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 RS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Square wave Frequency None 32.768 8.192 4.096 2.048 1.024 512 256 128 64 32 16 8 4 2 1
M41T80
Units kHz kHz kHz kHz kHz Hz Hz Hz Hz Hz Hz Hz Hz Hz Hz
3.3
Full-time 32kHz square wave output
The M41T80 offers the user a special 32kHz square wave function which defaults to output on the F32k pin (Pin 3) as long as VCC is valid, and the oscillator is running (ST Bit = '0'). This function is available within four seconds of initial power-up and can only be disabled by setting the 32kE Bit to '0' or the ST Bit to '1.' If not used, the F32k pin should be disconnected and allowed to float.
Note:
The F32k pin is an open drain which requires an external pull-up resistor.
3.4
Century bit
Bits D7 and D6 of Clock Register 03h contain the CENTURY ENABLE Bit (CEB) and the CENTURY Bit (CB). Setting CEB to a '1' will cause CB to toggle, either from a '0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial state). If CEB is set to a '0,' CB will not toggle.
16/25
M41T80
Clock operation
3.5
Output driver pin
When the AFE Bit and SQWE Bit are not set, the IRQ/OUT/SQW pin becomes an output driver that reflects the contents of D7 of the Control Register. In other words, when D7 (OUT Bit) of address location 08h is a '0,' then the IRQ/OUT/SQW pin will be driven low.
Note:
The IRQ/OUT/SQW pin is an open drain which requires an external pull-up resistor.
3.6
Preferred power-on default
When powering the device up from ground (0V), the following register bits are set to a '0' state: ST; AFE; and SQWE. The following bits are set to a '1' state: OUT and 32kE (see Table 6: Preferred power-on default values on page 17). Table 6. Preferred power-on default values
Condition Power-up(1) ST 0 Out 1 AFE 0 SQWE 0 32kE 1
1. If VCC falls to a voltage, 0V < VCC < 2.0V, these bits should be rewritten by the user.
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Maximum rating
M41T80
4
Maximum rating
Stressing the device above the rating listed in the "Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 7.
Symbol TSTG VCC TSLD
(1) (2)
Absolute maximum ratings
Parameter Storage temperature (VCC off, oscillator off) Supply voltage Lead solder temperature for 10 seconds Input or output voltages Output current Power dissipation Value 55 to 125 0.3 to 7 260 0.3 to Vcc+0.3 20 1 Unit C V C V mA W
VIO IO PD
1. For SO package, standard (SnPb) lead finish: Reflow at peak temperature of 225C (total thermal budget not to exceed 180C for between 90 to 150 seconds). 2. For SO package, Lead-free (Pb-free) lead finish: Reflow at peak temperature of 260C (total thermal budget not to exceed 245C for greater than 30 seconds).
18/25
M41T80
DC and AC parameters
5
DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the Measurement Conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 8. Operating and AC measurement conditions (1)
Parameter Supply voltage (VCC) Ambient operating temperature (TA) Load capacitance (CL) Input rise and fall times Input pulse voltages Input and output timing ref. voltages
1. Output Hi-Z is defined as the point where data is no longer driven.
M41T80 2.0 to 5.5V 40 to 85C 100pF 50ns 0.2VCC to 0.8 VCC 0.3VCC to 0.7 VCC
Figure 12. AC measurement I/O waveform
0.8VCC
0.7VCC 0.3VCC
AI02568
0.2VCC
Table 9.
Symbol CIN COUT tLP
(3)
Capacitance
Parameter(1) (2) Input capacitance Output capacitance Low-pass filter input time constant (SDA and SCL) Min Max 7 10 50 Unit pF pF ns
1. Effective capacitance measured with power supply at 5V; sampled only, not 100% tested. 2. At 25C, f = 1MHz.
3. Outputs deselected.
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DC and AC parameters Table 10.
Symbol ILI ILO ICC1
M41T80
DC characteristics
Parameter Input leakage current Output leakage current Supply current Test condition(1) 0V VIN VCC 0V VOUT VCC 3.0V Switch freq (SCL) = 400kHz 5.5V 32KE = 1 3.0V or SQWE = 1 5.5V 32KE = 0 3.0V and SQWE = 0 5.5V 0.3 0.7VCC IOL = 3.0mA IOL = 10mA IRQ/out/SQW, F32k 1.8 200 3.0 35 1.5 2.4 31 0.3VCC VCC + 0.3 0.4 0.4 5.5 Min Typ Max 1 1 30 Unit A A A A A A A A V V V V V
ICC2(2)
Supply current (standby)
All inputs = VCC 0.2V Switch freq (SCL) = 0Hz
VIL VIH VOL
Input low voltage Input high voltage Output low voltage Output low voltage (open drain)(3) Pull-up supply voltage (open drain)
1. Valid for Ambient Operating Temperature: TA = 40 to 85C; VCC = 2.0 to 5.5V (except where noted). 2. At 25C. 3. For IRQ/FT/OUT, RST, and 32kHz pins (Open Drain)
Table 11.
Sym fO RS CL
Crystal electrical characteristics
Parameter(1) (2) Resonant frequency Series resistance Load capacitance 12.5 Min Typ 32.768 60 Max Units kHz k pF
1. Externally supplied if using the SO8 package. STMicroelectronics recommends the KDS DT-38: 1TA/1TC252E127, Tuning Fork Type (thru-hole) or the DMX-26S: 1TJS125FH2A212, (SMD) quartz crystal for industrial temperature operations. KDS can be contacted at kouhou@kdsj.co.jp or http://www.kdsj.co.jp for further information on this crystal type. 2. Load capacitors are integrated within the M41T80. Circuit board layout considerations for the 32.768kHz crystal of minimum trace lengths and isolation from RF generating signals should be taken into account.
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M41T80
Package mechanical information
6
Package mechanical information
In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a Lead-free second level interconnect . The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
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Package mechanical information Figure 13. SO8 8 lead plastic small outline, 150 mils body width, package mechanical drawing
h x 45 A2 b e 0.25 mm GAUGE PLANE k
8
M41T80
A ccc c
D
E1
1
E A1 L L1
SO-A
1. Drawing is not to scale.
Table 12.
SO8 8 lead plastic small outline, 150 mils body width, package mechanical data
millimetres inches Max 1.75 0.10 1.25 0.28 0.17 0.48 0.23 0.10 4.90 6.00 3.90 1.27 4.80 5.80 3.80 0.25 0 0.40 1.04 5.00 6.20 4.00 0.50 8 1.27 0.041 0.193 0.236 0.154 0.050 0.189 0.228 0.150 0.010 0 0.016 0.25 0.004 0.049 0.011 0.007 0.019 0.009 0.004 0.197 0.244 0.157 0.020 8 0.050 Typ Min Max 0.069 0.010
Symbol Typ A A1 A2 b c ccc D E E1 e h k L L1 Min
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M41T80
Part numbering
7
Part numbering
Table 13.
Example:
Ordering information scheme
M41T 80 M 6 E
Device type M41T
Supply voltage and write protect voltage 80 = VCC = 2.0 to 5.5V
Package M = SO8
Temperature range 6 = 40C to 85C
Shipping method E = ECOPACK package, standard package F = ECOPACK package, tape & reel 24mm packing
For other options, or for more information on any aspect of this device, please contact the ST Sales Office nearest you.
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Revision history
M41T80
8
Revision history
Table 14.
Date October 2002 15-Jun-04
Revision history
Version 1.0 2.0 First issue Reformatted; add Lead-free information; update characteristics (Table 7, Table 10, Table 13) Changed document to new template; added new features in Feature summary on page 1; updated Package mechanical data in Section 6: Package mechanical information; small text changes for entire document, ecopack compliant Revision details
29-Aug-2006
3
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M41T80
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