STLC2150
BLUETOOTH RADIO TRANSCEIVER
Bluetooth v.1.2 specification compliant Fully integrated single chip: transceiver with minimum of external RF components PLL completely integrated Integrated antenna switch
Supports Power Class 2 and 3 operation with power control Supports Power Class 1 operation with an external Power Amplifie Outstanding maximum usable input signal Interface with base-band: BlueRF compatible unidirectional received data: RxMode2 and RxMode2+ are supported serial interface: JTAG
VFQFPN-48 (7x7x1.0mm) ORDERING NUMBER: STLC2150 Temperature range: -40 to 85 C
CMOS technology Standard VFQFPN-48 package Low standby power consumption Extended temperature range Compliant to automotive specification AEC-Q100
DESCRIPTION
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APPLICATIONS Wireless data transmission applications to 432 Kbps symmetrical or 721 Kbps asymmetrical. Typical applications in which the STLC2150 is used are: Computer peripherals Modems Cameras Portable computers, PDA Handheld data transfer devices Mobile phone Other types of devices that require the wireless communication provided by Bluetooth.
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The STLC2150 is a fully integrated Bluetooth single chip radio transceiver. Together with a BB processor, like STLC2410, it offers a compact and complete solution for short-range wireless connectivity for a variety of applications. The STLC2150 implements a low-IF receiver for Bluetooth modulated input signals and no external IF filtering is required. The GFSK demodulator is fully integrated and supplies digital output data and RSSI. The transmit section features a fully integrated GFSK modulator, followed by a direct up-conversion stage, giving an output signal of 0 dBm. Optional power control is available. On-chip VCO covers full Bluetooth band and contains all of the tank resonator circuitry. Unidirectional BlueRF compatible interface and 4 wires serial JTAG interface are used to control all functions of radio transceiver, enabling operation with wide range of BB processors.
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January 2004
Rev. 2.0
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STLC2150
BLOCK DIAGRAM
A/D VGA A/D
LNA
MIX
IQBPF
RX BRXD DIGITAL PART
POWER & CLOCK CONTROL
ANTENNA
PLL & VCO
BLUE RF
FILTER CALIBRATION
SERIAL PROGRAM INTERFACE
LPF
PA
MIX LPF
DAC SYSTEM
MODULATOR
BTXD
D02TL547
QUICK REFERENCE DATA Table 1. Absolute Maximum Ratings Operation of the device beyond these conditions is not guaranteed. Sustained exposure to these limits will adversely effect device reliability.
Symbol VDD VIN Conditions Power supply Analogue and Digital Core Input voltage on any pin Min VSS - 0.3 VSS - 0.3
VSSDIF VDDIO
Maximum voltage difference between different VSS* pins Power supply for digital I/O
(*) Analogue test and RF pins only.
Table 2. Operating Ranges
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Operating ranges define the limits for functional operation and parametric characteristics of the device. Functionality outside these limits is not implied.
Symbol VDD Conditions Power supply Analogue and Digital Core Power supply for I/O Ambient temperature Min 2.62 2.50 -40 Typ 2.70 Max 2.78 3.60 85 Unit V V C
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Max 3.5 0.3 4.6
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Unit V V
VDD + 0.3 AND < 3.5(*) VDDIO + 0.3 AND < 4.6
-0.3
V V
VSS - 0.3
VDDIO Tamb
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STLC2150
Pin Description and Assignment
Pin# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Pin Name VSS3 AOUTIP AOUTIN AOUTQP AOUTQN LPCLK BDCLK DVDD1 DVSS1 BNDEN BMOSI BMISO RESETN BXTLEN BTXEN BRXEN IOVDD1 CLK13MHZ BTXD BRCLK OTP_ZAP BPKTCTL BRXD BSEN Description Analogue Ground Analogue test output Analogue test output Analogue test output Analogue test output 3.2 or 32 KHz clock output JTAG TCK Digital Core Supply pin Digital Core Ground pin JTAG TMS JTAG TDI JTAG TDO Reset Oscillator enable Tx path enable Rx path enable Digital IO Supply pin 13 MHz output Tx data 1 MHz-clock associated with data OTP ZAP Access code successfully decoded Rx data Synthesizer enable Pin# 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Pin Name XTAL130 XTAL13I VDDXTAL VSS1 VDD1 VDD2 VSS2 VSS6 VDD6 VDD5 VSS5 VDD7 VSS7 AINQN AINQP VDD4 VSS4 RF_N RF_P VSS4 VDD4 AININ AINIP Description 13 MHz Crystal oscillator output pin 13 MHz Crystal oscillator input pin 13 MHz oscillator supply Analogue Ground Analogue Supply Analogue Supply Analogue Ground Analogue Ground Analogue Supply Analogue Supply Analogue Ground Analogue Supply Analogue Ground Analogue test input Analogue test input Analogue Supply Analogue Ground RF antenna connection RF antenna connection
PIN CONNECTION (bottom view)
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VDD7 VSS5 VDD5 VDD6 VSS6 VSS2 VDD2 VDD1 VSS1 35 34 33 32 31 30 29 28 27 26
37 38 39 40 41 42 43 44 45 46 47 48 36 1 2 3 4 5 6 7 8 9 10 11
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AINQN AINQP VDD4 VSS4
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RF_N VSS4 RF_P
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VDD3
AININ VDD3 AINIP
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Analogue Ground Analogue Supply
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Analogue test input Analogue Supply
Analogue test input
VDD4
VSS7
VSS3 AOUTIP AOUTIN AOUTQP AOUTQN LPCLK BDCLK DVDD1 DVSS1 BNDEN BMOSI BMISO
VDDXTAL XTAL13I XTAL13O
12 25 24 23 22 21 20 19 18 17 16 15 14 13
BPKTCTL
OTP_ZAP
BRCLK
BSEN
BRXD
BTXD
CLK13MHZ
IOVDD1
BRXEN
BTXEN
BXTLEN
RESETN
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STLC2150
CURRENT CONSUMPTION Table 3. Typical Current Consumption
Symbol Istby Irx Itx Ivco I32K Parameter Current consumption in standby mode (@27 C) Current consumption in Receive mode Current consumption in Transmit mode Current consumption when only PLL is enabled Current consumption when only the 32-kHz clock oscillator is operating Typ 5 40 66 22 TBD 52 80 TBD TBD Max Unit A mA mA mA A
I/O CELL CHARACTERISTICS Table 4: CMOS DC Electrical characteristics, rated for the operating range
Symbol VIH VIL VOH VOL Vt+ VtHigh Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Schmitt trigger rising threshold Schmitt trigger falling threshold Schmitt trigger minimum hysteresis 1.4 0.5 248 85% of VDDIO 0.4 2.0 1.2 Parameter Min 80% of VDDIO 20% of VDDIO Max Unit V V V V V V mV
APPLICATION REFERENCE DESIGN Figure 1. reference design schematic diagram
2.7V
DVDD LPCLK bdclk bnden bmosi bmiso RESET sys_clk_req btxen brxen BDCLK BNDEN BMOSI BMISO 6 7 10 11 8
DVSS 9
VSS3 1
STLC2410
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xin btxd brclk bpkctl brxd bsen
2.7V C1 100nF
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RESETN BXTLEN 12 13 BTXEN 14 15 BRXEN IOVDD OTP_ZAP CLK13MHZ BTXD BRCLK BPKTCTL BRXD BSEN XTAL13O 16 17 21 18 19 20 22 23 24
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C8 100nF VDD3
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VDD4 45
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40
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2.7V C6 100nF RF_P RF_N
2.7V
C7 100nF VDD4
IMPEDANCE ADAPTATION +BPF 1 2 AINIP AININ VSS4 VSS4 AINQP AINQN VSS7 50
48
43 42
47 46 44 41 39
STLC2150
38 37
27 29 30 33 34 36 2 AOUTIP C3 15pF 3 AOUTIN 4 5 28 VSS1 31 VSS2 32 VSS6 35
VDDXTL VDD1 VDD2 VDD6 VDD5 VDD7 C4 100nF 2.7V
25 26
XTAL13I
AOUTQP AOUTQN
VSS5
C2 15pF
Y1 13MHz
D02TL548A
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STLC2150
FUNCTIONAL DESCRIPTION Receiver The STLC2150 implements a low-IF receiver for Bluetooth modulated input signals. The radio signal is taken from 75 balanced RF input and amplified by an LNA. The mixers are driven by two quadrature signals which are locally generated from a VCO signal running at twice the frequency. The output signals in the I signal path and Q signal path are bandpass filtered by a polyphase bandpass filter for channel filtering and image rejection. The output of the lowpass filters is amplified by a VGA to the optimal input range for the A/D converters. Further filtering is done in digital filters. The digital part demodulates the GFSK coded bit stream by evaluating the phase information in the I and Q signals. The digital part recovers the receive bit clock. It extracts RSSI data by calculating the signal strength. Overall automatic gain amplification in the receive path is controlled by the digital part. Transmitter The transmitter takes the serial input transmit data from the base-band. This data is GFSK modulated to I and Q signals. The Tx bit clock is provided to the base-band for synchronization. The output of the digital part is converted to analogue signals which are lowpass filtered before being sent to direct up-conversion mixers. The quadrature up-conversion mixers use the same LO as the receiver. 0dBm output power at the antenna port is achieved with an internal PA, which has 75 balanced RF output. Optional power control is available. PLL
The on-chip VCO is part of a PLL, the frequency is programmed for the RF channels by the digital part. The tank resonator circuitry for the VCO is completely integrated. Process variations on the VCO center frequency are calibrated out automatically. Also the RC time constants for the analogue lowpass filters are automatically calibrated on chip. Base-band interface
Unidirectional BlueRF compatible interface is used to control all functions of radio transceiver. The unidirectional RXMODE2 is supported. STLC2150 has also the capability to provide the recovered clock and the aligned data to the base-band (Rxmode2+). 4 wires serial JTAG interface is used to access the internal registers. Also JTAG is used to set channel number and read RSSI. Crystal oscillator
The STLC2150 has a crystal oscillator to generate 13 MHz reference clock for internal use and for the baseband chip. Also a 3.2 or 32 kHz clock for low power modes operation can be provided.
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GENERAL SPECIFICATION All the provided values are specified over the operational conditions (VDD and temperature) according to the Bluetooth v.1.2 specification. Receiver To comply with the Bluetooth norm, an external RF filter is required to provide minimum 17dB of attenuation in the bands: 30MHz - 2000MHz and 3000MHz - 12.75GHz. All specification below are measured at the antenna port. The loss between IC inputs and the port is approximately 2dB
Symbol RFin RXsens RXmax Parameter Input frequency range Receiver sensitivity @BER 0.1% (including dirty signal test) Max input signal level @BER 0.1%
3)
Test condition
Min 2402
Typ -77.5 1) >16
Max 2480 -73.7 2)
Unit MHz dBm dBm
Receiver interference Performance @BER 0.1% C/Ico-channel C/I1MHz C/I2MHz C/I3MHz C/Iimage C/Iimage1MHz Co-channel interference Adjacent (1MHz) interference Adjacent (2MHz) interference Adjacent (3MHz) interference Image interference Adjacent (1MHz) to image interference 30 MHz 2000 MHz 3000 MHz 12.75 GHz 2000 MHz 2400 MHz 2500 MHz 3000 MHz Input referred IP3
@ Input signal strength = -60 dBm @ Input signal strength = -60 dBm @ Input signal strength = -60 dBm @ Input signal strength = -67 dBm @ Input signal strength = -67 dBm @ Input signal strength = -67 dBm
10 -1 -36 -50 -25 -40
11 0 -30 -42 -11 -28
dB dB dB dB dB dB
Receiver blocking @BER 0.1% RXB_1 RXB_2
@ input signal strength = -67 dBm @ input signal strength = -67dBm
Receiver intermodulation RXIIP3
1) Sensitivity at chip pins is -79.5 dBm. 2) Guarantied over process variation and full temperature range -40 to +85C. 3) Without any exception.
RSSI Extraction
The RSSI extraction block allows to determine the Received Signal Strength. The indicator output is an 8-bit word, indicating the signal strength in dBm
Symbol
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RSSI_AC RSSI_R
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Interferers at 39 dBm, intended channel at 64 dBm, BER < 0.1%
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-10 -27
dBm dBm
-7.5
-11.5
dBm
Parameter
Test condition / notes Signal power = -70 dBm Range upwards from 70 dBm
Min
Typ 4
Max
Unit dB dB dB/bit
RSSI accuracy RSSI range RSSI Resolution RSSI reference point
20
40 0.37
RSSI_RES RSSI_REF
signal power = -64 dBm
107
The RSSI value is stored in the RSSI register. The value is latched when the base-band sends the access code recognition signal (BPKTCTL) and is kept unchanged until the next RX active slot. The register can be read by the base-band at any time
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STLC2150
Transmitter All output power specifications are given at the antenna port, with a bandpass filter and matching network in between the port and the IC. The loss between antenna port and IC output is approximately 2 dB
Symbol RFout TXPout Parameter Output frequency range Nominal output power Test condition Min 2402 -6 0 Typ Max 2480 +4 Unit MHz dBm
Bluetooth frequency band
@ 2402 2480 MHz
In-band spurious emission TX_SE1 TX_SE2 TX_SE3 Frequency offset = 550kHz Channel offset = 2 Channel offset 3 Measured in a 100 kHz bandwidth -26 -51 -62 -20 dBc dBm dBm
Out-of-band spurious emission TX_SE4 Emission in the 30 MHz 1 GHz band Emission in the 1 GHz 12.75 GHz band Emission in the 1.8 GHz 1.9 GHz band Emission in the 5.15 GHz 5.3 GHz band Operation mode Idle mode TX_SE5 Operation mode Idle mode TX_SE6 Operation mode Idle mode TX_SE7 Operation mode Idle mode -65 -65 -58 -65 -65 dBm dBm
PLL
The centre frequency of the radio transmit or receive channel is controlled by a PLL. The selected radio channel centre frequency is given by: Fc = 2.400GHz + n*1 MHz, where "n" is a 7-bit channel control word, ranging from 2 to 97
Symbol Fref
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VCOset Fd
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Exter nal reference clock From Channel selection to LOCK = H
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Parameter
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dBm
-65 -65
dBm
Test condition
Min -20ppm
Typ 13.000 40 100
Max +20ppm 100
Unit MHz s Hz/s
VCO settling time after power up
Transmitter frequency drift
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STLC2150
Crystal oscillator An on-chip crystal oscillator provides a 13MHz master clock. The external crystal must be connected to the pads XTAL13I and XTAL13O. The frequency specification of 20 ppm can be achieved by 2 different ways: 1. by external components choice (default); 2. by internal tuning (with internal capacitors as defined by the control word stored in the registers. The control word allows modifying the value of the capacitor connected to the oscillator pads. The total capacitance (including the parasitic capacitors) must be about 16 pF. The variable capacitor is implemented as a capacitor array of about 255 x 90 fF. External crystal example
Parameter Frequency Mode Drive level Temp drift Value 13.0 0 00 Fundamental 100 10 W ppm 20 Referred to value at 25C over temperature range 1) max 1% ma x 20 % 24 % min Unit M Hz tolerance 10 ppm At 25 C 3 C Comment
Aging Cload Rseries C0 C1 Rins Pull_sens Activity Dips
1)
1 16.0 40 1.7 6.5 500 10 0.5
Ppm/year pF pF pF M Ppm
Ppm / C
Temperaure range is defined by application needs.
Low power clock
The STLC2150 can provide 3.2 or 32 KHz, low power clock for baseband chip operation in Hold, Snif and Park modes. External reference frequency
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The STLC2150 can take a digital clock from external source 13 MHz on the CLK13MHZ pin. The IC also can use an analogue (sine wave, from 0.2 up to 1 Vpp) clock from external 13 MHz source on the XTAL13I pin. Registers description To provide operational control, configuration flexibility (e.g. clock configuration, XTAL trimming) and to set maximum performance the STLC2150 has a bank of registers. Detailed description is available in "STLC2150: Interface and Programming Guide".
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20 % max
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(16 pF)
Shunt capacitance Motional capacitance
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Insulation resistance
Temperature range 1)
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STLC2150
mm DIM. M IN. A A1 A2 A3 b D D2 E E2 e L ddd 0.180 6.850 2.250 6.850 2.250 0.450 0.300 0.800 TYP. 0.900 0.020 0.650 0.250 0.230 7.000 4.700 7.000 4.700 0.500 0.400 0.300 7.150 5.250 7.150 5.250 0.550 0.500 0.080 0.007 0.269 0.088 0.269 0.088 0.018 0.012 MAX . 1.000 0.050 1.000 MIN. 0.031
inch TYP. 0.035 MA X. 0.039
OUTLINE AND MECHANICAL DATA
0.0008 0.0019 0.025 0.01 0.009 0.275 0.185 0.275 0.185 0.020 0.016 0.012 0.281 0.207 0.281 0.207 0.022 0.020 0.003 0.039
VFQFPN-48 (7x7x1.0mm) Very Fine Quad Flat Package No lead
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7446345_A
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STLC2150
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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The ST logo is a registered trademark of STMicroelectronics.
The BLUETOOTH word mark and logos are owned by the Bluetooth SIG, Inc. and any use of such marks by STMicroelectronics is under license. All other names are the property of their respective owners 2004 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com
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