ST7MC1xx/ST7MC2xx
8-bit MCU with nested interrupts, Flash, 10-bit ADC, brushless motor control, five timers, SPI, LINSCITM
Features
Memories 8K to 60K dual voltage FLASH Program memory or ROM with read-out protection capability, In-Application Programming and In-Circuit Programming. 384 to 1.5K RAM HDFlash endurance: 100 cycles, data retention: 40 years at 85C Clock, reset and supply management Enhanced reset system Enhanced low voltage supervisor (LVD) for main supply and auxiliary voltage detector (AVD) with interrupt capability Clock sources: crystal/ceramic resonator oscillators and by-pass for external clock, clock security system. Four power saving modes: Halt, Active-Halt, Wait and Slow Interrupt management Nested interrupt controller 14 interrupt vectors plus TRAP and RESET MCES top level interrupt pin 16 external interrupt lines (on 3 vectors) Up to 60 I/O ports up to 60 multifunctional bidirectional I/O lines up to 41 alternate function lines up to 12 high sink outputs 5 timers Main Clock Controller with: Real time base, Beep and Clock-out capabilities Configurable window watchdog timer Two 16-bit timers with: 2 input captures, 2 output compares, external clock input, PWM and pulse generator modes 8-bit PWM Auto-Reload timer with: 2 input captures, 4 PWM outputs, output compare and time base interrupt, external clock with Table 1. Device summary

LQFP80 14 x 14

LQFP 64 14 x 14

LQFP44 10 x 10

LQFP32 7x 7

event detector 2 Communication interfaces SPI synchronous serial interface LINSCITM asynchronous serial interface Brushless motor control peripheral 6 high sink PWM output channels for sinewave or trapezoidal inverter control Motor safety including asynchronous emergency stop and write-once registers 4 analog inputs for rotor position detection (sensorless/hall/tacho/encoder) Permanent magnet motor coprocessor including multiplier, programmable filters, blanking windows and event counters Operational amplifier and comparator for current/voltage mode regulation and limitation Analog peripheral 10-bit ADC with 16 input pins In-circuit Debug Instruction set 8-bit Data Manipulation 63 Basic Instructions with illegal opcode detection 17 main Addressing Modes 8 x 8 Unsigned Multiply Instruction True Bit Manipulation Development tools Full hardware/software development package

Features
Program memory - bytes RAM (stack) - bytes Peripherals Operating Supply vs. Frequency

ST7MC1K2 / ST7MC1K4
8K 384 (256)

ST7MC2N6 1)/ ST7MC2S4 / ST7MC2S6 / ST7MC2S7 / ST7MC2S9 / ST7MC2R6 / ST7MC2R7 / ST7MC2R9 / ST7MC2M9

16K 16K 32K 48K 60K 768 (256) 768 (256) 1024 (256) 1536 (256) Watchdog, 16-bit Timer A, LINSCITM, 10-bit ADC, MTC, 8-bit PWM ART, ICD SPI, 16-bit Timer B 4.5 to 5.5V with fCPU8MHz -40C to +85C LQFP32 -40C to +85C -40C to +85 C -40C to +125C 1)/LQFP64 LQFP64/44 LQFP80/64 LQFP44 SDIP56 -40C to +125C LQFP44

-40C to +85C Temperature Range /-40C to +125C Package LQFP32 Note 1: For development only. No production

September 2008

Rev 12

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Table of Contents
1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.2 4.3 4.4 4.5 4.6 4.7 4.8 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 STRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 ICP (IN-CIRCUIT PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 IAP (IN-APPLICATION PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.2 5.3 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.1 OSCILLATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.2 6.3 6.4 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 SYSTEM INTEGRITY MANAGEMENT (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK AND BEEPER (MCC/RTC) . 37

7 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.2 7.3 7.4 7.5 7.6 7.7 MASKING AND PROCESSING FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 CONCURRENT & NESTED MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 INTERRUPT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 EXTERNAL INTERRUPT CONTROL REGISTER (EICR) . . . . . . . . . . . . . . . . . . . . . . . 47

8 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 8.2 8.3 8.4 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 ACTIVE-HALT AND HALT MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

9 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 9.2 9.3 9.4 9.5 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 309 10 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 10.1 WINDOW WATCHDOG (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

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10.2 PWM AUTO-RELOAD TIMER (ART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 10.3 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 10.4 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 10.5 LINSCI SERIAL COMMUNICATION INTERFACE (LIN MASTER/SLAVE) . . . . . . . . . 107 10.6 MOTOR CONTROLLER (MTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 10.7 OPERATIONAL AMPLIFIER (OA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 10.8 10-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 11 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 11.1 CPU ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 11.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 12 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 12.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 12.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 12.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 12.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 12.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 12.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 12.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 12.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 12.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 12.10 TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 12.11 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 271 12.12 MOTOR CONTROL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 12.13 OPERATIONAL AMPLIFIER CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 12.14 10-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 13 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 13.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 13.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 13.3 SOLDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 14 ST7MC DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . 290 14.1 FLASH OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 14.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . 292 14.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 14.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 15 IMPORTANT NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 15.1 FLASH/FASTROM DEVICES ONLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 15.2 CLEARING ACTIVE INTERRUPTS OUTSIDE INTERRUPT ROUTINE . . . . . . . . . . . . 300 15.3 TIMD SET SIMULTANEOUSLY WITH OC INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . 300 15.4 LINSCI LIMITATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 15.5 MISSING DETECTION OF BLDC "Z EVENT" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 15.6 INJECTED CURRENT ON PD7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303

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15.7 RESET VALUE OF UNAVAILABLE PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 15.8 MAXIMUM VALUES OF AVD THRESHOLDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 15.9 EXTERNAL INTERRUPT MISSED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 16 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307

To obtain the most recent version of this datasheet, please check at www.st.com>products>technical literature>datasheet

Please also pay special attention to the Section "IMPORTANT NOTES" on page 299.

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ST7MC1xx/ST7MC2xx

1 INTRODUCTION
The ST7MCx device is member of the ST7 microcontroller family designed for mid-range applications with a Motor Control dedicated peripheral. All devices are based on a common industrystandard 8-bit core, featuring an enhanced instruction set and are available with FLASH, ROM or FASTROM program memory. Under software control, all devices can be placed in WAIT, SLOW, ACTIVE-HALT or HALT mode, reducing power consumption when the application is in idle or stand-by state. The enhanced instruction set and addressing modes of the ST7 offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code. In addition to standard 8-bit data management, all ST7 microcontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes. The devices feature an on-chip Debug Module (DM) to support in-circuit debugging (ICD). For a description of the DM registers, refer to the ST7 ICC Protocol Reference Manual.

Figure 1. Device Block Diagram
8-BIT CORE ALU RESET VPP VSS VDD CONTROL PROGRAM MEMORY (8K - 60K Bytes) RAM (384 - 1536Bytes) PORT H 1) PH7:0 1) (8-bits) PG7:0 1) (8-bits)

LVD AVD

OSC1 OSC2

OSC ADDRESS AND DATA BUS SCI/LIN

PORT G 1)

WATCHDOG PWM ART PORT A

PORT D PD7:0 (8-bits) TIMER A 10-BIT ADC VAREF VSSA PORT E1 PE5:0 (6-bits) TIMER B1

PA7:0 1) (8-bits)

PORT B MTC VOLT INPUT SPI1 PB7:0 (8-bits)

PORT C PORT PF5:0 (6-bits) F1 PC7:0 (8-bits) MOTOR CONTROL MCES MCC/RTC/BEEP1 DEBUG MODULE

On some devices only, see Table 1, "ST7MC Device Pin Description," on page 12

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ST7MC1xx/ST7MC2xx

2 PIN DESCRIPTION
Figure 2. 80-Pin LQFP 14x14 Package Pinout

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

MCO2 (HS) MCO1 (HS) MCO0 (HS) VPP/ICCSEL PE5 PE4 / EXTCLK_B PE3 / ICAP1_B PE2 / ICAP2_B PE1 / OCMP1_B PE0 (HS) / OCMP2_B PH7 PH6 PH5 PH4 VDD_2 VSS_2 PD7 (HS) / TDO PD6 (HS) / RDI PD5 / AIN15 / ICCDATA PD4 /EXTCLK_A / AIN14 / ICCCLK

(HS) MCO3 (HS) MCO4 (HS) MCO5 MCES PG0 PG1 PG2 PG3 OSC1 OSC2 VSS_1 VDD_1 PWM3 / PA0 PWM2 / (HS) PA1 PWM1 / PA2 AIN0 / PWM0 / PA3 ARTCLK / (HS) PA4 AIN1 / ARTIC1 / PA5 ARTIC2 / PA6 AIN2 / PA7

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

ei0

ei1

ei1

ei2

ei2

60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41

PD3 / ICAP1_A / AIN13 PD2 / ICAP2_A / AIN12 PD1 (HS) / OCMP1_A PD0 / OCMP2_A / AIN11 PH3 PH2 PH1 PH0 PF5 (HS) PF4 (HS)

PF3 (HS) / BEEP
PF2 / MCO / AIN10 PF1 / MCZEM / AIN9 PF0 / MCDEM / AIN8 RESET

VDD_0
VSS_0 VSSA VAREF PC7 / MCPWMW / AIN7

MCVREF / PB0 MCIA / PB1 MCIB / PB2 MCIC / PB3 MISO / PB4 AIN3 / MOSI / PB5 SCK / (HS) PB6 AIN4 /SS /(HS) PB7 PG4 PG5 PG6 PG7

(HS) 20mA high sink capability eix associated external interrupt vector * Once the MTC peripheral is ON, the pin PC4 is configured to an alternate function. PC4 is no longer usable as a digital I/O

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(HS) PC0 AIN5 / MCCFI 0/ PC1 OAP / PC2 OAN / PC3 AIN6 / MCCFI 1/ OAZ * MCCREF / PC4 MCPWMU/ PC5 MCPWMV/ PC6

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

ST7MC1xx/ST7MC2xx
PIN DESCRIPTION (Cont'd) Figure 3. 64-Pin LQFP 14x14 Package Pinout
MCO2 (HS) MCO1 (HS) MCO0 (HS) VPP /ICCSEL PE5 / PE4 / EXTCLK_B PE3 / ICAP1_B PE2 / ICAP2_B PE1 / OCMP1_B PE0 (HS) / OCMP2_B VDD_2 VSS_2 PD7 (HS) / TDO PD6 (HS) / RDI PD5 / AIN15 / ICCDATA PD4 /EXTCLK_A / AIN14 / ICCCLK 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 47 2 46 3 ei0 45 4 44 5 43 6 42 7 41 8 40 9 39 10 38 11 37 12 ei1 36 13 35 14 ei2 34 15 ei1 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 MCVREF / PB0 MCIA / PB1 MCIB / PB2 MCIC / PB3 MISO / PB4 AIN3 / MOSI / PB5 SCK / (HS) PB6 AIN4 / SS /(HS) PB7 (HS) PC0 AIN5 / MCCFI0 / PC1 OAP / PC2 OAN / PC3 AIN6 / MCCFI1 / OAZ * MCCREF / PC4 MCPWMU / PC5 MCPWMV/ PC6

(HS) MCO3 (HS) MCO4 (HS) MCO5 MCES OSC1 OSC2 VSS_1 VDD_1 PWM3 / PA0 PWM2 / (HS) PA1 PWM1 / PA2 AIN0 / PWM0 / PA3 ARTCLK / (HS) PA4 AIN1 / ARTIC1 / PA5 ARTIC2 / PA6 AIN2 / PA7

PD3 / ICAP1_A / AIN13 PD2 / ICAP2_A / AIN12 PD1 (HS) / OCMP1_A PD0 / OCMP2_A / AIN11 PF5 (HS) PF4 (HS) PF3 (HS) / BEEP PF2 / MCO / AIN10 PF1 / MCZEM / AIN9 PF0 / MCDEM / AIN8 RESET VDD_0 VSS_0 VSSA VAREF PC7 / MCPWMW / AIN7

(HS) 20mA high sink capability eix associated external interrupt vector * Once the MTC peripheral is ON, the pin PC4 is configured to an alternate function. PC4 is no longer usable as a digital I/O

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ST7MC1xx/ST7MC2xx
PIN DESCRIPTION (Cont'd) Figure 4. 32-Pin SDIP Package Pinouts

ICCSEL / VPP MCO0 MCO1 MCO2 MCO3 MCO4 MCO5 MCES OSC1 OSC2 AIN0 / PWM0 / PA3 AIN1 / ARTIC1 / PA5 MCVREF / PB0 MCIA / PB1 MCIB / PB2 MCIC / PB3

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

32 31 30 29

PD7 (HS) / TDO PD6 (HS) / RDI PD5 / AIN15 / ICCDATA PD4 / EXTCLK_A / AIN14 / ICCCLK PD3 / ICAP1_A / AIN13 PD2 / ICAP2_A / MCZEM / AIN12 PD1 (HS) / OCMP1_A / MCPWMV / MCDEM PD0 / OCMP2_A / MCPWMW / AIN11 RESET VDD_0 VSS_0 VAREF PC4 / MCCREF * OAZ / MCCFI1 / AIN6 PC3 / OAN PC2 / OAP

ei0

28 27 26 25 24 23 22

ei1

21 20 19 18

ei2
16 17

(HS) 20mA high sink capability eix associated external interrupt vector * Once the MTC peripheral is ON, the pin PC4 is configured to an alternate function. PC4 is no longer usable as a digital I/O

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ST7MC1xx/ST7MC2xx
PIN DESCRIPTION (Cont'd) Figure 5. 56-Pin SDIP Package Pinouts

OCMP1_B / PE1 ICAP2_B / PE2 ICAP1_B / PE3 VPP/ICCSEL (HS) MCO0 (HS) MCO1 (HS) MCO2 (HS) MCO3 (HS) MCO4 (HS) MCO5 MCES OSC1 OSC2 Vss_1 Vdd_1 PWM2 / (HS) PA1 AIN0 / PWM0 / PA3 ARTCLK / (HS) PA4 AIN1 / ARTIC1 / PA5 ARTIC2 / PA6 MCVREF / PB0 MCIA / PB1 MCIB / PB2 MCIC / PB3 MISO / PB4 AIN3 / MOSI / PB5 SCK / (HS) PB6 AIN4 / SS /(HS) PB7

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

ei0

56 55 54 53 52 51 50 49 48 47
46

PE0 (HS) / OCMP2_B VDD_2 VSS_2 PD7 (HS) / TDO PD6 (HS) / RDI PD5 / AIN15 / ICCDATA PD4 /EXTCLK_A / AIN14 / ICCCLK PD3 / ICAP1_A / AIN13 PD2 / ICAP2_A / AIN12 PD1 (HS) / OCMP1_A PD0 / OCMP2_A / AIN11 PF3 (HS) / BEEP PF1 / MCZEM / AIN9 PF0 / MCDEM / AIN8 RESET VDD_0 VSS_0 VSSA VAREF PC7 / MCPWMW / AIN7 PC6 / MCPWMV PC5 / MCPWMU PC4 / MCCREF * OAZ / MCCFI1 / AIN6 PC3 / OAN PC2 / OAP PC1 / MCCFI0/AIN5 PC0(HS)

ei1

ei1

ei2 ei2

45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29

(HS) 20mA high sink capability eix associated external interrupt vector * Once the MTC peripheral is ON, the pin PC4 is configured to an alternate function. PC4 is no longer usable as a digital I/O

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PIN DESCRIPTION (Cont'd) Figure 6. 44-Pin LQFP Package Pinouts
PE3 / ICAP1_B PE2 / ICAP2_B PE1 / OCMP1_B PE0 (HS) / OCMP2_B PD7 (HS) / TDO PD6 (HS) / RDI PD5 / AIN15 / ICCDATA

(HS) MCO3 (HS) MCO4 (HS) MCO5 MCES OSC1 OSC2 VSS_1 VDD_1 AIN0 / PWM0 / PA3 AIN1 / ARTIC1 / PA5 MCVREF / PB0

44 43 42 41 40 39 38 37 36 35 34 1 33 2 ei0 32 3 31 4 30 5 29 6 28 7 27 8 26 9 25 ei1 10 24 ei2 11 23 12 13 14 15 16 17 18 19 20 21 22 MCIA / PB1 MCIB / PB2 MCIC / PB3 MISO / PB4 AIN3 / MOSI / PB5 SCK / (HS) PB6 AIN4 / SS /(HS) PB7 OAP / PC2 OAN / PC3 AIN6 / MCCFI1 / OAZ * MCCREF / PC4

VPP /ICCSEL

MCO2 (HS)

MCO1 (HS) MCO0 (HS)

PD4 /EXTCLK_A / AIN14 / ICCCLK PD3 / ICAP1_A / AIN13 PD2 / ICAP2_A / MCZEM / AIN12 PD1 (HS) / OCMP1_A / MCPWMV/MCDEM PD0 / OCMP2_A / AIN11 RESET VDD_0 VSS_0 VSSA VAREF PC7 / MCPWMW / AIN7

(HS) 20mA high sink capability eix associated external interrupt vector * Once the MTC peripheral is ON, the pin PC4 is configured to an alternate function. PC4 is no longer usable as a digital I/O

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PIN DESCRIPTION (Cont'd) Figure 7. 32-Pin LQFP 7x7 Package Pinout
PD4 /EXTCLK_A / AIN14 / ICCCLK

(HS) MCO3 (HS) MCO4 (HS) MCO5 MCES OSC1 OSC2 AIN0 / PWM0 / PA3 AIN1 / ARTIC1 / PA5

32 31 30 29 28 27 26 25 24 1 23 2 ei0 22 3 21 4 20 5 19 6 18 7 ei2 ei1 17 8 9 10 11 12 13 14 15 16 MCVREF / PB0 MCIA / PB1 MCIB / PB2 MCIC / PB3 OAP / PC2 OAN / PC3 AIN6 / MCCFI1 / OAZ * MCCREF / PC4

PD5 / AIN15 / ICCDATA

PD7 (HS) / TDO PD6 (HS) / RDI

VPP /ICCSEL

MCO2 (HS) MCO1 (HS) MCO0 (HS)

PD3 / ICAP1_A / AIN13 PD2 / ICAP2_A / MCZEM / AIN12 PD1 (HS) / OCMP1_A / MCPWMV / MCDEM PD0 / OCMP2_A / MCPWMW /AIN11 RESET VDD_0 VSS_0 VAREF

(HS) 20mA high sink capability eix associated external interrupt vector * Once the MTC peripheral is ON, the pin PC4 is configured to an alternate function. PC4 is no longer usable as a digital I/O

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PIN DESCRIPTION (Cont'd) For external pin connection guidelines, See "ELECTRICAL CHARACTERISTICS" on page 247. Legend / Abbreviations for Table 1: Type: I = input, O = output, S = supply Input level: A = Dedicated analog input In/Output level: CT= CMOS 0.3VDD/0.7VDD with Schmitt trigger TT= Refer to the G&H ports Characteristics in section 12.8.1 on page 264 Output level: HS = 20mA high sink (on N-buffer only) Port and control configuration: Input: float = floating, wpu = weak pull-up, wpd = weak pull-down, int = interrupt 1), ana = analog Output: OD = open drain, PP = push-pull Refer to "I/O PORTS" on page 54 for more details on the software configuration of the I/O ports. The RESET configuration of each pin is shown in bold which is valid as long as the device is in reset state. Table 1. ST7MC Device Pin Description
Pin n Type LQFP80 LQFP64 LQFP44 LQFP32 SDIP56 SDIP32 Pin Name Level Output Input Input float w pu Port
1)

ana

OD

1 2 3 4 5 6 7 8 9 10 11 12 13

1 2 3 4 5 6 7 8 9

8 9 10 11 12 13 14 15 -

1 2 3 4 5 6 7 8 9 -

5 6 7 8 9 10 11 -

1 2 3 4 5 6 7 8 -

MCO3 (HS) MCO4 (HS) MCO5 (HS) M CES3 ) P G0 P G1 P G2 P G3 OSC14) OSC24) V ss_1
5)

O O O I CT I/O TT I/O TT I/O TT I/O TT I I/O S S

HS HS HS X XX XX XX XX X X X X

PP

int

Main function Output (after reset) X X X X X X X

Alternate function 2)

Motor Control Output 3 Motor Control Output 4 Motor Control Output 5 MTC Emergency Stop Port G0 Port G1 Port G2 Port G3 External clock input or Resonator oscillator inverter input Resonator oscillator inverter output Digital Ground Voltage Digital Main Supply Voltage

Vdd_15) P A0/PW M 3 P A1/PW M2 P A2PWM 1 PA3/PWM0/ AIN0

14 10 16 15 11

I /O C T I /O CT H S I / O CT I/O CT

XX XX XX X XX X X X ei1 X ei1 ei1 X ei1 X

X X X X X X X X

X X X X X X X X

Port A0 Port A1 Port A2 Port A3 Port A4 Port A5 Port A6 Port A7

PWM Output 3 PWM Output 2 PWM Output 1 PWM Output 0 ADC Analog Input 0

16 12 17 17 13 18

PA4 (HS)/ARTI/O CT HS CLK PA5 / ARTIC1/ I/O CT AIN1 PA6 / ARTIC2 P A7/AIN2 I/O C T I /O C T

PWM-ART External Clock PWM-ART Input Capture 1 ADC Analog Input 1

18 14 19 10 12 19 15 20 20 16 -

PWM-ART Input Capture 2 ADC Analog Input 2

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Table 1. ST7MC Device Pin Description
Pin n Type LQFP80 LQFP64 LQFP44 LQFP32 SDIP56 SDIP32 Pin Name Level Output Input Port Input 1) float wpu ana int Main Output function (after reset) OD X X X X X X ei2 ei2 X X X X X X ei2 ei2 X X X X X PP X X X X X X X X X X X X X X X X Port B0 Port B1 Port B2 Port B3 Port B4 Port B5 Port B6 Port B7 Port G4 Port G5 Port G6 Port G7 Port C0 Port C1 Port C2 Port C3 Opamp Output X X X X X X X X X Port C4 Port C5 Port C6 Port C7 MTC Current Feedback Input 06) ADC Analog Input 5

Alternate function 2)

21 17 21 11 13

9

PB0/MCVREF I/O CT I/O CT I/O CT I/O CT I / O CT I/O CT I /O CT H S I/O CT HS I/O TT I/O TT I/O TT I/O TT I / O CT H S

XX XX XX XX XX XX X X XX XX XX XX X X X

X X X X

MTC Voltage Reference MTC Input A MTC Input B MTC Input C SPI Master In / Slave Out Data SPI Master Out / Slave In Data SPI Slave Select (active low) ADC Analog Input 3

22 18 22 12 14 10 P B1/MC IA 23 19 23 13 15 11 P B2/MC IB 24 20 24 14 16 12 P B3/MC IC 25 21 25 15 26 22 26 16 27 23 27 17 28 24 28 18 29 30 31 32 P B4/MISO PB5/MOSI/ AIN3 P B 6/SCK PB7/SS/AIN4 P G4 P G5 P G6 P G7 P C0

SPI Serial Clock ADC Analog Input 4

33 25 29 34 26 30

PC1/MCCFI06) I/O CT /AIN5 I / O CT I/O CT I/O

35 27 31 19 17 13 P C2/OA P 36 28 32 20 18 14 P C3/OA N O AZ / 37 29 33 21 19 15 MCCFI16)/ AIN6

ei2 X

OPAMP Positive Input OPAMP Negative Input MTC Current Feedback Input 16) ADC analog Input 6

X X ei2 X X

38 30 34 22 20 16 P C4/MC CREF I /O CT 39 31 35 40 32 36 PC5/MCPWMU P C6/ MCPWMV8) P C7/ MCPWMW8)/ AIN7 I/O CT I/O CT I/O CT I S S S I/O CT

XX XX XX XX

X

MTC Current Feedback Reference 9) MTC PWM Output U MTC PWM Output V8) MTC PWM Output W8) ADC Analog Input 7

41 33 37 23

42 34 38 24 21 17 VAREF 43 35 39 25 - VSSA5) 44 36 40 26 22 18 VSS_05) 45 37 41 27 23 19 VDD_05) 46 38 42 28 24 20 R ESET

Analog Reference Voltage for ADC Analog Ground Voltage Digital Ground Voltage Digital Main Supply Voltage Top priority non maskable interrupt

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Table 1. ST7MC Device Pin Description
Pin n Type LQFP80 LQFP64 LQFP44 LQFP32 SDIP56 SDIP32 Pin Name Level Output Input Port Input 1) float wpu ana int Main Output function (after reset) OD PP

Alternate function 2)

47 39 43

-

-

-

PF0/ MCDEM7)/ AIN8

I/O CT

XX

X

X

X

Port F0

MTC Demagnetization Output7)

ADC Analog Input 8

48 40 44 49 41 -

-

-

-

PF1/MCZEM7)/ I/O CT AIN9 PF2/MCO/ AIN10 PF3/BEEP PF4 PF5 P H0 P H1 P H2 P H3 I/O CT I / O CT H S I / O CT H S I / O CT H S I/O TT I/O TT I/O TT I/O TT

XX XX XX XX XX XX XX XX XX

X X

X X X X X X X X X

X X X X X X X X X

Port F1 Port F2 Port F3 Port F4 Port F5 Port H0 Port H1 Port H2 Port H3

MTC BEMF ADC AnaOutput7) log Input 9 Main Clock Out (fosc/2) ADC Analog Input 10

50 42 45 51 43 52 44 53 54 55 56 -

Beep Signal Output

P D0/ O CMP2_A/ 57 45 46 29 25 21 MCPWMW8)/ AIN11 PD1 (HS)/ O CMP1_A/ 58 46 47 30 26 22 MCPWMV8)/ M C D E M7 )

Timer A Output Compare 2 I/O CT X X X X Port D0 MTC PWM Output W8) ADC Analog Input 11 Timer A Output Compare 1 I/O CT HS X ei0 X X Port D1 MTC PWM Output V8) MTC Demagnetization7) Timer A Input Capture 2 X ei0 X X X Port D2 MTC BEMF7) ADC Analog Input 12 X ei0 X X X Port D3 Timer A Input Capture 1 ADC Analog Input 13

P D2/ICAP2_A/ 59 47 48 31 27 23 MCZEM7) / I/O CT AIN12 60 48 49 32 28 24 P D3/ICAP1_A/ I/O CT AIN13

P D4/ 61 49 50 33 29 25 EXTCLK_A/IC- I/O CT C CLK/AIN14 62 50 51 34 30 26 P D5/ICCDATA/AIN15 I/O CT I/O CT HS I / O CT H S S S I/O TT I/O TT

Timer A External Clock source X ei0 X X X Port D4 ICC Clock Output ADC Analog Input 14 X X XX ei0 ei0 X X X X X X X Port D5 Port D6 Port D7 ICC Data Input ADC Analog Input 15 SCI Receive Data In SCI Transmit Data Output

63 51 52 35 31 27 PD6/RDI 64 52 53 36 32 28 P D7/TDO 65 53 54 66 54 55 67 68 VSS_2 VDD_2 P H4 P H5

Digital Ground Voltage Digital Main Supply Voltage XX XX X X X X Port H4 Port H5

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Table 1. ST7MC Device Pin Description
Pin n Type LQFP80 LQFP64 LQFP44 LQFP32 SDIP56 SDIP32 Pin Name Level Output Input Port Input 1) float wpu ana int Main Output function (after reset) OD X X X X X X X X X X X PP X X X X X X X X Port H6 Port H7 Port E0 Port E1 Port E2 Port E3 Port E4 Port E5 Must be tied low. In the programming mode when available, this pin acts as the programming voltage input VPP./ ICC mode pin. See section 12.9.2 on page 269 HS HS HS X X X MTC Output Channel 0 MTC Output Channel 1 MTC Output Channel 2 Timer B Output Compare 2 Timer B Output Compare 1 Timer B Input Capture 2 Timer B Input Capture 1 Timer B External Clock source

Alternate function 2)

69 70

-

-

-

-

-

P H6 P H7 P E0 / O CMP2_B P E1 / O CMP1_B P E2/ICAP2_B

I/O TT I/O TT I/O CT HS I/O CT I / O CT

XX XX XX XX XX XX XX XX

71 55 56 37 72 56 73 57 74 58 75 59 76 60 1 2 3 38 39 40 -

P E3/ICAP1_B/ I /O C T P E4 / I/O CT E XTCLK_B P E5 I / O CT

77 61

4

41

1

29 VPP/ICCSEL

I

78 62 79 63 80 64

5 6 7

42 43 44

2 3 4

30 MCO0 (HS) 31 MCO1 (HS) 32 MCO2 (HS)

O O O

Notes: 1. In the interrupt input column, "eiX" defines the associated external interrupt vector. If the weak pull-up column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input, else the configuration is floating interrupt input 2. If two alternate function outputs are enabled at the same time on a given pin (for instance, MCPWMV and MCDEM on PD1 on LQFP32), the two signals will be ORed on the output pin. 3. MCES is a floating input. To disable this function, a pull-up resistor must be used. 4. OSC1 and OSC2 pins connect a crystal/ceramic resonator or an external source to the on-chip oscillator; see Section 1 INTRODUCTION and Section 12.5 CLOCK AND TIMING CHARACTERISTICS for more details. 5. It is mandatory to connect all available VDD and VDDA pins to the supply voltage and all VSS and VSSA pins to ground. 6. MCCFI can be mapped on 2 different pins on 80 ,64 and 56-pin packages. This allows: - either to use PC1 as a standard I/O and map MCCFI on OAZ (MCCFI1) with or without using the operational amplifier (selected case after reset), - or to map MCCFI on PC1 (MCCFI0) and use the amplifier for another function. The mapping can be selected in MREF register of motor control cell. See section MOTOR CONTROL for more details. 7. MCZEM is mapped on PF1 on 80, 64 and 56-pin packages and on PD2 on 44 and 32-pins. MCDEM is mapped on PF0 on 80, 64 and 56-pin packages and on PD1 on 44 and 32-pin packages. 8. MCPWMV is mapped on PC6 on 80 and 64-pin packages and on PD1 on 44,and 32-pins packages. MCPWMW is mapped on PC7 on 80, 64 and 44-pin packages and on PD0 on 32-pins package. 9. Once the MTC peripheral is ON (bits CKE=1 or DAC=1 in the register MCRA), the pin PC4 is configured

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to an alternate function. PC4 is no longer usable as a digital I/O.l 10. On the chip, each I/O port has 8 pads. Pads that are not bonded to external pins are in input pull-up configuration after reset. The configuration of these pads must be kept at reset state to avoid added current consumption. Refer to section 15.7 on page 303

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3 REGISTER & MEMORY MAP
As shown in Figure 8, the MCU is capable of addressing 64K bytes of memories and I/O registers. The available memory locations consist of 128 bytes of register locations, up to 2Kbytes of RAM and up to 60Kbytes of user program memory. The RAM space includes up to 256 bytes for the stack from 0100h to 01FFh. Figure 8. Memory Map
0000h 007Fh 0080h

The highest address bytes contain the user reset and interrupt vectors. IMPORTANT: Memory locations marked as "Reserved" must never be accessed. Accessing a reserved area can have unpredictable effects on the device.

HW Registers (see Table 2)

0080h

Short Addressing RAM (zero page)
00FFh 0100h

RA M (1536/1024 768/384 Bytes)
067Fh 0680h

256 By tes S tac k
01FFh 0200h

1000h

60 KBytes

Reserved
0FFFh 1000h

16-bit Addressing RA M
01FFh or 037Fh or 047Fh or 067Fh

4000h

48 KBytes
8000h

32 KBytes 16 KBytes

Program Memory (60K, 48K, 32K, 16K, 8K)
FFDFh FFE0h FFFFh

C000h E000h FFFFh

Interrupt & Reset Vectors (see Table 8)

8 KBytes

As shown in Figure 9, the MCU is capable of addressing 64K bytes of memories and I/O registers. The available memory locations consist of 128 bytes of register locations, up to 1536 bytes of RAM and up to 60 Kbytes of user program memo-

ry. The RAM space includes up to 256 bytes for the stack from 0100h to 01FFh. The highest address bytes contain the user reset and interrupt vectors.

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Table 2. Hardware Register Map
Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h SPID R SPIC R SPIC S R Block Register Label PADR PADDR PAOR PBDR PBDDR PBOR PCDR PCDDR PCOR PDDR PDDDR PDOR PEDR PEDDR PEOR PFDR PFDDR PFOR PGDR PGDDR PGOR PHDR PHDDR PHOR SCISR SCIDR SCIB RR SCIC R1 SCIC R2 SCIC R3 SCIE RPR SCIE TPR Register Name Port A Data Register Port A Data Direction Register Port A Option Register Port B Data Register Port B Data Direction Register Port B Option Register Port C Data Register Port C Data Direction Register Port C Option Register Port D Data Register Port D Data Direction Register Port D Option Register Port E Data Register Port E Data Direction Register Port E Option Register Port F Data Register Port F Data Direction Register Port F Option Register Port G Data Register Port G Data Direction Register Port G Option Register Port H Data Register Port H Data Direction Register Port H Option Register SCI Status Register SCI Data Register SCI Baud Rate Register SCI Control Register 1 SCI Control Register 2 SCI Control Register 3 SCI Extended Receive Prescaler Register SCI Extended Transmit Prescaler Register Reserved Area (1 Byte) SPI Data I/O Register SPI Control Register SPI Control/Status Register xxh 0xh 00h R/W R/W R/W Reset Status 00h1 ) 00h 00h 00h1 ) 00h 00h 00h1 ) 00h 00h 00h1 ) 00h 00h 00h1 ) 00h 00h 00h1 ) 00h 00h 00h1 ) 00h 00h 00h1 ) 00h 00h C0h xxh 00h xxh 00h 00h 00h 00h Remarks R/W R/W R/W 2) R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 2) R/W 2) R/W R/W R/W R/W R/W R/W R/W R/W R/W Read Only R/W R/W R/W R/W R/W R/W R/W

Port A

Port B

Port C

Port D

Port E

Port F

Port G

Port H

LINSCITM

SPI

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Table 2. Hardware Register Map
Address 0024h 0025h 0026h 0027h 0028h 0029h 002Ah 002Bh 002Ch 002Dh 002Eh 002Fh 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh Block Register Label ITSPR 0 ITSPR 1 ITSPR 2 ITSPR 3 EICR FSCR WDG CR W ATCHDOG W D G WR MC C MCCSR MCCBC R Window Watchdog Window Register Main Clock Control / Status Register Main Clock Controller: Beep Control Register 7Fh 00h 00h 00h 00h 00h 00h 00h xxh xxh xxh 80h 00h FFh FCh FFh FCh xxh xxh 80h 00h R/W R/W R/W R/W Read Only Read Only R/W R/W R/W Read Only Read Only R/W R/W Read Only Read Only Read Only Read Only Read Only Read Only R/W R/W Register Name Interrupt Software Priority Register 0 Interrupt Software Priority Register 1 Interrupt Software Priority Register 2 Interrupt Software Priority Register 3 External Interrupt Control Register Flash Control/Status Register Window Watchdog Control Register Reset Status FFh FFh FFh FFh 00h 00h 7Fh Remarks R/W R/W R/W R/W R/W R/W R/W

ITC

FLASH

AD C

ADCCSR Control/Status Register ADCDRMSB Data Register MSB ADCDRLSB Data Register LSB TACR2 TACR1 TACSR TAIC1H R TAIC1LR TAOC1HR TAOC1LR TACHR TACLR TAACHR TAACLR TAIC2H R TAIC2LR TAOC2HR TAOC2LR SICS R TBCR2 TBCR1 TBCSR TBIC1H R TBIC1LR TBOC1HR TBOC1LR TBCHR TBCLR TBACHR TBACLR TBIC2H R TBIC2LR TBOC2HR TBOC2LR Timer A Control Register 2 Timer A Control Register 1 Timer A Control/Status Register Timer A Input Capture 1 High Register Timer A Input Capture 1 Low Register Timer A Output Compare 1 High Register Timer A Output Compare 1 Low Register Timer A Counter High Register Timer A Counter Low Register Timer A Alternate Counter High Register Timer A Alternate Counter Low Register Timer A Input Capture 2 High Register Timer A Input Capture 2 Low Register Timer A Output Compare 2 High Register Timer A Output Compare 2 Low Register System Integrity Control/Status Register Timer B Control Register 2 Timer B Control Register 1 Timer B Control/Status Register Timer B Input Capture 1 High Register Timer B Input Capture 1 Low Register Timer B Output Compare 1 High Register Timer B Output Compare 1 Low Register Timer B Counter High Register Timer B Counter Low Register Timer B Alternate Counter High Register Timer B Alternate Counter Low Register Timer B Input Capture 2 High Register Timer B Input Capture 2 Low Register Timer B Output Compare 2 High Register Timer B Output Compare 2 Low Register

TIME R A

SIM

000x000x b R/W 00h 00h xxh xxh xxh 80h 00h FFh FCh FFh FCh xxh xxh 80h 00h R/W R/W R/W Read Only Read Only R/W R/W Read Only Read Only Read Only Read Only Read Only Read Only R/W R/W

TIME R B

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Table 2. Hardware Register Map
Address 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h 0058h 0059h 005Ah 005Bh 005Ch 005Dh 005Eh 005Fh 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006Ah 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h to 006Ah 006Bh 006Ch 006Dh 006Eh 006Fh 0070h DMCR DMSR DMBK1H DMBK1L DMBK2H DMBK2L Block Register Label MTIM MTIML MZPRV MZREG MCOM P MDREG MWG H T MPRSR MIMR MISR MCRA MCRB MCRC MPHST MDFR MCFR MREF MPCR MREP MCPW H MCPW L MCPVH MCPVL MCPUH MCPUL MCP0H MCP0L MDTG MPOL MPW ME MCON F MPAR MZRF MSCR Register Name Timer Counter High Register Timer Counter Low Register Capture Zn-1 Register Capture Zn Register Compare Cn+1 Register Demagnetization Register An Weight Register Prescaler & Sampling Register Interrupt Mask Register Interrupt Status Register Control Register A Control Register B Control Register C Phase State Register D event Filter Register Current feedback Filter Register Reference Register PWM Control Register Repetition Counter Register Compare Phase W Preload Register High Compare Phase W Preload Register Low Compare Phase V Preload Register High Compare Phase V Preload Register Low Compare Phase U Preload Register High Compare Phase U Preload Register Low Compare Phase 0 Preload Register High Compare Phase 0 Preload Register Low Dead Time Generator Enable Polarity Register PWM Register Configuration Register Parity Register Z event Filter Register Sampling Clock Register Reserved Area (4 Bytes) Debug Control Register Debug Status Register Debug Breakpoint 1 MSB Register Debug Breakpoint 1 LSB Register Debug Breakpoint 2 MSB Register Debug Breakpoint 2 LSB Register 00h 10h FFh FFh FFh FFh R/W Read Only R/W R/W R/W R/W Reset Status 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 0Fh 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 0Fh FFh FFh 3Fh 00h 02h 00h 0Fh 00h Remarks R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

M TC (page 0)

M TC (page 1)

see MTC description

DM

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Table 2. Hardware Register Map
Address 0074h 0075h 0076h 0077h 0078h 0079h 007Ah 007Bh 007Ch 007Dh 007Eh 007Fh OP A M P PWM ART Block Register Label PWMDCR3 PWM DCR2 PWM DCR1 PWM DCR0 PWM C R ARTCSR ARTCAR ARTARR ARTIC C SR ARTIC R 1 ARTIC R 2 OACSR Register Name PWM AR Timer Duty Cycle Register 3 PWM AR Timer Duty Cycle Register 2 PWM AR Timer Duty Cycle Register 1 PWM AR Timer Duty Cycle Register 0 PWM AR Timer Control Register Auto-Reload Timer Control/Status Register Auto-Reload Timer Counter Access Register Auto-Reload Timer Auto-Reload Register AR Timer Input Capture Control/Status Reg. AR Timer Input Capture Register 1 AR Timer Input Capture Register 2 OPAMP Control/Status Register Reset Status 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h Remarks R/W R/W R/W R/W R/W R/W R/W R/W R/W Read Only Read Only R/W

Legend: x=undefined, R/W=read/write Notes: 1. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the I/O pins are returned instead of the DR register contents. 2. The bits associated with unavailable pins must always keep their reset value.

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4 FLASH PROGRAM MEMORY
4.1 INTRODUCTION The ST7 dual voltage High Density Flash (HDFlash) is a non-volatile memory that can be electrically erased as a single block or by individual sectors and programmed on a Byte-by-Byte basis using an external VPP supply. The HDFlash devices can be programmed and erased off-board (plugged in a programming tool) or on-board using ICP (In-Circuit Programming) or IAP (In-Application Programming). The array matrix organisation allows each sector to be erased and reprogrammed without affecting other sectors. 4.2 MAIN FEATURES

Depending on the overall Flash memory size in the microcontroller device, there are up to three user sectors (see Table 3). Each of these sectors can be erased independently to avoid unnecessary erasing of the whole Flash memory when only a partial erasing is required. The first two sectors have a fixed size of 4 Kbytes (see Figure 9). They are mapped in the upper part of the ST7 addressing space so the reset and interrupt vectors are located in Sector 0 (F000hFFFFh). Table 3. Sectors available in Flash devices
Flash Size (bytes) 4K 8K > 8K Available Sectors Sector 0 Sectors 0,1 Sectors 0,1, 2

3 Flash programming modes: Insertion in a programming tool. In this mode, all sectors including option bytes can be programmed or erased. ICP (In-Circuit Programming). In this mode, all sectors including option bytes can be programmed or erased without removing the device from the application board. IAP (In-Application Programming) In this mode, all sectors except Sector 0, can be programmed or erased without removing the device from the application board and while the application is running. ICT (In-Circuit Testing) for downloading and executing user application test patterns in RAM Read-out protection Register Access Security System (RASS) to prevent accidental programming or erasing

4.3 STRUCTURE The Flash memory is organised in sectors and can be used for both code and data storage. Figure 9. Memory Map and Sector Address
4K
1000h 3FFFh 7FFFh 9FFFh BFFFh D7FFh DFFFh EFFFh FFFFh

4.3.1 Read-out Protection Read-out protection, when selected, provides a protection against Program Memory content extraction and against write access to Flash memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller. In Flash devices, this protection is removed by reprogramming the option. In this case, the entire program memory is first automatically erased and the device can be reprogrammed. Read-out protection selection depends on the device type: In Flash devices it is enabled and removed through the FMP_R bit in the option byte. In ROM devices it is enabled by mask option specified in the Option List.

8K

10K

16K

24K

32K

48K

60K

FLASH MEMORY SIZE

SECTOR 2 2 Kbytes 8 Kbytes 16 Kbytes 24 Kbytes 40 Kbytes 52 Kbytes 4 Kbytes 4 Kbytes SECTOR 1 SECTOR 0

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FLASH PROGRAM MEMORY (Cont'd) 4.4 ICC INTERFACE ICC (In-Circuit Communication) needs a minimum of four and up to six pins to be connected to the programming tool (see Figure 10). These pins are: RESET: device reset VSS: device power supply ground Figure 10. Typical ICC Interface
PROGRAMMING TOOL ICC CONNECTOR ICC Cable APPLICATION BOARD (See Note 3) OPTIONAL (See Note 4) ICC CONNECTOR HE10 CONNECTOR TYPE 9 10 7 8 5 6 3 4 1 2 APPLICATION RESET SOURCE See Note 2 10k APPLICATION POWER SUPPLY CL2 CL1 See Note 1 APPLICATION I/O

ICCCLK: ICC output serial clock pin ICCDATA: ICC input/output serial data pin ICCSEL/VPP: programming voltage OSC1(or OSCIN): main clock input for external source (optional) VDD: application board power supply (see Figure 10, Note 3)

ST7

Notes: 1. If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal isolation is necessary. As soon as the Programming Tool is plugged to the board, even if an ICC session is not in progress, the ICCCLK and ICCDATA pins are not available for the application. If they are used as inputs by the application, isolation such as a serial resistor has to implemented in case another device forces the signal. Refer to the Programming Tool documentation for recommended resistor values. 2. During the ICC session, the programming tool must control the RESET pin. This can lead to conflicts between the programming tool and the application reset circuit if it drives more than 5mA at high level (push pull output or pull-up resistor<1K). A schottky diode can be used to isolate the application RESET circuit in this case. When using a classical RC network with R > 1K or a reset man-

agement IC with open drain output and pull-up resistor > 1K, no additional components are needed. In all cases the user must ensure that no external reset is generated by the application during the ICC session. 3. The use of Pin 7 of the ICC connector depends on the Programming Tool architecture. This pin must be connected when using most ST Programming Tools (it is used to monitor the application power supply). Please refer to the Programming Tool manual. 4. Pin 9 has to be connected to the OSC1 or OSCIN pin of the ST7 when the clock is not available in the application or if the selected clock option is not programmed in the option byte. ST7 devices with multi-oscillator capability need to have OSC2 grounded in this case.

ICCSEL/VPP

ICCDATA

RESET

ICCCLK

OSC2

OSC1

VDD

VSS

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FLASH PROGRAM MEMORY (Cont'd) 4.5 ICP (IN-CIRCUIT PROGRAMMING) To perform ICP the microcontroller must be switched to ICC (In-Circuit Communication) mode by an external controller or programming tool. Depending on the ICP code downloaded in RAM, Flash memory programming can be fully customized (number of bytes to program, program locations, or selection serial communication interface for downloading). When using an STMicroelectronics or third-party programming tool that supports ICP and the specific microcontroller device, the user needs only to implement the ICP hardware interface on the application board (see Figure 10). For more details on the pin locations, refer to the device pinout description. 4.6 IAP (IN-APPLICATION PROGRAMMING) This mode uses a BootLoader program previously stored in Sector 0 by the user (in ICP mode or by plugging the device in a programming tool). This mode is fully controlled by user software. This allows it to be adapted to the user application, (user-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored, etc.). For example, it is possible to download code from the SPI, SCI or other type of serial interface and program it in the Flash. IAP mode can be used to program any of the Flash sectors except Sector 0, which is write/ erase protected to allow recovery in case errors occur during the programming operation. 4.7 RELATED DOCUMENTATION For details on Flash programming and ICC protocol, refer to the ST7 Flash Programming Reference Manual and to the ST7 ICC Protocol Reference Manual. 4.8 REGISTER DESCRIPTION FLASH CONTROL/STATUS REGISTER (FCSR) Read / Write Reset Value: 0000 0000 (00h)
7 0 0 0 0 0 0 0 0 0

This register is reserved for use by Programming Tool software. It controls the Flash programming and erasing operations.

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5 CENTRAL PROCESSING UNIT
5.1 INTRODUCTION This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 5.2 MAIN FEATURES

5.3 CPU REGISTERS The six CPU registers shown in Figure 11 are not present in the memory mapping and are accessed by specific instructions. Accumulator (A) The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. Index Registers (X and Y) These 8-bit registers are used to create effective addresses or as temporary storage areas for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.) The Y register is not affected by the interrupt automatic procedures. Program Counter (PC) The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is the LSB) and PCH (Program Counter High which is the MSB).

Enable executing 63 basic instructions Fast 8-bit by 8-bit multiply 17 main addressing modes (with indirect addressing mode) Two 8-bit index registers 16-bit stack pointer Low power HALT and WAIT modes Priority maskable hardware interrupts Non-maskable software/hardware interrupts

Figure 11. CPU Registers
7 RESET VALUE = XXh 7 RESET VALUE = XXh 7 RESET VALUE = XXh 15 PCH 87 PCL 0 PROGRAM COUNTER RESET VALUE = RESET VECTOR @ FFFEh-FFFFh 7 0 CONDITION CODE REGISTER 1 1 I1 H I0 N Z C RESET VALUE = 1 1 1 X 1 X X X 15 87 0 STACK POINTER RESET VALUE = STACK HIGHER ADDRESS X = Undefined Value 0 Y INDEX REGISTER 0 X INDEX REGISTER 0 ACCUMULATOR

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CENTRAL PROCESSING UNIT (Cont'd) Condition Code Register (CC) Read/Write Reset Value: 111x1xxx
7
1 1 I1 H I0 N Z

Bit 1 = Z Zero. This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero. 0: The result of the last operation is different from zero. 1: The result of the last operation is zero. This bit is accessed by the JREQ and JRNE test inst ructions. Bit 0 = C Carry/borrow. This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: No overflow or underflow has occurred. 1: An overflow or underflow has occurred. This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the "bit test and branch", shift and rotate instructions. Interrupt Management Bits Bit 5,3 = I1, I0 Interrupt The combination of the I1 and I0 bits gives the current interrupt software priority.
Interrupt Software Priority Level 0 (main) Level 1 Level 2 Level 3 (= interrupt disable) I1 1 0 0 1 I0 0 1 0 1

0 C

The 8-bit Condition Code register contains the interrupt masks and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions. These bits can be individually tested and/or controlled by specific instructions. Arithmetic Management Bits Bit 4 = H Half carry. This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or ADC instructions. It is reset by hardware during the same instructions. 0: No half carry has occurred. 1: A half carry has occurred. This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines. Bit 2 = N Negative. This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic, logical or data manipulation. It's a copy of the result 7th bit. 0: The result of the last operation is positive or null. 1: The result of the last operation is negative (that is, the most significant bit is a logic 1). This bit is accessed by the JRMI and JRPL instructions.

These two bits are set/cleared by hardware when entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software priority registers (IxSPR). They can be also set/ cleared by software with the RIM, SIM, IRET, HALT, WFI and PUSH/POP instructions. See the interrupt management chapter for more details.

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CENTRAL PROCESSING UNIT (Cont'd) Stack Pointer (SP) Read/Write Reset Value: 01 FFh
15 0 7
SP7 SP6 SP5 SP4 SP3 SP2 SP1

8 0 0 0 0 0 0 1 0 SP0

The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 12). Since the stack is 256 bytes deep, the 8 most significant bits are forced by hardware. Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP7 to SP0 bits are set) which is the stack higher address. Figure 12. Stack Manipulation Example
CALL Subroutine @ 0100h Interrupt Event P USH Y

The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD instruction. Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow. The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP. Then the other registers are stored in the next locations as shown in Figure 12. When an interrupt is received, the SP is decremented and the context is pushed on the stack. On return from interrupt, the SP is incremented and the context is popped from the stack. A subroutine call occupies two locations and an interrupt five locations in the stack area.

PO P Y

IRET

RET or RSP

SP SP CC A X PC H SP PCH @ 01FFh PCL P CL PCH PCL Y CC A X PCH PCL PCH PC L SP CC A X PCH PCL PCH PCL SP PCH PCL SP

Stack Higher Address = 01FFh Stack Lower Address = 0100h

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6 SUPPLY, RESET AND CLOCK MANAGEMENT
The device includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and reducing the number of external components. An overview is shown in Figure 13. For more details, refer to dedicated parametric section. Main features Reset Sequence Manager (RSM) 1 Crystal/Ceramic resonator oscillator System Integrity Management (SI) Main supply Low voltage detection (LVD) Auxiliary Voltage detector (AVD) with interrupt capability for monitoring the main supply Clock Security System (CSS) with the VCO of the PLL, providing a backup safe oscillator Clock Detector PLL which can be used to multiply the frequency by 2 if the clock frequency input is 8MHz

Figure 13. Clock, Reset and Supply Block Diagram
SYSTEM INTEGRITY MANAGEMENT

fOSC CLOCK SECURITY SYSTEM 8Mhz OSCILLATOR OSC1 fOSC DIV2 OPT CKSEL fCLK fCPU MAIN CLOCK CONTROLLER WITH REALTIME fMTC CLOCK (MCC/RTC)

OSC2

PLL
Safeosc

16Mhz
lock

1/2

SICSR, page 1 PA GE 0 VCO LO PLL EN CK EN 0 CK SEL 0

Clock Detector

RESET SEQUENCE RESET MANAGER (RSM) SICSR, page 0

AVD Interrupt Request PA AVD AVD LVD G E IE F RF CSS CSS WDG IE D RF

WATCHDOG TIMER (WDG)

0

CSS Interrupt Request LOW VOLTAGE VSS VDD* DETECTOR (LVD)

AUXILIARY VOLTAGE DETECTOR (AVD) * It is recommended to decouple the power supply by placing a 0.1F capacitor as close as possible to VDD

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6.1 OSCILLATOR The main clock of the ST7 can be generated by a crystal or ceramic resonator oscillator or an external source. The associated hardware configurations are shown in Table 4. Refer to the electrical characteristics section for more details. External Clock Source In this external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC1 pin while the OSC2 pin is not connected. Crystal/Ceramic Oscillators This family of oscillators has the advantage of producing a very accurate rate on the main clock of the ST7. In this mode, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. This oscillator is not stopped during the RESET phase to avoid losing time in its start-up phase. See Electrical Characteristics for more details. Note: When crystal oscillator is used as a clock source, a risk of failure may exist if no series resistors are implemented. Table 4. ST7 Clock Sources
Hardware Configuration

External Clock

ST7 OS C1 OSC 2 NC EX TERNAL SO URCE

Crystal/Ceram ic Resonators

ST7 OSC 1 OSC2

CL1

LOA D CAPA CITO RS

CL 2

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6.2 RESET SEQUENCE MANAGER (RSM) 6.2.1 Introduction The reset sequence manager includes three RESET sources as shown in Figure 15: External RESET source pulse Internal LVD RESET (Low Voltage Detection) Internal WATCHDOG RESET Note: A reset can also be triggered following the detection of an illegal opcode or prebyte code. Refer to section 11.2.1 on page 244 for further details . These sources act on the RESET pin and it is always kept low during the delay phase. The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory map. The basic RESET sequence consists of 3 phases as shown in Figure 14: Active Phase depending on the RESET source 256 or 4096 CPU clock cycle delay (selected by option byte) RESET vector fetch Caution: When the ST7 is unprogrammed or fully erased, the Flash is blank and the RESET vector is not programmed. For this reason, it is recommended to keep the RESET pin in low state until programming mode is entered, in order to avoid unwanted behavior. Figure 15. Reset Block Diagram
VDD

The 256 or 4096 CPU clock cycle delay allows the oscillator to stabilise and ensures that recovery has taken place from the Reset state. The shorter or longer clock cycle delay should be selected by option byte to correspond to the stabilization time of the external oscillator used in the application. The RESET vector fetch phase duration is 2 clock c ycles. Figure 14. RESET Sequence Phases

RESET
Active Phase INTERNAL RESET 256 or 4096 CLOCK CYCLES FETCH VECTOR

6.2.2 Asynchronous External RESET pin The RESET pin is both an input and an open-drain output with integrated RON weak pull-up resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It can be pulled low by external circuitry to reset the device. See Electrical Characteristic section for more details. A RESET signal originating from an external source must have a duration of at least th(RSTL)in in order to be recognized (see Figure 16). This detection is asynchronous and therefore the MCU can enter reset state even in HALT mode.

RO N
RESET
Filter INTERNAL RESET

PULSE GENERATOR

WATCHDOG RESET ILLEGAL OPCODE RESET 1) LVD RESET

Note 1: See "Illegal Opcode Reset" on page 244. for more details on illegal opcode reset conditions.

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RESET SEQUENCE MANAGER (Cont'd) The RESET pin is an asynchronous signal which plays a major role in EMS performance. In a noisy environment, it is recommended to follow the guidelines mentioned in the electrical characteristics section. 6.2.3 External Power-On RESET If the LVD is disabled by option byte, to start up the microcontroller correctly, the user must ensure by means of an external reset circuit that the reset signal is held low until VDD is over the minimum level specified for the selected fOSC frequency. A proper reset signal for a slow rising VDD supply can generally be provided by an external RC network connected to the RESET pin. 6.2.4 Internal Low Voltage Detector (LVD) R ESET Two different RESET sequences caused by the internal LVD circuitry can be distinguished: Power-On RESET Voltage Drop RESET The device RESET pin acts as an output that is pulled low when VDD
Figure 16. RESET Sequences VDD
VIT+(LVD) VIT-(LVD)

LVD RESET

EXTERNAL RESET

WATCHDOG RESET

RUN
ACTIVE PHASE

RUN

ACTIVE PHASE

RUN

ACTIVE PHASE

RUN

th(RSTL)in
EXTERNAL RESET SOURCE

tw(RSTL)out

RESET PIN

WATCHDOG RESET WATCHDOG UNDERFLOW INTERNAL RESET (256 or 4096 TCPU) VECTOR FETCH

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6.3 SYSTEM INTEGRITY MANAGEMENT (SI) The System Integrity Management block contains the Low Voltage Detector (LVD), Auxiliary Voltage Detector (AVD) and Clock Security System (CSS) functions. It is managed by the SICSR register. Note: A reset can also be triggered following the detection of an illegal opcode or prebyte code. Refer to section 11.2.1 on page 244 for further details . 6.3.1 Low Voltage Detector (LVD) The Low Voltage Detector function (LVD) generates a static reset when the VDD supply voltage is below a VIT- reference value. This means that it secures the power-up as well as the power-down keeping the ST7 in reset. The VIT- reference value for a voltage drop is lower than the VIT+ reference value for power-on in order to avoid a parasitic reset when the MCU starts running and sinks current on the supply (hysteresis). The LVD Reset circuitry generates a reset when VDD is below: VIT+ when VDD is rising VIT- when VDD is falling Figure 17. Low Voltage Detector vs Reset
VDD

The LVD function is illustrated in Figure 17. Provided the minimum VDD value (guaranteed for the oscillator frequency) is above VIT-, the MCU can only be in two modes: under full software control in static safe reset In these conditions, secure operation is always ensured for the application without the need for external reset hardware. During a Low Voltage Detector Reset, the RESET pin is held low, thus permitting the MCU to reset other devices. Notes: The LVD allows the device to be used without any external RESET circuitry. The LVD is an optional function which can be selected by option byte. It is recommended to make sure that the VDD supply voltage rises monotonously when the device is exiting from Reset, to ensure the application functions properly.

Vhys VIT+ VIT-

RESET

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SYSTEM INTEGRITY MANAGEMENT (Cont'd) 6.3.2 Auxiliary Voltage Detector (AVD) The Voltage Detector function (AVD) is based on an analog comparison between a VIT-(AVD) and VIT+(AVD) reference value and the VDD main supply. The VIT- reference value for falling voltage is lower than the VIT+ reference value for rising voltage in order to avoid parasitic detection (hysteresis). The output of the AVD comparator is directly readable by the application software through a real time status bit (AVDF) in the SICSR register. This bit is read only. Caution: The AVD function is active only if the LVD is enabled through the option byte (see section 14.1 on page 290). 6.3.2.1 Monitoring the VDD Main Supply If the AVD interrupt is enabled, an interrupt is generated when the voltage crosses the VIT+(AVD) or VIT-(AVD) threshold (AVDF bit toggles). In the case of a drop in voltage, the AVD interrupt acts as an early warning, allowing software to shut down safely before the LVD resets the microcontroller. See Figure 18. The interrupt on the rising edge is used to inform the application that the VDD warning state is over. If the voltage rise time trv is less than 256 or 4096 CPU cycles (depending on the reset delay selected by option byte), no AVD interrupt will be generated when VIT+(AVD) is reached. If trv is greater than 256 or 4096 cycles then: If the AVD interrupt is enabled before the VIT+(AVD) threshold is reached, then 2 AVD interrupts will be received: the first when the AVDIE bit is set, and the second when the threshold is reached. If the AVD interrupt is enabled after the VIT+(AVD) threshold is reached then only one AVD interrupt will occur.

Figure 18. Using the AVD to Monitor VDD VDD Early Warning Interrupt (Power has dropped, MCU not not yet in reset)
Vh y s t

VIT+(AVD) VIT-(AVD) VIT+(LVD) VIT-(LVD)

trv VOLTAGE RISE TIME

AVDF bit AVD INTERRUPT REQUES T IF AVDIE bit = 1

0

1

0

INTERRUPT PROCESS

INTERRUPT PROCESS

LVD RESET

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SYSTEM INTEGRITY MANAGEMENT (Cont'd) 6.3.3 Clock Security System (CSS) The Clock Security System (CSS) protects the ST7 against main clock problems. To allow the integration of the security features in the applications, it is based on a PLL which can provide a backup clock. The PLL can be enabled or disabled by option byte or by software. It requires an 8-MHz input clock and provides a 16-MHz output clock. 6.3.3.1 Safe Oscillator Control The safe oscillator of the CSS block is made of a PLL. If the clock signal disappears (due to a broken or disconnected resonator...) the PLL continues to provide a lower frequency, which allows the ST7 to perform some rescue operations. Note: The clock signal must be present at start-up. Otherwise, the ST7MC will not start and will be maintained in RESET conditions. 6.3.3.2 Limitation detection The automatic safe oscillator selection is notified by hardware setting the CSSD bit of the SICSR register. An interrupt can be generated if the CSSIE bit has been previously set. These two bits are described in the SICSR register d e s c r i p t io n . 6.3.4 Low Power Modes
Mode WAIT Description No effect on SI. CSS and AVD interrupts cause the device to exit from Wait mode. The CRSR register is frozen. The CSS (including the safe oscillator) is disabled until HALT mode is exited. The previous CSS configuration resumes when the MCU is woken up by an interrupt with "exit from HALT mode" capability or from the counter reset value when the MCU is woken up by a RESET. The AVD remains active, and an AVD interrupt can be used to exit from Halt mode.

H AL T

6.3.4.1 Interrupts The CSS or AVD interrupt events generate an interrupt if the corresponding Enable Control Bit (CSSIE or AVDIE) is set and the interrupt mask in the CC register is reset (RIM instruction).
Interrupt Event Enable Event Control Flag Bit C SSIE A VDIE Exit from Wait Yes Yes Exit from Halt No 1) Yes

CSS event detection (safe oscillator acti- CSSD vated as main clock) AVD event AVDF

Note 1: This interrupt allows to exit from activehalt mode.

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SYSTEM INTEGRITY MANAGEMENT (Cont'd) 6.3.5 Register Description SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR, page 0) Read / Write is detected by the Clock Security System (CSSD bit set). It is set and cleared by software. Reset Value: 000x 000x (00h) 0: Clock security system interrupt disabled 1: Clock security system interrupt enabled 7 0 When the PLL is disabled (PLLEN=0), the CSSIE bit has no effect. PA G AVD A VD LVD C S S C S S WDG
E IE F RF 0 IE D RF

Bit 7 = PAGE SICSR Register Page Selection This bit selects the SICSR register page. It is set and cleared by software 0: Access to SICSR register mapped in page 0. 1: Access to SICSR register mapped in page 1. Bit 6 = AVDIE Voltage Detector interrupt enable This bit is set and cleared by software. It enables an interrupt to be generated when the AVDF flag changes (toggles). The pending interrupt information is automatically cleared when software enters the AVD interrupt routine. 0: AVD interrupt disabled 1: AVD interrupt enabled Bit 5 = AVDF Voltage Detector flag This read-only bit is set and cleared by hardware. If the VDIE bit is set, an interrupt request is generated when the AVDF bit changes value. 0: VDD over VIT+ (AVD) threshold 1: VDD under VIT-(AVD) threshold Bit 4 = LVDRF LVD reset flag This bit indicates that the last Reset was generated by the LVD block. It is set by hardware (LVD reset) and cleared by software (writing zero). See WDGRF flag description for more details. When the LVD is disabled by OPTION BYTE, the LVDRF bit value is undefined. Bit 3 = Reserved, must be kept cleared. Bit 2 = CSSIE Clock security syst. interrupt enable This bit enables the interrupt when a disturbance

Bit 1 = CSSD Clock security system detection This bit indicates a disturbance on the main clock signal (fOSC): the clock stops (at least for a few cycles). It is set by hardware and cleared by reading the SICSR register when the original oscillator recovers. 0: Safe oscillator is not active 1: Safe oscillator has been activated When the PLL is disabled (PLLEN=0), the CSSD bit value is forced to 0. Bit 0 = WDGRF Watchdog reset flag This bit indicates that the last Reset was generated by the Watchdog peripheral. It is set by hardware (watchdog reset) and cleared by software (writing zero) or an LVD Reset (to ensure a stable cleared state of the WDGRF flag when CPU starts). Combined with the LVDRF flag information, the flag description is given by the following table.
RESET Sources External RESET pin Watchdog LVD LV DRF 0 0 1 WDG RF 0 1 X

Application notes The LVDRF flag is not cleared when another RESET type occurs (external or watchdog), the LVDRF flag remains set to keep trace of the original failure. In this case, a watchdog reset can be detected by software while an external reset can not.

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SYSTEM INTEGRITY MANAGEMENT (Cont'd) SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR, page 1) Reset Value: 0 0 0000 (00h) Bit 3 = PLLEN PLL Enable This bit enables the PLL and the clock detector. It is set and cleared by software. 7 0 0: PLL and Clock Detector (CKD) disabled VC O L O PLL PA CK1: PLL and Clock Detector (CKD) enabled 0 0 0
GE EN CK EN S EL

Bit 7 = PAGE SICSR Register Page Selection This bit selects the SICSR register page. It is set and cleared by software 0: Access to SICSR register mapped in page 0. 1: Access to SICSR register mapped in page 1. Bit 6 = Reserved, must be kept cleared. Bit 5 = VCOEN VCO Enable This bit is set and cleared by software. 0: VCO (Voltage Controlled Oscillator) connected to the output of the PLL charge pump (default mode), to obtain a 16-MHz output frequency (with an 8-MHz input frequency). 1: VCO tied to ground in order to obtain a 10-MHz frequency (fvco) Notes: 1. During ICC session, this bit is set to 1 in order to have an internal frequency which does not depend on the input clock. Then, it can be reset in order to run faster with an external oscillator. Bit 4 = LOCK PLL Locked This bit is read only. It is set by hardware. It is set automatically when the PLL reaches its operating frequency. 0: PLL not locked 1: PLL locked

Notes: 1. During ICC session, this bit is set to 1. 2. PLL cannot be disabled if PLL clock source is selected (CKSEL= 1). Bit 2 = Reserved, must be kept cleared. Bit 1 = CKSEL Clock Source Selection This bit selects the clock source: oscillator clock or clock from the PLL. It is set and cleared by software. It can also be set by option byte (PLL opt) 0: Oscillator clock selected 1: PLL clock selected Notes: 1. During ICC session, this bit is set to 1. Then, CKSEL can be reset in order to run with fOSC. 2. Clock from the PLL cannot be selected if the PLL is disabled (PLLEN =0) 3. If the clock source is selected by PLL option bit, CKSEL bit selection has no effect. Bit 0 = Reserved, must be kept cleared.

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6.4 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK AND BEEPER (MCC/RTC) The Main Clock Controller consists of three different functions: a programmable CPU clock prescaler a clock-out signal to supply external devices a real time clock timer with interrupt capability Each function can be used independently and simultaneously. 6.4.1 Programmable CPU Clock Prescaler The programmable CPU clock prescaler supplies the clock for the ST7 CPU and its internal peripherals. It manages SLOW power saving mode (See Section 8.2 SLOW MODE for more details). The prescaler selects the fCPU main clock frequency and is controlled by three bits in the MCCSR register: CP[1:0] and SMS. 6.4.2 Clock-out Capability The clock-out capability is an alternate function of an I/O port pin that outputs a fOSC2 clock to drive external devices. It is controlled by the MCO bit in the MCCSR register. CAUTION: When selected, the clock out pin suspends the clock during ACTIVE-HALT mode. 6.4.3 Real Time Clock Timer (RTC) The counter of the real time clock timer allows an interrupt to be generated based on an accurate real time clock. Four different time bases depending directly on fOSC2 are available. The whole functionality is controlled by four bits of the MCCSR register: TB[1:0], OIE and OIF. When the RTC interrupt is enabled (OIE bit set), the ST7 enters ACTIVE-HALT mode when the HALT instruction is executed. See Section 8.4 ACTIVE-HALT AND HALT MODES for more details. 6.4.4 Beeper The beep function is controlled by the MCCBCR register. It can output three selectable frequencies on the BEEP pin (I/O port alternate function).

Figure 19. Main Clock Controller (MCC/RTC) Block Diagram
BC1 BC0 MCCBCR BEEP BEEP SIGNAL GE NERATOR MCO

DIV128 MCCSR MCO fCLK DIV 2 fOSC2 DIV 2, 4, 8, 16

RTC COUNTER

CP0 SMS TB1 TB0

OIE

OIF MCC/RTC INTERRUPT (AND TO MTC PERIPHERAL) fCPU CPU CLOCK TO CPU AND PERIPHERALS TO MOTOR CONTROL PERIPHERAL

DIV 2 DIV 2, 4, 8, 16

fADC fMTC

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MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont'd) 6.4.5 Low Power Modes Bit 6:5 = CP[1:0] CPU clock prescaler Mode Description These bits select the CPU clock prescaler which is No effect on MCC/RTC peripheral. applied in the different slow modes. Their action is WAIT MCC/RTC interrupt cause the device to exit conditioned by the setting of the SMS bit. These from WAIT mode. two bits are set and cleared by software
A C TIVEH ALT No effect on MCC/RTC counter (OIE bit is set), the registers are frozen. MCC/RTC interrupt cause the device to exit from ACTIVE-HALT mode. MCC/RTC counter and registers are frozen. MCC/RTC operation resumes when the MCU is woken up by an interrupt with "exit from HALT" capability. fCPU in SLOW mode fOSC2 / 2 fOSC2 / 4 fOSC2 / 8 fOSC2 / 16 CP1 0 0 1 1 CP0 0 1 0 1

H ALT

6.4.6 Interrupts The MCC/RTC interrupt event generates an interrupt if the OIE bit of the MCCSR register is set and the interrupt mask in the CC register is not active (RIM instruction).
Interrupt Event Time base overflow event Enable Event Control Flag Bit OIF OIE Exit from Wait Ye s Exit from Halt No 1 )

Bit 4 = SMS Slow mode select This bit is set and cleared by software. 0: Normal mode. fCPU = fOSC2 1: Slow mode. fCPU is given by CP1, CP0 See Section 8.2 SLOW MODE and Section 6.4 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK AND BEEPER (MCC/RTC) for more details . Bit 3:2 = TB[1:0] Time base control These bits select the programmable divider time base. They are set and cleared by software.
Time Base Counter Prescaler f OSC2 =4MHz fOSC2=8MHz 16000 4ms 8ms 20ms 50ms 2ms 4ms 10m s 25m s 32000 80000 20 0 0 TB1 0 0 1 1 TB0 0 1 0 1

Note: The MCC/RTC interrupt wakes up the MCU from ACTIVE-HALT mode, not from HALT mode.

6.4.7 Register Description MCC CONTROL/STATUS REGISTER (MCCSR) Read / Write Reset Value: 0000 0000 (00h)
7 MCO C P1 CP0 SM S TB1 T B0 OIE 0 OIF

A modification of the time base is taken into account at the end of the current period (previously set) to avoid an unwanted time shift. This allows to use this time base as a real time clock. Bit 1 = OIE Oscillator interrupt enable This bit set and cleared by software. 0: Oscillator interrupt disabled 1: Oscillator interrupt enabled This interrupt can be used to exit from ACTIVEHALT mode. When this bit is set, calling the ST7 software HALT instruction enters the ACTIVE-HALT power saving mode.

Bit 7 = MCO Main clock out selection This bit enables the MCO alternate function on the PF0 I/O port. It is set and cleared by software. 0: MCO alternate function disabled (I/O pin free for general-purpose I/O) 1: MCO alternate function enabled (fOSC2on I/O port) Note: To reduce power consumption, the MCO function is not active in ACTIVE-HALT mode.

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MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont'd) MCC BEEP CONTROL REGISTER (MCCBCR) Bit 0 = OIF Oscillator interrupt flag This bit is set by hardware and cleared by software Read / Write reading the CSR register. It indicates when set Reset Value: 0000 0000 (00h) that the main oscillator has reached the selected elapsed time (TB1:0). 7 0 0: Timeout not reached 1: Timeout reached AD- ADC 0 0 0 0 BC1 BC0 CAUTION: The BRES and BSET instructions STS IE must not be used on the MCCSR register to avoid Bit 7:4 = Reserved, must be kept cleared. unintentionally clearing the OIF bit. Bit 3 = ADSTS A/D Converter Sample Time Stretch This bit is set and cleared by software to enable or disable the A/D Converter sample time stretch feature. 0: AD sample time stretch disabled (for standard impedance analog inputs) 1 AD sample time stretch enabled (for high impedance analog inputs) Bit 2 = ADCIE A/D Converter Interrupt Enable This bit is set and cleared by software to enable or disable the A/D Converter interrupt. 0: AD Interrupt disabled 1 AD Interrupt enabled Bit 1:0 = BC[1:0] Beep control These 2 bits select the PF1 pin beep capability.
BC1 0 0 1 1 B C0 0 1 0 1 ~2-KHz ~1- KHz ~500-Hz Beep mode with fOSC2=8MHz Off Output Beep signal ~50% duty cycle

The beep output signal is available in ACTIVEHALT mode but has to be disabled to reduce the consumption. Table 5. Main Clock Controller Register Map and Reset Values
Address (Hex.) 0040h 0040h 002Ch 002Dh Register Label SICSR, page0 Reset Value SICSR, page1 Reset Value M CCSR Reset Value M CCBCR Reset Value 7 PAGE 0 PAGE 0 MCO 0 0 6 VDIE 0 0 CP1 0 0 5 VDF 0 VC OEN 0 CP0 0 0 4 LV DRF x LOCK x S MS 0 0 3 2 CFIE 0 0 TB0 0 ADCIE 0 1 C SSD 0 CKSEL 0 OIE 0 BC1 0 0 W D GR F x 0 OIF 0 BC0 0

0 PLLEN 0 TB1 0 ADSTS 0

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7 INTERRUPTS
7.1 INTRODUCTION The ST7 enhanced interrupt management provides the following features: Hardware interrupts Software interrupt (TRAP) Nested or concurrent interrupt management with flexible interrupt priority and level management: Up to 4 software programmable nesting levels Up to 16 interrupt vectors fixed by hardware 2 non maskable events: RESET, TRAP 1 maskable top level event: MCES This interrupt management is based on: Bit 5 and bit 3 of the CPU CC register (I1:0), Interrupt software priority registers (ISPRx), Fixed interrupt vector addresses located at the high addresses of the memory map (FFE0h to FFFFh) sorted by hardware priority order. This enhanced interrupt controller guarantees full upward compatibility with the standard (not nested) ST7 interrupt controller. 7.2 MASKING AND PROCESSING FLOW The interrupt masking is managed by the I1 and I0 bits of the CC register and the ISPRx registers which give the interrupt software priority level of Figure 20. Interrupt Processing Flowchart
RESET PENDING INTERRUPT N Y MCES Interrupt has the same or a lower software priority than current one N I1:0 Interrupt has a higher software priority than current one Y

each interrupt vector (see Table 6). The processing flow is shown in Figure 20 When an interrupt request has to be serviced: Normal processing is suspended at the end of the current instruction execution. The PC, X, A and CC registers are saved onto the stack. I1 and I0 bits of CC register are set according to the corresponding values in the ISPRx registers of the serviced interrupt vector. The PC is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to "Interrupt Mapping" table for vector addresses). The interrupt service routine should end with the IRET instruction which causes the contents of the saved registers to be recovered from the stack. Note: As a consequence of the IRET instruction, the I1 and I0 bits will be restored from the stack and the program in the previous level will resume. Table 6. Interrupt Software Priority Levels
Interrupt software priority Level 0 (main) Level 1 Level 2 Level 3 (= interrupt disable) Level Low I1 1 0 0 1 I0 0 1 0 1

High

FETCH NEXT INSTRUCTION

THE INTERRUPT STAYS PENDING

Y

"IRET" N

RESTORE PC, X, A, CC FROM STACK

EXECUTE INSTRUCTION

STACK PC, X, A, CC LOAD I1:0 FROM INTERRUPT SW REG. LOAD PC FROM INTERRUPT VECTOR

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INTERRUPTS (Cont'd) Servicing Pending Interrupts As several interrupts can be pending at the same time, the interrupt to be taken into account is determined by the following two-step process: the highest software priority interrupt is serviced, if several interrupts have the same software priority then the interrupt with the highest hardware priority is serviced first. Figure 21 describes this decision process. Figure 21. Priority Decision Process
PENDING INTERRUPTS

ing to the flowchart in Figure 20 as a MCES top level interrupt.

RESET The RESET source has the highest priority in the ST7. This means that the first current routine has the highest software priority (level 3) and the highest hardware priority. See the RESET chapter for more details.

Same

SOFTWARE PRIORITY

Different

HIGHEST SOFTWARE PRIORITY SERVICED HIGHEST HARDWARE PRIORITY SERVICED

When an interrupt request is not serviced immediately, it is latched and then processed when its software priority combined with the hardware priority becomes the highest one. Note 1: The hardware priority is exclusive while the software one is not. This allows the previous process to succeed with only one interrupt. Note 2: RESET, TRAP and MCES can be considered as having the highest software priority in the decision process. Different Interrupt Vector Sources Two interrupt source types are managed by the ST7 interrupt controller: the non-maskable type (RESET, TRAP) and the maskable type (external or from internal peripherals). Non-Maskable Sources These sources are processed regardless of the state of the I1 and I0 bits of the CC register (see Figure 20). After stacking the PC, X, A and CC registers (except for RESET), the corresponding vector is loaded in the PC register and the I1 and I0 bits of the CC are set to disable interrupts (level 3). These sources allow the processor to exit HALT mode. TRAP (Non Maskable Software Interrupt) This software interrupt is serviced when the TRAP instruction is executed. It will be serviced accord-

Maskable Sources Maskable interrupt vector sources can be serviced if the corresponding interrupt is enabled and if its own interrupt software priority (in ISPRx registers) is higher than the one currently being serviced (I1 and I0 in CC register). If any of these two conditions is false, the interrupt is latched and thus remains pending. MCES (MTC Emergency Stop) This hardware interrupt occurs when a specific edge is detected on the dedicated MCES pin or when an error is detected by the micro in the motor speed measurement. The interrupt request is maintained as long as the MCES pin is low if the interrupt is enabled by the EIM bit in the MIMR regis ter. External Interrupts External interrupts allow the processor to exit from HALT low power mode. External interrupt sensitivity is software selectable through the External Interrupt Control register (EICR). External interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. If several input pins of a group connected to the same interrupt line are selected simultaneously, these will be logically ORed. Peripheral Interrupts Usually the peripheral interrupts cause the MCU to exit from HALT mode except those mentioned in the "Interrupt Mapping" table. A peripheral interrupt occurs when a specific flag is set in the peripheral status registers and if the corresponding enable bit is set in the peripheral control register. The general sequence for clearing an interrupt is based on an access to the status register followed by a read or write to an associated register. Note: The clearing sequence resets the internal latch. A pending interrupt (i.e. waiting for being serviced) will therefore be lost if the clear sequence is executed.

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INTERRUPTS (Cont'd) 7.3 INTERRUPTS AND LOW POWER MODES All interrupts allow the processor to exit the WAIT low power mode. On the contrary, only external and other specified interrupts allow the processor to exit from the HALT modes (see column "Exit from HALT" in "Interrupt Mapping" table). When several pending interrupts are present while exiting HALT mode, the first one serviced can only be an interrupt with exit from HALT mode capability and it is selected through the same decision process shown in Figure 21. Note: If an interrupt, that is not able to Exit from HALT mode, is pending with the highest priority when exiting HALT mode, this interrupt is serviced after the first one serviced. Figure 22. Concurrent Interrupt Management
M CES SOFTW ARE PRIORITY LEVEL IT2 IT1 IT4 IT3 IT0

7.4 CONCURRENT & NESTED MANAGEMENT The following Figure 22 and Figure 23 show two different interrupt management modes. The first is called concurrent mode and does not allow an interrupt to be interrupted, unlike the nested mode in Figure 23. The interrupt hardware priority is given in this order from the lowest to the highest: MAIN, IT4, IT3, IT2, IT1, IT0, MCES. The software priority is given for each interrupt. Warning: A stack overflow may occur without notifying the software of the failure.

I1

I0

HARDWARE PRIORITY

MCES IT0 IT1 IT2 IT3 RIM IT4 MAIN MAIN IT1

3 3 3 3 3 3 3/0 10

11 11 11 11 11 11

11 / 10 Figure 23. Nested Interrupt Management
MC ES

SOFTW ARE PRIORITY LEVEL

IT2

IT1

IT4

IT3

IT0

I1

I0

HARDWARE PRIORITY

MCES IT0 IT1 IT2 IT3 RIM IT4 MAIN IT4 MAIN IT1 IT2

3 3 2 1 3 3 3/0 10

11 11 00 01 11 11

11 / 10

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USED STACK = 20 BYTES

U SED S TACK = 10 BYTE S

ST7MC1xx/ST7MC2xx
INTERRUPTS (Cont'd) 7.5 INTERRUPT REGISTER DESCRIPTION CPU CC REGISTER INTERRUPT BITS Read / Write Reset Value: 111x 1010 (xAh)
7 1 1 I1 H I0 N Z 0 C ISPR1 I1_7 I0_7 I1_6 I0_6 I1_5 I0_5 I0_9 I1_4 I1_8 I0_4 I0_8

INTERRUPT SOFTWARE PRIORITY REGISTERS (ISPRX) Read/Write (bit 7:4 of ISPR3 are read only) Reset Value: 1111 1111 (FFh)
7 ISPR0 I1_3 I0_3 I1_2 I0_2 I1_1 I0_1 I1_0 0 I0_0

Bit 5, 3 = I1, I0 Software Interrupt Priority These two bits indicate the current interrupt software priority.
Interrupt Software Priority Level 0 (main) Level 1 Level 2 Level 3 (= interrupt disable*) Level Low I1 1 0 0 1 I0 0 1 0 1

ISPR2 ISPR3

I1_11 I0_11 I1_10 I0_10 I1_9 1 1 1 1

I1_13 I0_13 I1_12 I0_12

High

These two bits are set/cleared by hardware when entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software priority registers (ISPRx). They can be also set/cleared by software with the RIM, SIM, HALT, WFI, IRET and PUSH/POP instructions (see "Interrupt Dedicated Instruction Set" table). *Note: MCES, TRAP and RESET events can interrupt a level 3 program.

These four registers contain the interrupt software priority of each interrupt vector. Each interrupt vector (except RESET and TRAP) has corresponding bits in these registers where its own software priority is stored. This correspondence is shown in the following table.
Vector address FFFBh-FFFAh FFF9h-FFF8h ... FFE1h-FFE0h ISPRx bits I1_0 and I0_0 bits* I1_1 and I0_1 bits ... I1_13 and I0_13 bits

Each I1_x and I0_x bit value in the ISPRx registers has the same meaning as the I1 and I0 bits in the CC register. Level 0 can not be written (I1_x=1, I0_x=0). In this case, the previously stored value is kept. (example: previous=CFh, write=64h, result=44h) The RESET, TRAP and MCES vectors have no software priorities. When one is serviced, the I1 and I0 bits of the CC register are both set. *Note: Bits in the ISPRx registers which correspond to the MCES can be read and written but they are not significant in the interrupt process management. Caution: If the I1_x and I0_x bits are modified while the interrupt x is executed the following behaviour has to be considered: If the interrupt x is still pending (new interrupt or flag not cleared) and the new software priority is higher than the previous one, the interrupt x is re-entered. Otherwise, the software priority stays unchanged up to the next interrupt request (after the IRET of the interrupt x).

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INTERRUPTS (Cont'd) Table 7. Dedicated Interrupt Instruction Set
Instruction HALT IR ET JRM JRNM POP CC RIM SIM TRAP New Description Entering Halt mode Interrupt routine return Jump if I1:0=11 (level 3) Jump if I1:0<>11 Pop CC from the Stack Enable interrupt (level 0 set) Disable interrupt (level 3 set) Software trap Pop CC, A, X, PC I1:0=11 ? I1:0<>11 ? Mem => CC Load 10 in I1:0 of CC Load 11 in I1:0 of CC Software NMI I1 1 1 1 H I0 0 1 1 N Z C Function/Example I1 1 I1 H H I0 0 I0 N Z C N Z C

WFI Wait for interrupt 1 0 Note: During the execution of an interrupt routine, the HALT, POPCC, RIM, SIM and WFI instructions change the current software priority up to the next IRET instruction or one of the previously mentioned instructions.

Table 8. Interrupt Mapping
N Source Block R ESET TRAP 0 1 2 3 4 5 6 7 8 9 10 11 12 13 SPI T IM ER A TIM ER B MTC MC E S MCC/RTC CSS e i0 ei1 ei2 Reset Software interrupt Motor Control Emergency Stop or Speed error interrupt Main clock controller time base interrupt Safe oscillator activation interrupt External interrupt port External interrupt port External interrupt port Event U or Current Loop or Sampling Out MISR/MCONF Event R or Event Z Event C or Event D SPI peripheral interrupts TIMER A peripheral interrupts TIMER B peripheral interrupts MISR SPICSR T ASR T BSR SCISR SICSR A DCSR ARTCSR ARTICCSR Lowest Priority N/A Description Register Label N/A MISR MCR C M CCSR SICSR Priority Order Exit from HALT 1 ) yes no Highest Priority no yes yes y es y es no no no y es no no no yes no Address Vector FFFEh-FFFFh FFFCh-FFFDh FFFAh-FFFBh FFF8h-FFF9h FFF6h-FFF7h FFF4h-FFF5h FFF2h-FFF3h FFF0h-FFF1h FFEEh-FFEFh FFECh-FFEDh FFEAh-FFEBh FFE8h-FFE9h FFE6h-FFE7h FFE4h-FFE5h FFE2h-FFE3h FFE0h-FFE1h

LINSCITM
AV D/ ADC PWM ART

LINSCITM Peripheral interrupts
Auxiliary Voltage detector interrupt ADC End of conversion interrupt PWM ART overflow interrupt PWM ART input capture interrupts

Note 1. Valid for HALT and ACTIVE-HALT modes except for the MCC/RTC or CSS interrupt source which exits from ACTIVE-HALT mode only.

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INTERRUPTS (Cont'd) 7.6 EXTERNAL INTERRUPTS The pending interrupts are cleared writing a different value in the ISx[1:0], IPA or IPB bits of the EICR. Note: External interrupts are masked when an I/O (configured as input interrupt) of the same interrupt vector is forced to VSS. 7.6.1 I/O PORT INTERRUPT SENSITIVITY The external interrupt sensitivity is controlled by the IPA, IPB and ISxx bits of the EICR register (Figure 24). This control allows to have up to 4 fully independent external interrupt source sensitivities. Each external interrupt source can be generated on four (or five) different events on the pin: Falling edge Rising edge Falling and rising edge Falling edge and low level Rising edge and high level (only for ei0 and ei2) To guarantee correct functionality, the sensitivity bits in the EICR register can be modified only when the I1 and I0 bits of the CC register are both set to 1 (level 3).

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INTERRUPTS (Cont'd) Figure 24. External Interrupt Control bits
PORT D [6:4] INTERRUPTS PDOR.6 PDDDR.6 PD6 CONTROL IPA BIT EICR IS30 IS31 PD6 PD5 PD4 ei0 INTERRUPT SOURCE

SENSITIVITY

PORT D [3:1] INTERRUPTS PDOR.3 PDDDR.3 PD3

EICR IS30 IS31 PD3 PD2 PD1

SENSITIVITY CONTROL

ei0 INTERRUPT SOURCE

PORT A3, PORT A[7:5] INTERRUPTS PAOR.7 PADDR.7 PA7

EICR IS20 IS21 PA7 PA6 PA5 PA3

SENSITIVITY CONTROL

ei1 INTERRUPT SOURCE

PORT C [3:1] INTERRUPTS PCOR.3 PCDDR.3 PC3

EICR IS10 IS11 PC3 PC2 PC1

SENSITIVITY CONTROL

ei2 INTERRUPT SOURCE

IPB BIT

PORT C0, PORT B[7:6] INTERRUPTS PCOR.0 PCDDR.0 PC0

EICR IS10 IS11 PC0 PB7 PB6

SENSITIVITY CONTROL

ei2 INTERRUPT SOURCE

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INTERRUPTS (Cont'd) 7.7 EXTERNAL INTERRUPT CONTROL REGISTER (EICR) Read / Write Reset Value: 0000 0000 (00h)
7 IS11 IS10 IPB I S21 I S20 I S31 I S30 0 IPA

These 2 bits can be written only when I1 and I0 of the CC register are both set to 1 (level 3). Bit 5 = IPB Interrupt polarity for port C This bit is used to invert the sensitivity of the port C[3:1] external interrupts. It can be set and cleared by software only when I1 and I0 of the CC register are both set to 1 (level 3). 0: No sensitivity inversion 1: Sensitivity inversion Bit 4:3= IS2[1:0] ei1sensitivity The interrupt sensitivity, defined using the IS2[1:0] bits, is applied to the following external interrupts: - ei1 (port A3, A5...A7)
I S 21 IS20 0 0 1 1 0 1 0 1 External Interrupt Sensitivity Falling edge & low level Rising edge only Falling edge only Rising and falling edge

Bit 7:6 = IS1[1:0] ei2 sensitivity The interrupt sensitivity, defined using the IS1[1:0] bits, is applied to the following external interrupts: - ei2 (port C3..1)
External Interrupt Sensitivity IS11 IS10 IPB bit =0 0 0 1 1 0 1 0 1 Falling edge & low level Rising edge only Falling edge only IPB bit =1 Rising edge & high level Falling edge only Rising edge only

Rising and falling edge

- ei2 (port C0, B7..6)
IS11 IS10 0 0 1 1 0 1 0 1 External Interrupt Sensitivity Falling edge & low level Rising edge only Falling edge only Rising and falling edge

Bit 2:1= IS3[1:0] ei0sensitivity The interrupt sensitivity, defined using the IS2[1:0] bits, is applied to the following external interrupts:

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EXTERNAL INTERRUPT CONTROL REGISTER (EICR) (Cont'd) - ei0 (port D6..4)
External Interrupt Sensitivity IS31 IS30 IPA bit =0 0 0 1 1 0 1 0 1 Falling edge & low level Rising edge only Falling edge only IPA bit =1 Rising edge & high level Falling edge only Rising edge only

Bit 0 = IPA Interrupt polarity for port D This bit is used to invert the sensitivity of the port D [6:4] external interrupts. It can be set and cleared by software only when I1 and I0 of the CC register are both set to 1 (level 3). 0: No sensitivity inversion 1: Sensitivity inversion

Rising and falling edge

- ei0 (port D3..1)
IS31 IS30 0 0 1 1 0 1 0 1 External Interrupt Sensitivity Falling edge & low level Rising edge only Falling edge only Rising and falling edge

These 2 bits can be written only when I1 and I0 of the CC register are both set to 1 (level 3).

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INTERRUPTS (Cont'd) Table 9. Nested Interrupts Register Map and Reset Values
Address (Hex.) 0024h Register Label ISPR0 Reset Value ISPR1 Reset Value ISPR2 Reset Value ISPR3 Reset Value EICR Reset Value 7 6 5 4 3 2 1 MCES 1 ei2 I1_4 1 SPI I1_8 1 AVD I1_12 1 0 I0_12 1 0 I0_8 1 I0_4 1 1 0

0025h

0026h

ei1 I1_3 I0_3 1 1 MTC C/D I1_7 I0_7 1 1 SC I I1_11 I0_11 1 1 I1_15 1 IS11 0 I0_15 1 IS10 0

ei0 I1_2 I0_2 1 1 MTC R/Z I1_6 I0_6 1 1 T IMER B I1_10 I0_10 1 1 I1_14 1 IPB 0 I0_14 1 IS21 0

0027h 0028h

MCC + SI I1_1 I0_1 1 1 MTC U/CL I1_5 I0_5 1 1 T IM ER A I1_9 I0_9 1 1 PWM ART I1_13 I0_13 1 1 IS20 IPA 0 0

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8 POWER SAVING MODES
8.1 INTRODUCTION To give a large measure of flexibility to the application in terms of power consumption, four main power saving modes are implemented in the ST7 (see Figure 25): SLOW, WAIT (SLOW WAIT), ACTIVE HALT and HALT. After a RESET the normal operating mode is selected by default (RUN mode). This mode drives the device (CPU and embedded peripherals) by means of a master clock which is based on the main oscillator frequency divided or multiplied by 2 (fOSC2). From RUN mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific ST7 software instruction whose action depends on the oscillator status. Figure 25. Power Saving Mode Transitions
High
fOSC2/2 fOSC2/4 fOSC2

8.2 SLOW MODE This mode has two targets: To reduce power consumption by decreasing the internal clock in the device, To adapt the internal clock frequency (fCPU) to the available supply voltage. SLOW mode is controlled by three bits in the MCCSR register: the SMS bit which enables or disables Slow mode and two CPx bits which select the internal slow frequency (fCPU). In this mode, the master clock frequency (fOSC2) can be divided by 2, 4, 8 or 16. The CPU and peripherals are clocked at this lower frequency (fCPU). Note: SLOW-WAIT mode is activated when entering the WAIT mode while the device is already in SLOW mode. Figure 26. SLOW Mode Clock Transitions

RUN SLOW MCCS R WAIT SLOW WAIT ACTIVE HALT HALT Low PO WER CONS UMPTION

f CPU

fOSC2 CP1:0 SMS 00 01

NEW SLOW FREQUENCY REQUEST

NORMAL RUN MODE REQUEST

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POWER SAVING MODES (Cont'd) 8.3 WAIT MODE WAIT mode places the MCU in a low power consumption mode by stopping the CPU. This power saving mode is selected by calling the `WFI' instruction. All peripherals remain active. During WAIT mode, the I[1:0] bits of the CC register are forced to `10', to enable all interrupts. All other registers and memory remain unchanged. The MCU remains in WAIT mode until an interrupt or RESET occurs, whereupon the Program Counter branches to the starting address of the interrupt or Reset service routine. The MCU will remain in WAIT mode until a Reset or an Interrupt occurs, causing it to wake up. Refer to Figure 27. Figure 27. WAIT Mode Flow-chart
OSCILLATOR PERIPHERALS CP U I[1:0] BITS ON ON OFF 10

WFI I N S T R U C T I O N

N RE SET N INTERRUP T Y OSCILLATOR PERIPHERALS CP U I[1:0] BITS ON OFF ON 10 Y

256 OR 4096 CPU CLOCK CYCLE DELAY

OSCILLATOR ON PERIPHERALS ON CP U ON I[1:0] BITS XX 1)

FETC H RES ET VEC TOR O R SE RVICE I NTERRUPT

Note: 1. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of the interrupt routine and recovered when the CC register is popped.

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POWER SAVING MODES (Cont'd) 8.4 ACTIVE-HALT AND HALT MODES ACTIVE-HALT and HALT modes are the two lowest power consumption modes of the MCU. They are both entered by executing the `HALT' instruction. The decision to enter either in ACTIVE-HALT or HALT mode is given by the MCC/RTC interrupt enable flag (OIE bit in MCCSR register).
MCCSR O I E bi t 0 1 Power Saving Mode entered when HALT instruction is executed HALT mode ACTIVE-HALT mode H A L T INSTR UCTIO N (MC C SR. O IE=1)

Figure 28. ACTIVE-HALT Timing Overview
RUN ACTIVE 256 OR 4096 CPU HA LT CYCLE DELAY 1) RESET OR INTER RUPT RUN

HA LT IN STRUCTION [MCCS R.OIE=1]

FE TCH VECTOR

Figure 29. ACTIVE-HALT Mode Flow-chart
OSCILLATOR ON PERIPHERALS 2) OFF CP U OFF 10 I[1:0] BITS N RE SET N INTERRUPT 3) Y OSCILLATOR ON PERIPHERALS OFF CP U ON I[1:0] BITS XX 4) 256 OR 4096 CPU CLOCK CYCLE DELAY OSCILLATOR ON PERIPHERALS ON CP U ON I[1:0] BITS XX 4) FETC H RES ET VEC TOR O R SE RVICE I NTERRUPT Y

8.4.1 ACTIVE-HALT MODE ACTIVE-HALT mode is the lowest power consumption mode of the MCU with a real time clock available. It is entered by executing the `HALT' instruction when the OIE bit of the Main Clock Controller Status register (MCCSR) is set (see section 6.4 on page 37 for more details on the MCCSR register). The MCU can exit ACTIVE-HALT mode on reception of either an MCC/RTC interrupt, a specific interrupt (see Table 8, "Interrupt Mapping," on page 44) or a RESET. When exiting ACTIVEHALT mode by means of an interrupt, no 256 or 4096 CPU cycle delay occurs. The CPU resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see Figure 29). When entering ACTIVE-HALT mode, the I[1:0] bits in the CC register are forced to `10b' to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately. In ACTIVE-HALT mode, only the main oscillator and its associated counter (MCC/RTC) are running to keep a wake-up time base. All other peripherals are not clocked except those which get their clock supply from another clock generator (such as external or auxiliary oscillator). The safeguard against staying locked in ACTIVEHALT mode is provided by the oscillator interrupt. Note: As soon as the interrupt capability of one of the oscillators is selected (MCCSR.OIE bit set), entering ACTIVE-HALT mode while the Watchdog is active does not generate a RESET. This means that the device cannot spend more than a defined delay in this power saving mode.

Notes: 1. This delay occurs only if the MCU exits ACTIVEHALT mode by means of a RESET. 2. Peripheral clocked with an external clock source can still be active. 3. Only the MCC/RTC interrupt and some specific interrupts can exit the MCU from ACTIVE-HALT mode (such as external interrupt). Refer to Table 8, "Interrupt Mapping," on page 44 for more details. 4. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of the interrupt routine and restored when the CC register is popped.

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POWER SAVING MODES (Cont'd) 8.4.2 HALT MODE The HALT mode is the lowest power consumption mode of the MCU. It is entered by executing the `HALT' instruction when the OIE bit of the Main Clock Controller Status register (MCCSR) is cleared (see section 6.4 on page 37 for more details on the MCCSR register). The MCU can exit HALT mode on reception of either a specific interrupt (see Table 8, "Interrupt Mapping," on page 44) or a RESET. When exiting HALT mode by means of a RESET or an interrupt, the oscillator is immediately turned on and the 256 or 4096 CPU cycle delay is used to stabilize the oscillator. After the start up delay, the CPU resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see Figure 31). When entering HALT mode, the I[1:0] bits in the CC register are forced to `10b'to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately. In HALT mode, the main oscillator is turned off causing all internal processing to be stopped, including the operation of the on-chip peripherals. All peripherals are not clocked except the ones which get their clock supply from another clock generator (such as an external or auxiliary oscillator). The compatibility of Watchdog operation with HALT mode is configured by the "WDGHALT" option bit of the option byte. The HALT instruction when executed while the Watchdog system is enabled, can generate a Watchdog RESET (see section 14.1 on page 290 for more details). Figure 30. HALT Timing Overview
RUN HA LT 256 OR 4096 CPU CYCLE DELAY RESET OR INTER RUPT FE TCH VECTOR RUN FETC H RES ET VEC TOR O R SE RVICE I NTERRUPT

Figure 31. HALT Mode Flow-chart
H AL T INSTRUCTION (MCCSR.OIE=0) ENABLE W D GH A L T 1 ) 1 W ATCHDO G RE SET OSCILLATOR OFF PERIPHERALS 2) OFF CP U OFF I[1:0] BITS 10 0 W ATCHDOG DISABLE

N RE SET N Y INTERRUPT 3) Y OSCILLATOR ON PERIPHERALS OFF CP U ON I[1:0] BITS XX 4) 256 OR 4096 CPU CLOCK C YCL E DE LAY OSCILLATOR ON PERIPHERALS ON CP U ON I[1:0] BITS XX 4)

HA LT IN STRUCTION [MCCS R.OIE=0]

Notes: 1. WDGHALT is an option bit. See option byte section for more details. 2. Peripheral clocked with an external clock source can still be active. 3. Only some specific interrupts can exit the MCU from HALT mode (such as external interrupt). Refer to Table 8, "Interrupt Mapping," on page 44 for more details. 4. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of the interrupt routine and recovered when the CC register is popped.

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9 I/O PORTS
9.1 INTRODUCTION The I/O ports offer different functional modes: transfer of data through digital inputs and outputs and for specific pins: external interrupt generation alternate signal input/output for the on-chip peripherals. An I/O port contains up to 8 pins. Each pin can be programmed independently as digital input (with or without interrupt generation) or digital output. 9.2 FUNCTIONAL DESCRIPTION Each port has two main registers: Data Register (DR) Data Direction Register (DDR) and one optional register: Option Register (OR) Each I/O pin may be programmed using the corresponding register bits in the DDR and OR registers: Bit X corresponding to pin X of the port. The same correspondence is used for the DR register. The following description takes into account the OR register, (for specific ports which do not provide this register refer to the I/O Port Implementation section). The generic I/O block diagram is shown in Figure 32 9.2.1 Input Modes The input configuration is selected by clearing the corresponding DDR register bit. In this case, reading the DR register returns the digital value applied to the external I/O pin. Different input modes can be selected by software through the OR register. Notes: 1. Writing the DR register modifies the latch value but does not affect the pin status. 2. When switching from input to output mode, the DR register has to be written first to drive the correct level on the pin as soon as the port is configured as an output. 3. Do not use read/modify/write instructions (BSET or BRES) to modify the DR register as this might corrupt the DR content for I/Os configured as input. External interrupt function When an I/O is configured as Input with Interrupt, an event on this I/O can generate an external interrupt request to the CPU. Each pin can independently generate an interrupt request. The interrupt sensitivity is independently programmable using the sensitivity bits in the EICR register. Each external interrupt vector is linked to a dedicated group of I/O port pins (see pinout description and interrupt section). If several input pins are selected simultaneously as interrupt sources, these are first detected according to the sensitivity bits in the EICR register and then logically ORed. The external interrupts are hardware interrupts, which means that the request latch (not accessible directly by the application) is automatically cleared when the corresponding interrupt vector is fetched. To clear an unwanted pending interrupt by software, the sensitivity bits in the EICR register must be modified. 9.2.2 Output Modes The output configuration is selected by setting the corresponding DDR register bit. In this case, writing the DR register applies this digital value to the I/O pin through the latch. Then reading the DR register returns the previously stored value. Two different output modes can be selected by software through the OR register: Output push-pull and open-drain. DR register value and output pin status:
DR 0 1 Push-pull VS S VDD Open-drain Vss Floating

9.2.3 Alternate Functions When an on-chip peripheral is configured to use a pin, the alternate function is automatically selected. This alternate function takes priority over the standard I/O programming. When the signal is coming from an on-chip peripheral, the I/O pin is automatically configured in output mode (push-pull or open drain according to the peripheral). When the signal is going to an on-chip peripheral, the I/O pin must be configured in input mode. In this case, the pin state is also digitally readable by addressing the DR register. Note: Input pull-up configuration can cause unexpected value at the input of the alternate peripheral input. When an on-chip peripheral use a pin as input and output, this pin has to be configured in input floating mode.

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I/O PORTS (Cont'd) Figure 32. I/O Port General Block Diagram
ALTERNATE OU TPUT

REGISTER ACCESS

1 0

VDD

P-BUFFER (see table below) PULL-UP (see table below) VDD

ALTERNATE ENA BLE DR

DDR PULL-UP COND ITION If implemented OR SEL N-BUFFER DDR SEL CMO S SCHMITT TRIG GER ANALOG INPUT DIODES (see table below) PAD

OR

EXTERN AL INTERR UPT SOURCE (eix)

Table 10. I/O Port Mode Options
Configuration Mode Input Floating with/without Interrupt Pull-up with/without Interrupt Push-pull Open Drain (logic level) True Open Drain Pull-Up Off On Off NI P-Buffer Off On Off NI On On Diodes to VDD to VSS

O u tput

Legend: NI - not implemented Off - implemented not activated On - implemented and activated

DATA BUS

DR SEL

1 0

ALTERNATE INPUT

NI (see note)

Note: The diode to VDD is not implemented in the true open drain pads. A local protection between the pad and VSS is implemented to protect the device against positive stress.

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I/O PORTS (Cont'd) Table 11. I/O Port Configurations
Hardware Configuration
NOT IMPLEMENTED IN TRUE OPEN DRAIN I/O PORTS VDD RPU PAD PULL-UP CONDITION DR REGISTER ACCESS

DR REGISTER

W DATA BUS R

INPUT 1)

ALTERNATE INPUT EXTERNAL INTERRUPT SOURCE (eix) INTERRUPT CONDITION ANALOG INPUT NOT IMPLEMENTED IN TRUE OPEN DRAIN I/O PORTS

OPEN-DRAIN O UTPUT 2 )

VDD RPU

DR REGISTER ACCESS

PAD

DR REGISTER

R/W

DATA BUS

ALTERNATE ENABLE

ALTERNATE OUTPUT

P U S H - P U L L OU T P U T 2 )

NOT IMPLEMENTED IN TRUE OPEN DRAIN I/O PORTS

VDD RPU

DR REGISTER ACCESS

PAD

DR REGISTER

R/W

DATA BUS

ALTERNATE ENABLE

ALTERNATE OUTPUT

Notes: 1. When the I/O port is in input configuration and the associated alternate function is enabled as an output, reading the DR register will read the alternate function output status. 2. When the I/O port is in output configuration and the associated alternate function is enabled as an input, the alternate function reads the pin status given by the DR register content.

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I/O PORTS (Cont'd) CAUTION: The alternate function must not be activated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts. Analog alternate function When the pin is used as an ADC input, the I/O must be configured as floating input. The analog multiplexer (controlled by the ADC registers) switches the analog voltage present on the selected pin to the common analog rail which is connected to the ADC input. It is recommended not to change the voltage level or loading on any port pin while conversion is in progress. Furthermore it is recommended not to have clocking pins located close to a selected analog pin. WARNING: The analog input voltage level must be within the limits stated in the absolute maximum ratings. 9.3 I/O PORT IMPLEMENTATION The hardware implementation on each I/O port depends on the settings in the DDR and OR registers and specific feature of the I/O port such as ADC Input or true open drain. Switching these I/O ports from one state to another should be done in a sequence that prevents unwanted side effects. Recommended safe transitions are illustrated in Figure 33 on page 57. Other transitions are potentially risky and should be avoided, since they are likely to present unwanted side-effects such as spurious interrupt generation.

Figure 33. Interrupt I/O Port State Transitions
01
INPUT floating/pull-up interrupt

00
INPUT floating (reset state)

10
OUTPUT open-drain

11
OUTPUT push-pull

XX

= DDR, OR

9.4 LOW POWER MODES
Mode WAIT H AL T Description No effect on I/O ports. External interrupts cause the device to exit from WAIT mode. No effect on I/O ports. External interrupts cause the device to exit from HALT mode.

9.5 INTERRUPTS The external interrupt event generates an interrupt if the corresponding configuration is selected with DDR and OR registers and the interrupt mask in the CC register is not active (RIM instruction).
Interrupt Event External interrupt on