A special session at DAC 2006 is dedicated to the debate and discussion of how the electronics industry will successfully compete in the IC nanometer race. Philippe Magarshack, Front-End Technology and Manufacturing Vice-President and Central CAD & Design Solutions General Manager at STMicroelectronics, has been invited on a panel to discuss how ST is striving to improve its chances of success in creating ICs in the nanometer age.

Another panel will look at the industry cooperation that has established common language and methodology standards to support Electronic System Level (ESL) modeling, design, and verification using SystemC, SystemC Verification (SCV), and SystemC Transaction Level Modeling (TLM). Completely absent, however, is a common, standard methodology for ESL design and verification itself. Pascal Urard, High Level Synthesis Manager in the Central CAD & Design Solutions organization, will join other ESL users and suppliers to look at what is being done today and to identify what more is needed to address increasing system complexity.

With the ongoing trend towards more and more digitization in applications ranging from multimedia to telecommunications, Daniel Saias from ST’s Home, Personal, Communication Sector will challenge panelists who question the future need for analog circuits in scaled technologies.

ST will also present a number of interesting papers on its top-tier design efforts. In high-performance simulation of transaction level and dataflow models, ST experts, in partnership with researchers from the University of Milan and Catania, will present a Unified Modeling Language (UML)-SystemC modeling tool with full roundtrip capability.

A paper co-authored by ST and research partners at LIRMM (Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier), France, will address the critical area of security in system design, by reporting on ciphering and integrity checking of data exchanged between a System-on-Chip (SoC) and its external memory.

In an invited session, ST will focus on system-level specification and co-design of embedded software for the Nomadik^TM multimedia processor to help attendees understand the new challenges created by designing complex billion-transistor devices. These designs, which span system and architecture levels all the way through physical implementation, arise across the flow of EDA tools.

Another primary concern in the design of digital-signal-processing-oriented applications is bridging the system to RTL (Register Transfer Level) verification gap. In this field, STMicroelectronics together with Calypto Design Systems, will propose a methodology based on high-level synthesis and sequential equivalence checking, which allows engineers to design at higher levels of abstraction while keeping the various models synchronized at all stages of development.

ST was also selected to chair the discussion on how MPSoC (Multi-Processor System-on-Chip) design tools can help solve some of problems associated with the design and verification of the emerging class of SoCs that have instantiations of multiple processors.

Further information about DAC 2006 is available at: www.dac.com/43rd/index.html